From 29de80758f0c0a0df4f9da51c10d7b3109a664a4 Mon Sep 17 00:00:00 2001 From: Mary Bennett Date: Thu, 30 May 2024 16:06:59 +0100 Subject: RISC-V: Add support for XCVmem extension in CV32E40P Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvmem` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Note XCVmem as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-mem-fail-march.d: New test. * testsuite/gas/riscv/cv-mem-fail-march.l: New test. * testsuite/gas/riscv/cv-mem-fail-march.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-mem-lbpost.d: New test. * testsuite/gas/riscv/cv-mem-lbpost.s: New test. * testsuite/gas/riscv/cv-mem-lbrr.d: New test. * testsuite/gas/riscv/cv-mem-lbrr.s: New test. * testsuite/gas/riscv/cv-mem-lbrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lbrrpost.s: New test. * testsuite/gas/riscv/cv-mem-lbupost.d: New test. * testsuite/gas/riscv/cv-mem-lbupost.s: New test. * testsuite/gas/riscv/cv-mem-lburr.d: New test. * testsuite/gas/riscv/cv-mem-lburr.s: New test. * testsuite/gas/riscv/cv-mem-lburrpost.d: New test. * testsuite/gas/riscv/cv-mem-lburrpost.s: New test. * testsuite/gas/riscv/cv-mem-lhpost.d: New test. * testsuite/gas/riscv/cv-mem-lhpost.s: New test. * testsuite/gas/riscv/cv-mem-lhrr.d: New test. * testsuite/gas/riscv/cv-mem-lhrr.s: New test. * testsuite/gas/riscv/cv-mem-lhrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lhrrpost.s: New test. * testsuite/gas/riscv/cv-mem-lhupost.d: New test. * testsuite/gas/riscv/cv-mem-lhupost.s: New test. * testsuite/gas/riscv/cv-mem-lhurr.d: New test. * testsuite/gas/riscv/cv-mem-lhurr.s: New test. * testsuite/gas/riscv/cv-mem-lhurrpost.d: New test. * testsuite/gas/riscv/cv-mem-lhurrpost.s: New test. * testsuite/gas/riscv/cv-mem-lwpost.d: New test. * testsuite/gas/riscv/cv-mem-lwpost.s: New test. * testsuite/gas/riscv/cv-mem-lwrr.d: New test. * testsuite/gas/riscv/cv-mem-lwrr.s: New test. * testsuite/gas/riscv/cv-mem-lwrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lwrrpost.s: New test. * testsuite/gas/riscv/cv-mem-sbpost.d: New test. * testsuite/gas/riscv/cv-mem-sbpost.s: New test. * testsuite/gas/riscv/cv-mem-sbrr.d: New test. * testsuite/gas/riscv/cv-mem-sbrr.s: New test. * testsuite/gas/riscv/cv-mem-sbrrpost.d: New test. * testsuite/gas/riscv/cv-mem-sbrrpost.s: New test. * testsuite/gas/riscv/cv-mem-shpost.d: New test. * testsuite/gas/riscv/cv-mem-shpost.s: New test. * testsuite/gas/riscv/cv-mem-shrr.d: New test. * testsuite/gas/riscv/cv-mem-shrr.s: New test. * testsuite/gas/riscv/cv-mem-shrrpost.d: New test. * testsuite/gas/riscv/cv-mem-shrrpost.s: New test. * testsuite/gas/riscv/cv-mem-swpost.d: New test. * testsuite/gas/riscv/cv-mem-swpost.s: New test. * testsuite/gas/riscv/cv-mem-swrr.d: New test. * testsuite/gas/riscv/cv-mem-swrr.s: New test. * testsuite/gas/riscv/cv-mem-swrrpost.d: New test. * testsuite/gas/riscv/cv-mem-swrrpost.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvmem string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVmem. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVmem. (enum riscv_insn_class): Add the XCVmem instruction class. opcodes/ChangeLog: * riscv-opc.c: Add XCVmem instructions. --- include/opcode/riscv-opc.h | 49 ++++++++++++++++++++++++++++++++++++++++++++++ include/opcode/riscv.h | 1 + 2 files changed, 50 insertions(+) (limited to 'include') diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 0661565..cd957ef 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2477,6 +2477,55 @@ #define MASK_CV_BNEIMM 0x707f #define MATCH_CV_BEQIMM 0x600b #define MASK_CV_BEQIMM 0x707f +/* Vendor-specific (CORE-V) Xcvmem instructions. */ +#define MASK_CV_LBPOST 0x707f +#define MATCH_CV_LBPOST 0xb +#define MASK_CV_LBUPOST 0x707f +#define MATCH_CV_LBUPOST 0x400b +#define MASK_CV_LHPOST 0x707f +#define MATCH_CV_LHPOST 0x100b +#define MASK_CV_LHUPOST 0x707f +#define MATCH_CV_LHUPOST 0x500b +#define MASK_CV_LWPOST 0x707f +#define MATCH_CV_LWPOST 0x200b +#define MASK_CV_LBRRPOST 0xfe00707f +#define MATCH_CV_LBRRPOST 0x302b +#define MASK_CV_LBURRPOST 0xfe00707f +#define MATCH_CV_LBURRPOST 0x1000302b +#define MASK_CV_LHRRPOST 0xfe00707f +#define MATCH_CV_LHRRPOST 0x200302b +#define MASK_CV_LHURRPOST 0xfe00707f +#define MATCH_CV_LHURRPOST 0x1200302b +#define MASK_CV_LWRRPOST 0xfe00707f +#define MATCH_CV_LWRRPOST 0x400302b +#define MASK_CV_LBRR 0xfe00707f +#define MATCH_CV_LBRR 0x800302b +#define MASK_CV_LBURR 0xfe00707f +#define MATCH_CV_LBURR 0x1800302b +#define MASK_CV_LHRR 0xfe00707f +#define MATCH_CV_LHRR 0xa00302b +#define MASK_CV_LHURR 0xfe00707f +#define MATCH_CV_LHURR 0x1a00302b +#define MASK_CV_LWRR 0xfe00707f +#define MATCH_CV_LWRR 0xc00302b +#define MASK_CV_SBPOST 0x707f +#define MATCH_CV_SBPOST 0x2b +#define MASK_CV_SHPOST 0x707f +#define MATCH_CV_SHPOST 0x102b +#define MASK_CV_SWPOST 0x707f +#define MATCH_CV_SWPOST 0x202b +#define MASK_CV_SBRRPOST 0xfe00707f +#define MATCH_CV_SBRRPOST 0x2000302b +#define MASK_CV_SHRRPOST 0xfe00707f +#define MATCH_CV_SHRRPOST 0x2200302b +#define MASK_CV_SWRRPOST 0xfe00707f +#define MATCH_CV_SWRRPOST 0x2400302b +#define MASK_CV_SBRR 0xfe00707f +#define MATCH_CV_SBRR 0x2800302b +#define MASK_CV_SHRR 0xfe00707f +#define MATCH_CV_SHRR 0x2a00302b +#define MASK_CV_SWRR 0xfe00707f +#define MATCH_CV_SWRR 0x2c00302b /* Vendor-specific (T-Head) XTheadBa instructions. */ #define MATCH_TH_ADDSL 0x0000100b #define MASK_TH_ADDSL 0xf800707f diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f6e6dae..0653ae5 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -494,6 +494,7 @@ enum riscv_insn_class INSN_CLASS_XCVALU, INSN_CLASS_XCVELW, INSN_CLASS_XCVBI, + INSN_CLASS_XCVMEM, INSN_CLASS_XTHEADBA, INSN_CLASS_XTHEADBB, INSN_CLASS_XTHEADBS, -- cgit v1.1