From 4e2b18982ade10897e62590896a1dec496269877 Mon Sep 17 00:00:00 2001
From: Jim Wilson <jimw@sifive.com>
Date: Mon, 17 Sep 2018 11:43:08 -0700
Subject: RISC-V: bge[u] should get higher priority than ble[u].

2018-09-17  Kito Cheng  <kito@andestech.com>
gas/
	* testsuite/gas/riscv/bge.d: New.
	* testsuite/gas/riscv/bge.s: Likewise.
opcodes/
	* riscv-opc.c (riscv_opcodes): Adjust the order of ble and
	  bleu.
---
 gas/ChangeLog                 |  5 +++++
 gas/testsuite/gas/riscv/bge.d | 13 +++++++++++++
 gas/testsuite/gas/riscv/bge.s |  5 +++++
 3 files changed, 23 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/bge.d
 create mode 100644 gas/testsuite/gas/riscv/bge.s

(limited to 'gas')

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3e76800..0a4c566 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2018-09-17  Kito Cheng  <kito@andestech.com>
+
+	* testsuite/gas/riscv/bge.d: New.
+	* testsuite/gas/riscv/bge.s: Likewise.
+
 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR gas/23670
diff --git a/gas/testsuite/gas/riscv/bge.d b/gas/testsuite/gas/riscv/bge.d
new file mode 100644
index 0000000..b3db91c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bge.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ 	]+0:[ 	]+00c5d063[ 	]+bge[ 	]+a1,a2,0 \<foo\>
+[ 	]+4:[ 	]+feb65ee3[ 	]+bge[ 	]+a2,a1,0 \<foo\>
+[ 	]+8:[ 	]+fec5fce3[ 	]+bgeu[ 	]+a1,a2,0 \<foo\>
+[ 	]+c:[ 	]+feb67ae3[ 	]+bgeu[ 	]+a2,a1,0 \<foo\>
diff --git a/gas/testsuite/gas/riscv/bge.s b/gas/testsuite/gas/riscv/bge.s
new file mode 100644
index 0000000..a28d25e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bge.s
@@ -0,0 +1,5 @@
+foo:
+	bge a1, a2, foo
+	ble a1, a2, foo
+	bgeu a1, a2, foo
+	bleu a1, a2, foo
-- 
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