From fc6141f097056f830a412afebed8d81a9d72b696 Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Wed, 20 Jun 2018 12:38:10 +0100 Subject: Change the ARM assembler's ADR and ADRl pseudo-ops so that they will only set the bottom bit of imported thumb function symbols if the -mthumb-interwork option is active. For more information see the email thread starting here: https://www.sourceware.org/ml/binutils/2018-05/msg00348.html PR 21458 * tc-arm.c (do_adr): Only set the bottom bit of an imported thumb function symbol address if -mthumb-interwork is active. (do_adrl): Likewise. * doc/c-arm.texi: Update descriptions of the -mthumb-interwork option and the ADR and ADRL pseudo-ops. * NEWS: Mention the new behaviour of the ADR and ADRL pseudo-ops. * testsuite/gas/arm/pr21458.d: Add -mthumb-interwork option to assembler command line. * testsuite/gas/arm/adr.d: Likewise. * testsuite/gas/arm/adrl.d: Likewise. --- gas/doc/c-arm.texi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'gas/doc/c-arm.texi') diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index cd533ca..4683b8a 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -318,7 +318,8 @@ instructions; that is, it should behave as though the file starts with a @cindex @code{-mthumb-interwork} command line option, ARM @item -mthumb-interwork This option specifies that the output generated by the assembler should -be marked as supporting interworking. +be marked as supporting interworking. It also affects the behaviour +of the @code{ADR} and @code{ADRL} pseudo opcodes. @cindex @code{-mimplicit-it} command line option, ARM @item -mimplicit-it=never @@ -1061,6 +1062,16 @@ out of range, or if it is not defined in the same file (and section) as the ADR instruction, then an error will be generated. This instruction will not make use of the literal pool. +If @var{label} is a thumb function symbol, and thumb interworking has +been enabled via the @option{-mthumb-interwork} option then the bottom +bit of the value stored into @var{register} will be set. This allows +the following sequence to work as expected: + +@smallexample + adr r0, thumb_function + blx r0 +@end smallexample + @cindex @code{ADRL reg,