From f3f6c0df60c4e8a6c3409db4f23f2cdec5a9d41c Mon Sep 17 00:00:00 2001
From: Victor Do Nascimento <victor.donascimento@arm.com>
Date: Tue, 12 Sep 2023 13:10:14 +0100
Subject: aarch64: Add LSE128 instructions

Implement, together with the necessary tests, the following new LSE128
atomic instructions:

  * Atomic bit clear on quadword in memory (ldclrp{a|l|al});
  * Atomic bit set on quadword in memory (ldsetp{a|l|al});
  * Swap quadword in memory (swpp{a|l|al});

gas/ChangeLog:

	* testsuite/gas/aarch64/lse128-atomic.d: New.
	* testsuite/gas/aarch64/lse128-atomic.s: Likewise.

opcodes/ChangeLog:

	* aarch64-tbl.h (ldclrp): new _LSE128_INSN entry.
	(ldclrpa):  Likewise.
	(ldclrpal): Likewise.
	(ldclrpl): Likewise.
	(ldsetp): Likewise.
	(ldsetpa): Likewise.
	(ldsetpal): Likewise.
	(ldsetpl): Likewise.
	(swpp): Likewise.
	(swppa): Likewise.
	(swppal): Likewise.
	(swppl): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
---
 gas/NEWS | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'gas/NEWS')

diff --git a/gas/NEWS b/gas/NEWS
index a6ac839..ddf48fc 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for 128-bit Atomic Instructions (LSE128) for AArch64.
+
 * Add support for Guarded Control Stack (GCS) for AArch64.
 
 * Add support for AArch64 Check Feature Status Extension (CHK).
-- 
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