From d95014a2ef6e9aee927c13960fa37e509d46eb32 Mon Sep 17 00:00:00 2001 From: Yao Qi Date: Thu, 12 Jan 2017 09:40:41 +0000 Subject: Return -1 on memory error in print_insn_msp430 Disassemblers in opcodes return -1 on memory error, but msp430 doesn't follow this convention. If I change GDB not to throw exception in disassemble_info.memory_error_func and rely on the return value of disassembler, I'll get the following output. (gdb) disassemble 0x0,+8 Dump of assembler code from 0x0 to 0x8: 0x00000000: .word 0xffff; ???? 0x00000002: .word 0xffff; ???? 0x00000004: .word 0xffff; ???? 0x00000006: .word 0xffff; ???? End of assembler dump. This patch teaches print_insn_msp430 and its callees to return -1 on memory error. opcodes: 2017-01-12 Yao Qi * msp430-dis.c (msp430_singleoperand): Return -1 if msp430dis_opcode_signed returns false. (msp430_doubleoperand): Likewise. (msp430_branchinstr): Return -1 if msp430dis_opcode_unsigned returns false. (msp430x_calla_instr): Likewise. (print_insn_msp430): Likewise. --- opcodes/ChangeLog | 10 +++++ opcodes/msp430-dis.c | 103 ++++++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 99 insertions(+), 14 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8494c51..5d670f6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2017-01-12 Yao Qi + + * msp430-dis.c (msp430_singleoperand): Return -1 if + msp430dis_opcode_signed returns false. + (msp430_doubleoperand): Likewise. + (msp430_branchinstr): Return -1 if + msp430dis_opcode_unsigned returns false. + (msp430x_calla_instr): Likewise. + (print_insn_msp430): Likewise. + 2017-01-05 Nick Clifton PR 20946 diff --git a/opcodes/msp430-dis.c b/opcodes/msp430-dis.c index 9c62193..58d31df 100644 --- a/opcodes/msp430-dis.c +++ b/opcodes/msp430-dis.c @@ -270,6 +270,8 @@ msp430_singleoperand (disassemble_info *info, (long)((addr + 2 + dst) & 0xfffff)); } } + else + return -1; } else if (regd == 2) { @@ -285,6 +287,8 @@ msp430_singleoperand (disassemble_info *info, sprintf (op, "&0x%05x", dst & 0xfffff); } } + else + return -1; } else { @@ -300,6 +304,8 @@ msp430_singleoperand (disassemble_info *info, } sprintf (op, "%d(r%d)", dst, regd); } + else + return -1; } } break; @@ -346,6 +352,8 @@ msp430_singleoperand (disassemble_info *info, sprintf (comm, "#0x%05x", dst); } } + else + return -1; } else * cycles = print_as3_reg_name (regd, op, comm, 1, 1, 3); @@ -370,6 +378,8 @@ msp430_singleoperand (disassemble_info *info, (long)((addr + 2 + dst) & 0xfffff)); } } + else + return -1; } else if (regd == 2) { @@ -384,6 +394,8 @@ msp430_singleoperand (disassemble_info *info, sprintf (op, "&0x%05x", dst & 0xfffff); } } + else + return -1; } else if (regd == 3) { @@ -407,6 +419,8 @@ msp430_singleoperand (disassemble_info *info, if (dst > 9 || dst < 0) sprintf (comm, "%05x", dst); } + else + return -1; } } break; @@ -511,6 +525,8 @@ msp430_doubleoperand (disassemble_info *info, (long)((addr + 2 + dst) & 0xfffff)); } } + else + return -1; } else if (regd == 2) { @@ -526,6 +542,8 @@ msp430_doubleoperand (disassemble_info *info, if (src != dst) return 0; } + else + return -1; cmd_len += 4; *cycles = 6; sprintf (op1, "&0x%04x", PS (dst)); @@ -535,6 +553,8 @@ msp430_doubleoperand (disassemble_info *info, sprintf (op1, "&0x%05x", dst & 0xfffff); } } + else + return -1; } else { @@ -553,6 +573,8 @@ msp430_doubleoperand (disassemble_info *info, if (dst > 9 || dst < -9) sprintf (comm1, "#0x%05x", dst); } + else + return -1; } } @@ -613,6 +635,8 @@ msp430_doubleoperand (disassemble_info *info, sprintf (comm1, "0x%05x", dst & 0xfffff); } } + else + return -1; } else * cycles = print_as3_reg_name (regs, op1, comm1, 1, 1, 2); @@ -640,6 +664,8 @@ msp430_doubleoperand (disassemble_info *info, (long) ((addr + 2 + dst) & 0xfffff)); } } + else + return -1; } else if (regs == 2) { @@ -658,6 +684,8 @@ msp430_doubleoperand (disassemble_info *info, * comm1 = 0; } } + else + return -1; } else if (regs == 3) { @@ -683,6 +711,8 @@ msp430_doubleoperand (disassemble_info *info, if (dst > 9 || dst < -9) sprintf (comm1, "0x%05x", dst); } + else + return -1; } } @@ -728,6 +758,8 @@ msp430_doubleoperand (disassemble_info *info, (long)((addr + cmd_len + dst) & 0xfffff)); } } + else + return -1; cmd_len += 2; } else if (regd == 2) @@ -743,6 +775,8 @@ msp430_doubleoperand (disassemble_info *info, sprintf (op2, "&0x%05x", dst & 0xfffff); } } + else + return -1; } else { @@ -761,6 +795,8 @@ msp430_doubleoperand (disassemble_info *info, } sprintf (op2, "%d(r%d)", dst, regd); } + else + return -1; } } @@ -821,6 +857,8 @@ msp430_branchinstr (disassemble_info *info, cmd_len += 2; sprintf (op1, "#0x%04x", PS (udst)); } + else + return -1; } else * cycles = print_as3_reg_name (regs, op1, comm1, 1, 1, 2); @@ -840,6 +878,8 @@ msp430_branchinstr (disassemble_info *info, sprintf (comm1, "PC rel. 0x%04x", PS ((short) addr + 2 + dst)); } + else + return -1; } else if (regs == 2) { @@ -849,6 +889,8 @@ msp430_branchinstr (disassemble_info *info, cmd_len += 2; sprintf (op1, "&0x%04x", PS (udst)); } + else + return -1; } else if (regs == 3) { @@ -864,6 +906,8 @@ msp430_branchinstr (disassemble_info *info, cmd_len += 2; sprintf (op1, "%d(r%d)", dst, regs); } + else + return -1; } } @@ -903,6 +947,8 @@ msp430x_calla_instr (disassemble_info * info, else sprintf (comm1, "0x%05x", dst); } + else + return -1; break; case 6: /* CALLA @Rdst */ @@ -923,6 +969,8 @@ msp430x_calla_instr (disassemble_info * info, sprintf (op1, "&%d", (ureg << 16) + udst); sprintf (comm1, "0x%05x", (ureg << 16) + udst); } + else + return -1; break; case 9: /* CALLA pcrel-sym */ @@ -934,6 +982,8 @@ msp430x_calla_instr (disassemble_info * info, sprintf (comm1, "PC rel. 0x%05lx", (long) (addr + 2 + dst + (reg << 16))); } + else + return -1; break; case 11: /* CALLA #imm20 */ @@ -944,6 +994,8 @@ msp430x_calla_instr (disassemble_info * info, sprintf (op1, "#%d", (ureg << 16) + udst); sprintf (comm1, "0x%05x", (ureg << 16) + udst); } + else + return -1; break; default: @@ -969,10 +1021,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) unsigned short bits; if (! msp430dis_opcode_unsigned (addr, info, &insn, NULL)) - { - prin (stream, ".word 0xffff; ????"); - return 2; - } + return -1; if (((int) addr & 0xffff) > 0xffdf) { @@ -989,11 +1038,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) extension_word = insn; addr += 2; if (! msp430dis_opcode_unsigned (addr, info, &insn, NULL)) - { - prin (stream, ".word 0x%04x, 0xffff; ????", - extension_word); - return 4; - } + return -1; } for (opcode = msp430_opcodes; opcode->name; opcode++) @@ -1011,9 +1056,13 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) && (insn & 0x000f) == 0 && (insn & 0x0080) == 0) { - cmd_len += + int ret = msp430_branchinstr (info, opcode, addr, insn, op1, comm1, &cycles); + + if (ret == -1) + return -1; + cmd_len += ret; if (cmd_len) break; } @@ -1022,10 +1071,14 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) { int n; int reg; + int ret; case 4: - cmd_len += msp430x_calla_instr (info, addr, insn, - op1, comm1, & cycles); + ret = msp430x_calla_instr (info, addr, insn, + op1, comm1, & cycles); + if (ret == -1) + return -1; + cmd_len += ret; break; case 5: /* PUSHM/POPM */ @@ -1080,6 +1133,8 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) if (n > 9 || n < 0) sprintf (comm1, "0x%05x", n); } + else + return -1; cmd_len = 4; } sprintf (op2, "r%d", reg); @@ -1120,6 +1175,8 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) if (strcmp (opcode->name, "bra") != 0) sprintf (op2, "r%d", reg); } + else + return -1; break; case 3: /* MOVA x(Rsrc), Rdst */ @@ -1139,6 +1196,8 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) sprintf (comm1, "0x%05x", n); } } + else + return -1; break; case 6: /* MOVA Rsrc, &abs20 */ @@ -1152,6 +1211,8 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) if (reg > 9 || reg < 0) sprintf (comm2, "0x%05x", reg); } + else + return -1; break; case 7: /* MOVA Rsrc, x(Rdst) */ @@ -1169,6 +1230,8 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) sprintf (comm2, "0x%05x", n); } } + else + return -1; break; case 8: /* MOVA #imm20, Rdst */ @@ -1185,6 +1248,8 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) if (strcmp (opcode->name, "bra") != 0) sprintf (op2, "r%d", reg); } + else + return -1; break; case 12: /* MOVA Rsrc, Rdst */ @@ -1206,15 +1271,21 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) switch (opcode->insn_opnumb) { + int ret; + case 0: cmd_len += msp430_nooperands (opcode, addr, insn, comm1, &cycles); break; case 2: - cmd_len += + ret = msp430_doubleoperand (info, opcode, addr, insn, op1, op2, comm1, comm2, extension_word, &cycles); + + if (ret == -1) + return -1; + cmd_len += ret; if (insn & BYTE_OPERATION) { if (extension_word != 0 && ((extension_word & BYTE_OPERATION) == 0)) @@ -1235,10 +1306,14 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) break; case 1: - cmd_len += + ret = msp430_singleoperand (info, opcode, addr, insn, op1, comm1, extension_word, &cycles); + + if (ret == -1) + return -1; + cmd_len += ret; if (extension_word && (strcmp (opcode->name, "swpb") == 0 || strcmp (opcode->name, "sxt") == 0)) -- cgit v1.1