From cc6aaa31491cacb485e07ac9adfe4f7d971b2ae2 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 21 Dec 2023 01:30:20 -0500 Subject: sim: cr16: add missing break statement Doesn't seem to make sense for this to fall through (although I'm not an expert in this ISA). --- sim/cr16/interp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sim/cr16/interp.c b/sim/cr16/interp.c index 9a2363a..0fa9a91 100644 --- a/sim/cr16/interp.c +++ b/sim/cr16/interp.c @@ -288,6 +288,7 @@ get_operands (operand_desc *s, uint64_t ins, int isize, int nops) OP[i] = (ins) & 0x3FFF; OP[++i] = (ins >> 14) & 0x1; /* get 1 bit for index-reg. */ OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */ + break; case rindex7_abs20: case rindex8_abs20: OP[i] = (ins) & 0xFFFFF; -- cgit v1.1