Age | Commit message (Collapse) | Author | Files | Lines |
|
* sim-fpu.h (SIM_FPU_IS_QNAN): Replace "Quite" with "Quiet" in
the comment for this enumerator.
|
|
* sim-fpu.h: Fix comment about sim_fpu_* constants.
|
|
* igen.c (main): Change -I to add include paths for :include:
files.
Implement -G as per sim/igen, with just gen-icache=N support.
Call load_insn_table() with the built include path.
* ld-insn.c (parse_include_entry): New. Load an :include: file.
(load_insn_table): New `includes' argument. Look for :include:
entries and call parse_include_entry() for them.
(main): Adjust load_insn_table() call.
* ld-insn.h (model_include_fields): New enum.
(load_insn_table): Update prototype.
* table.c (struct _open_table, struct _table): Rework
structures to handle included files.
(table_push): Move the guts of table_open() here.
* table.c (struct _open table, struct table): Make table object an
indirect ptr to the current table file.
(current_line, new_table_entry, next_line): Make file arg type
open_table.
(table_open): Use table_push.
(table_entry_read): Point variable file at current table, at eof, pop
last open table.
* misc.h (NZALLOC): New macro. From sim/igen.
* table.h, table.c (table_push): New function.
|
|
|
|
|
|
|
|
bytes wide return 0 for the other bytes.
|
|
(LSEXTRACTED64): Likewise.
* bits.h (_LSB_POS, _LSMASKn, LSMASK64): New macros from
sim/common/sim-bits.h
(LSMASKED64, LSEXTRACTED64): New functions definitions.
* Makefile.in (sim-bits.o): Remove target.
* main.c (zalloc): Fix typo in error message.
|
|
|
|
|
|
|
|
|
|
(sim_io_error): New function.
* sim_calls.c: (sim_io_error): New function.
|
|
|
|
* Makefile.in (LIB_OBJ): Add @sim_fpu@.
(ICACHE_CFLAGS, SEMANTICS_CFLAGS): New variables.
(icache.o, semantics.o): Add new ICACHE_FLAGS & SEMANTICS_FLAGS.
(sim-fpu.o, sim-bits.o, tconfig.h): New targets.
* configure.in: Rename INLINE_LOCALS to PSIM_INLINE_LOCALS. Add a
check for sim/common/sim-fpu.c. Output sim_fpu and sim_fpu_cflags.
* configure: Regenerate.
* device.h (device_find_integer_array_property): Match function definition.
* gen-icache.c (print_icache_internal_function_declaration): Rename
INLINE_ICACHE to PSIM_INLINE_ICACHE.
* gen-idecode.c (print_idecode_run_function_header): Rename INLINE_IDECODE
to PSIM_INLINE_IDECODE.
* gen-semantics.c (print_semantic_function_header): Rename
EXTERN_SEMANTICS to PSIM_EXTERN_SEMANTICS.
* gen-support.c (print_support_function_name): Rename INLINE_SUPPORT to
PSIM_INLINE_SUPPORT.
* igen.c (print_function_name): Also escape `(' and `)'.
(gen_semantics_h): Rename EXTERN_SEMANTICS to PSIM_EXTERN_SEMANTICS.
(gen_semantics_c): Likewise. Also output includes for "sim-fpu.h"
* inline.h (INLINE_SIM_ENDIAN): Renamed INLINE_PSIM_ENDIAN.
(EXTERN_SIM_ENDIAN): Renamed EXTERN_PSIM_ENDIAN.
(STATIC_INLINE_SIM_ENDIAN): Renamed STATIC_INLINE_PSIM_ENDIAN.
(INLINE_LOCALS): Renamed PSIM_INLINE_LOCALS.
(EXTERN_SUPPORT): Renamed PSIM_EXTERN_SUPPORT.
(INLINE_SUPPORT): Renamed PSIM_INLINE_SUPPORT.
(EXTERN_SEMANTICS): Renamed PSIM_EXTERN_SEMANTICS.
(INLINE_SEMANTICS): Renamed PSIM_INLINE_SEMANTICS.
(EXTERN_IDECODE): Renamed PSIM_EXTERN_IDECODE.
(INLINE_IDECODE): Renamed PSIM_INLINE_IDECODE.
(EXTERN_ICACHE): Renamed PSIM_EXTERN_ICACHE.
(INLINE_ICACHE): Renamed PSIM_INLINE_ICACHE.
* options.c (options_inline): Fix names.
* sim-endian-n.h: Change INLINE_SIM_ENDIAN to INLINE_PSIM_ENDIAN.
* sim-endian.h: Likewise.
* sim-main.h: New file.
* std-config.h: Rename INLINE_LOCALS to PSIM_INLINE_LOCALS.
|
|
(tmp-gencode, gencode.o, gencode): Delete targets.
(simops.h): New file.
($(BUILT_SRC_FROM_IGEN)): Do not depend on simops.h.
* gencode.c: Delete file.
|
|
* ppc-spr-table: Add SDA and PIR.
|
|
* sim-main.h (float_operation): Move enum declaration outside
of _sim_cpu struct declaration.
|
|
* Makefile.in (armemu32.o): Replace $< with autoconf recommended
$(srcdir)/....
(armemu26.o): Ditto.
|
|
|
|
* arch.c: Regenerate.
* arch.h: Regenerate.
* cpu.c: Regenerate.
* cpu.h: Regenerate.
* cpuall.h: Regenerate.
* cpux.c: Regenerate.
* cpux.h: Regenerate.
* decode.c: Regenerate.
* decode.h: Regenerate.
* decodex.c: Regenerate.
* decodex.h: Regenerate.
* model.c: Regenerate.
* modelx.c: Regenerate.
* sem-switch.c: Regenerate.
* sem.c: Regenerate.
* semx-switch.c: Regenerate.
|
|
* arch.c: Regenerate.
* arch.h: Regenerate.
* cpu.c: Regenerate.
* cpu.h: Regenerate.
* cpuall.h: Regenerate.
* decode.c: Regenerate.
* decode.h: Regenerate.
* model.c: Regenerate.
* sem-switch.c: Regenerate.
* sem.c: Regenerate.
|
|
* hw_htab.c (htab_map_binary): Don't try to map the text section
when it is empty.
* emul_chirp.c (map_over_chirp_note): Default load-base to -1 not
CHIRP_LOAD_BASE.
(emul_chirp_create): Map in the interrupt table.
|
|
|
|
Fix formatting.
|
|
memory. This was labeled as a hack to set r0/r1 with argc/argv.
|
|
* lib/sim-defs.exp (run_sim_test): Include a description such as
"assembling" or "linking" that identifies the phase a test fails
in, for easier analysis of failures.
|
|
address.
(m68hc11eepr_port_event): Fix detach/attach logic.
|
|
* interp.c (sim_resume): New function from sim-resume.c, install
the stepping event after having processed the pending ticks.
(has_stepped): Likewise.
(sim_info): Produce an output only if verbose or STATE_VERBOSE_P.
|
|
|
|
|
|
|
|
* Make-common.in (srccgen): Remove.
(CGEN_CPU_DIR): Define.
(CGEN_READ_SCM): Redefine without $(srccgen).
(CGEN_ARCH_SCM): Ditto.
(CGEN_CPU_SCM): Ditto.
(CGEN_DECODE_SCM): Ditto.
(CGEN_DESC_SCM): Ditto.
* $arch/Makefile.in: Use $(CGEN_CPU_DIR) where applicable.
|
|
|
|
pending interrupts.
* interrupts.c (interrupts_process): Keep track of the last number
of masked insn cycles.
(interrupts_initialize): Clear last number of masked insn cycles.
(interrupts_info): Report them.
(interrupts_update_pending): Compute clear and set masks of
interrupts and clear the interrupt bits before setting them
(due to SCI interrupt sharing).
* interrupts.h (struct interrupts): New members last_mask_cycles
and xirq_last_mask_cycles.
|
|
addressing modes.
|
|
|
|
|
|
|
|
|
|
Depend on targ-vals.h.
|
|
2001-04-25 Frank Ch. Eigler <fche@redhat.com>
* sim-load.c (sim_load_file): Put it back [...]
|
|
|
|
2001-04-19 Frank Ch. Eigler <fche@redhat.com>
* sim-utils.c (sim_analyze_program): Call bfd_cache_close after
we're finished with its immediate use.
* sim-load.c (sim_load_file): Ditto.
|
|
2001-04-18 matthew green <mrg@redhat.com>
* armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes.
(read_cp15_reg): Make non-static.
(XScale_cp15_LDC): Update for write_cp15_reg() change.
(XScale_cp15_MCR): Likewise.
(XScale_cp15_write_reg): Likewise.
(XScale_check_memacc): New function. Check for breakpoints being
activated by memory accesses. Does not support the Branch Target
Buffer.
(XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
(XScale_debug_moe): New function. Set the debug Method Of Entry,
if configured.
(write_cp14_reg): Reset count counter if requested.
* armdefs.h (struct ARMul_State): New members `LastTime' and
`CP14R0_CCD' used for the timer/counters.
(ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
defines for XScale registers.
(XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
(ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
(ARMul_Emulate32): Handle the clock counter and hardware instruction
breakpoints. Call XScale_set_fsr_far() for software breakpoints and
software interrupts.
(LoadMult): Call XScale_set_fsr_far() for data aborts.
(LoadSMult): Likewise.
(StoreMult): Likewise.
(StoreSMult): Likewise.
* armemu.h (write_cp15_reg): Update prototype.
* arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
(ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
register 0.
* armvirt.c (GetWord): Call XScale_check_memacc().
(PutWord): Likewise.
|
|
|
|
PENDING_FILL. Use PENDING_SCHED directly to handle the pending
set of the FCSR.
* sim-main.h (COCIDX): Remove definition; this isn't supported by
PENDING_FILL, and you can get the intended effect gracefully by
calling PENDING_SCHED directly.
|
|
|
|
2001-03-16 Frank Ch. Eigler <fche@redhat.com>
Add support for mmap-based memory regions.
* sim-memopt.c (mmap_next_fd): New global.
(sim_memory_init): Reinitialize it.
(OPTION_MEMORY_MAPFILE, memory_option_handler): Support new
"--memory-mapfile FILE" option. Check for some errors.
(do_memopt_add): Conditionally do mmap instead of malloc for
backing store of simulated memory. Check for more errors.
(do_simopt_delete, sim_memory_uninstall): Corresponding cleanup.
* sim-memopt.h (munmap_length): New member of _sim_memopt.
* configure.in: Look for mmap/fstat related functions and headers.
* config.in, configure: Regenerated.
|
|
2001-03-15 Frank Ch. Eigler <fche@redhat.com>
* sim-core.c (sim_core_map_attach): Correct overlap-related
error messages.
|