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2016-12-03Fix bugs with tbnz/tbz instructions.users/ARM/embedded-binutils-master-2016q4Jim Wilson2-3/+8
sim/aarch64 * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
2016-12-01Fix typo in ChangeLog entry.Jim Wilson1-1/+1
2016-12-01Fix bug with FP stur instructions.Jim Wilson2-6/+11
sim/aarch64 * simulator.c (fsturs): Switch use of rn and st variables. (fsturd, fsturq): Likewise
2016-11-12sim: mips: add PR info to ChangeLogMike Frysinger1-0/+2
2016-11-11sim: mips: fix dv-tx3904cpu build errorMike Frysinger2-0/+10
When building for mipstx39-rtems4.12 targets, some funcs use SD and CPU implicitly. Restore the defines for these to the local sd and cpu vars. This was broken by the clean up in commit d47f5b30d8481272e9480118bdcb. Reported-by: Joel Sherrill <joel.sherrill@oarcorp.com>
2016-11-11sim: mips: fix builds for r3900 cpus due to missing check_u64Mike Frysinger2-0/+5
2016-10-18sim: avr: move changelog entries to subdirMike Frysinger2-7/+7
2016-08-16sim: m68hc11: use standard STATIC_INLINE helperMike Frysinger2-25/+34
Rather than redefine inline locally, use the common STATIC_INLINE.
2016-08-15sim: unify symbol table handlingMike Frysinger17-170/+164
The common sim tracing code already handles loading and tracking of symbols from the target program so that it can show symbol info in trace/disassembly calls. Once we touch up the trace code and add a few API callbacks, ports don't need to do loading and searching of symbol tables themselves anymore.
2016-08-13sim: m68hc11: standardize sim_cpu namingMike Frysinger10-347/+366
We use "sim_cpu *cpu" in the sim code base, not "struct _sim_cpu" or the name "proc", so clean up this sim to follow along.
2016-08-13sim: m68hc11: fix up various prototype related warningsMike Frysinger8-12/+29
A few funcs are only used locally, so mark them static to avoid warnings due to -Wmissing-prototypes. Some funcs cast the return value wrong, so drop them (and let void * just work by default). Update some prototypes to be new style.
2016-08-13sim: cgen: constify mode_namesMike Frysinger3-2/+7
2016-08-13sim: cgen: drop unused argv/envp definitionsMike Frysinger2-8/+5
The common argv/envp are used now by all ports, so drop this old cgen fragment.
2016-08-13sim: bfin: split out common mach/model defines into arch.h [PR sim/20438]Mike Frysinger4-26/+55
The current machs.h mixes common enums with Blackfin-specific defines. This causes us troubles with header inclusion order such that we can't drop the old SIM_CPU typedef (which is duplicated in common code). By splitting the two up, we can unwind this dependency chain, and drop the old typedef. It also fixes building with older gcc versions.
2016-08-12Undo the previous change to the aarch64 sim - exporting aarch64_step() - and ↵Nick Clifton3-9/+19
instead make aarch64_run correctly process sim events. * simulator.c (aarch64_step): Revert pervious delta. (aarch64_run): Call sim_events_tick after each instruction is simulated, and if necessary call sim_events_process. * simulator.h: Revert previous delta.
2016-08-11Export the single step function from the AArch64 simulator.Nick Clifton4-9/+19
* interp.c (sim_create_inferior): Allow for being called with a NULL abfd parameter. If a bfd is provided, initialise the sim with that start address. * simulator.c (HALT_NYI): Just print out the numeric value of the instruction when not tracing. (aarch64_step): Change from static to global. * simulator.h: Add a prototype for aarch64_step().
2016-07-27Wean gdb and sim off private libbfd.h headerAlan Modra6-7/+18
The major reason this header was needed, bfd_default_set_arch_mach, has now moved to bfd.h. gdb/ * amd64-darwin-tdep.c: Don't include libbfd.h. * i386-darwin-tdep.c: Likewise. * rs6000-nat.c: Likewise. * rs6000-tdep.c: Likewise. sim/aarch64/ * memory.c: Don't include libbfd.h. sim/rl78/ * load.c: Don't include libbfd.h. (rl78_load): Don't use private iovec seek or read. sim/rx/ * load.c: Don't include libbfd.h. (rx_load): Don't use private iovec seek or read.
2016-07-21Fix typo fsqrt -> sqrtf.Nick Clifton1-1/+1
2016-07-21Use fsqrt() to calculate float (rather than double) square root.Nick Clifton2-1/+5
* simulator.c (fsqrts): Use fsqrt rather than sqrt.
2016-07-19 Update PC when simulate break instruction.Denis Chertykov2-2/+8
PR target/ 19401 * avr/interp.c (step_once): Pass break instruction address to sim_engine_halt function which writes that to PC. Remove code that follows that function call as it is unreachable.
2016-07-14Small improvements to the ARM simulator to cope with illegal binaries.Nick Clifton3-4/+13
* armemu.c (Multiply64): Only issue error messages about invalid arguments if debugging is enabled. * armos.c (ARMul_OSHandleSWI): Ignore invalid flags.
2016-06-30Add support for simulating big-endian AArch64 binaries.Jim Wilson3-9/+30
* cpustate.h: Include config.h. (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code use anonymous structs to align members. * simulator.c (aarch64_step): Use sim_core_read_buffer and endian_le2h_4 to read instruction from pc.
2016-05-06Add support for FMLA (by element) to AArch64 sim.Nick Clifton2-2/+77
* simulator.c (do_FMLA_by_element): New function. (do_vec_op2): Call it.
2016-04-27Fix a typo in the check for SNANs in the RX simulator.Nick Clifton2-1/+7
PR target/20000 * fpu.c (check_exceptions): Fix typo checking for signalling NANs.
2016-04-27Add support for the --trace-decode option to the AArch64 simulator.Nick Clifton2-7/+317
* simulator.c: Add TRACE_DECODE statements to all emulation functions.
2016-04-10Fix primary reason why the SH simulation hasn't been working on 64 bit hosts.Oleg Endo3-37/+21
sim/sh/ * interp.c (dmul): Split into dmul_s and dmul_u. Use explicit integer width types and simplify implementation. * gencode.c (dmuls.l, dmulu.l): Use new functions dmul_s and dmul_u.
2016-04-10Move ChangeLog entries from sim/ChangeLog to sim/sh/ChangeLog.Oleg Endo2-5/+5
2016-04-09Adjust default memory size and stack base address for SH simulator.Oleg Endo2-3/+8
ld/ChangeLog: * sh/interp.c (sim_memory_size): Default init to 30. (parse_and_set_memory_size): Adjust upper bound to 31. sim/ChangeLog: * sh/interp.c (sim_memory_size): Default init to 30. (parse_and_set_memory_size): Adjust upper bound to 31.
2016-04-04Ignore DWARF debug information with a version of 0 - assume that it is padding.Nick Clifton1-12/+189
PR 19872 bfd * dwarf2.c (parse_comp_unit): Skip warning about unrecognised version number if the version is zero. bin * dwarf.c (display_debug_aranges): Skip warning about unrecognised version number if the version is zero.
2016-03-30Fix more bugs in AArch64 simulator.Nick Clifton5-196/+323
* cpustate.c (aarch64_set_reg_s32): New function. (aarch64_set_reg_u32): New function. (aarch64_get_FP_half): Place half precision value into the correct slot of the union. (aarch64_set_FP_half): Likewise. * cpustate.h: Add prototypes for aarch64_set_reg_s32 and aarch64_set_reg_u32. * memory.c (FETCH_FUNC): Cast the read value to the access type before converting it to the return type. Rename to FETCH_FUNC64. (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit accesses. Use for 32-bit memory access functions. * simulator.c (ldrsb_wb): Use sign extension not zero extension. (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. (ldrsh_scale_ext, ldrsw_abs): Likewise. (ldrh32_abs): Store 32 bit value not 64-bits. (ldrh32_wb, ldrh32_scale_ext): Likewise. (do_vec_MOV_immediate): Fix computation of val. (do_vec_MVNI): Likewise. (DO_VEC_WIDENING_MUL): New macro. (do_vec_mull): Use new macro. (do_vec_mul): Use new macro. (do_vec_MLA): Read values before writing. (do_vec_xtl): Likewise. (do_vec_SSHL): Select correct shift value. (do_vec_USHL): Likewise. (do_scalar_UCVTF): New function. (do_scalar_vec): Call new function. (store_pair_u64): Treat reads of SP as reads of XZR.
2016-03-29Tidy up AArch64 simulator code.Nick Clifton4-1469/+1413
* cpustate.c: Remove space after asterisk in function parameters. * decode.h (greg): Delete unused function. (vreg, shift, extension, scaling, writeback, condcode): Likewise. * simulator.c: Use INSTR macro in more places. (HALT_NYI): Use sim_io_eprintf in place of fprintf. Remove extraneous whitespace.
2016-03-23More AArch64 simulator improvements.Nick Clifton6-278/+721
* cpustate.c (aarch64_get_FP_half): New function. Read a vector register as a half precision floating point number. (aarch64_set_FP_half): New function. Similar, but for setting a half precision register. (aarch64_get_thread_id): New function. Returns the value of the CPU's TPIDR register. (aarch64_get_FPCR): New function. Returns the value of the CPU's floating point control register. (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR register. * cpustate.h: Add prototypes for new functions. * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. * memory.c: Use unaligned core access functions for all memory reads and writes. * simulator.c (HALT_NYI): Generate an error message if tracing will not tell the user why the simulator is halting. (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. (INSTR): New time-saver macro. (fldrb_abs): New function. Loads an 8-bit value using a scaled offset. (fldrh_abs): New function. Likewise for 16-bit values. (do_vec_SSHL): Allow for negative shift values. (do_vec_USHL): Likewise. (do_vec_SHL): Correct computation of shift amount. (do_vec_SSHR_USHR): Correct decision of signed vs unsigned shifts and computation of shift value. (clz): New function. Counts leading zero bits. (do_vec_CLZ): New function. Implements CLZ (vector). (do_vec_MOV_element): Call do_vec_CLZ. (dexSimpleFPCondCompare): Implement. (do_FCVT_half_to_single): New function. Implements one of the FCVT operations. (do_FCVT_half_to_double): New function. Likewise. (do_FCVT_single_to_half): New function. Likewise. (do_FCVT_double_to_half): New function. Likewise. (dexSimpleFPDataProc1Source): Call new FCVT functions. (do_scalar_SHL): Handle negative shifts. (do_scalar_shift): Handle SSHR. (do_scalar_USHL): New function. (do_double_add): Simplify to just performing a double precision add operation. Move remaining code into... (do_scalar_vec): ... New function. (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs functions. (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR registers. (system_set): New function. (do_MSR_immediate): New function. Stub for now. (do_MSR_reg): New function. Likewise. Partially implements MSR instruction. (do_SYS): New function. Stub for now, (dexSystem): Call new functions.
2016-03-18Fix thinko in new GET_VEC_ELEMENT macro.Nick Clifton2-1/+2
* cpustate.c: (GET_VEC_ELEMENT): And fix thinko using macro arguments.
2016-03-18Fix code to check for illegal element numbers when accessing AArch64 vector ↵Nick Clifton2-2/+6
registers in AArch64 sim. * cpustate.c (GET_VEC_ELEMENT): Fix off by one error checking for an invalid element index. (SET_VEC_ELEMENT): Likewise.
2016-03-18Add simulation of MUL and NEG instructions to AArch64 simulator.Nick Clifton5-223/+341
* cpustate.c: Remove spurious spaces from TRACE strings. Print hex equivalents of floats and doubles. Check element number against array size when accessing vector registers. * memory.c: Trace memory reads when --trace-memory is enabled. Remove float and double load and store functions. * memory.h (aarch64_get_mem_float): Delete prototype. (aarch64_get_mem_double): Likewise. (aarch64_set_mem_float): Likewise. (aarch64_set_mem_double): Likewise. * simulator (IS_SET): Always return either 0 or 1. (IS_CLEAR): Likewise. (fldrs_pcrel): Load and store floats using 32-bit memory accesses and doubles using 64-bit memory accesses. (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. (store_pair_double, load_pair_float, load_pair_double): Likewise. (do_vec_MUL_by_element): New function. (do_vec_op2): Call do_vec_MUL_by_element. (do_scalar_NEG): New function. (do_double_add): Call do_scalar_NEG.
2016-03-03Fix bugs in the simulation of the AArch64's ADDP, FADDP, LD1, CCMP and CCMP ↵Nick Clifton2-44/+93
instructions. * simulator.c (set_flags_for_sub32): Correct type of signbit. (CondCompare): Swap interpretation of bit 30. (DO_ADDP): Delete macro. (do_vec_ADDP): Copy source registers before starting to update destination register. (do_vec_FADDP): Likewise. (do_vec_load_store): Fix computation of sizeof_operation. (rbit64): Fix type of constant. (aarch64_step): When displaying insn value, display all 32 bits.
2016-02-05sim: mips: fix prog_bfd usageMike Frysinger3-2/+8
We do not want to reference the "base" member directly. We have the STATE_PROG_BFD macro instead to look up the prog_bfd member.
2016-02-04Prevent possible undefined behaviour computing the size of the scache by ↵Nick Clifton2-11/+19
usingunsigned integers instead of signed integers. * cgen-scache.c (scache_option_handler): Prevent possible undefined behaviour computing the size of the scache by using unsigned integers instead of signed integers.
2016-02-03MAINTAINERS: Add Thiemo Seufer back, as a past maintainerMaciej W. Rozycki2-0/+5
Complement commit 26e0f8dbd817 ("* MAINTAINERS: Remove Thiemo Seufer."). * MAINTAINERS (Past sim maintainers): Add Thiemo Seufer.
2016-01-18MIPS: Only build microMIPS specific simulator functions if microMIPS support ↵Andrew Bennett2-0/+42
is required. This fixes PR sim/19441. In the MIPS simulator the microMIPS functions in micromips.igen were not predicated on the microMIPS models. This was causing build issues for some target triples. This patch sets all the microMIPS specific functions to only be built if the micromips32, micromips64 or micromipsdsp models are used. PR sim/19441 * micromips.igen (delayslot_micromips): Enable for `micromips32', `micromips64' and `micromipsdsp' only. (process_isa_mode): Enable for `micromips32' and `micromips64' only. (do_micromips_jalr, do_micromips_jal): Likewise. (compute_movep_src_reg): Likewise. (compute_andi16_imm): Likewise. (convert_fmt_micromips): Likewise. (convert_fmt_micromips_cvt_d): Likewise. (convert_fmt_micromips_cvt_s): Likewise. (FMT_MICROMIPS): Likewise. (FMT_MICROMIPS_CVT_D): Likewise. (FMT_MICROMIPS_CVT_S): Likewise.
2016-01-17Minor comment fixes in sim/common/sim-fpu.c.Joel Brobecker2-67/+71
This patch makes a fair number of fixes in the various comments of sim-fpu.c, mostly to either better conform to the GNU Coding Standards (sentences start with a capital letter, end with a period), or to fix spelling mistakes. sim/common/ChangeLog: * sim-fpu.c: Minor comment fixes throughout.
2016-01-17minor reformatting in sim/common/sim-fpu.c.Joel Brobecker2-2/+9
This patch just makes a copy of formatting changes to better conform with the GNU Coding Style. sim/common/ChangeLog: * sim-fpu.c (print_bits): Minor reformatting (no code change). (sim_fpu_map): Likewise.
2016-01-12sim: mips: workaround 32-bit addr sign extensionsMike Frysinger2-1/+18
The mips bfd will sign extend 32-bit addresses into 64-bit values, so if the entry happens to be 0x80000000 or higher, it is turned to 0xffffffff80000000 which points to memory that doesn't exist. This wasn't an issue until commit 26f8bf63bf36f9062a5cc1afacf71462a as all addresses were automatically truncated there in the translate function to 32-bits. When we cleaned up that code, the full 64-bits were checked leading to many test failures for mips-sde-elf targets and such.
2016-01-11sim: config: do not try to align settingsMike Frysinger2-5/+10
We try to align the output for a few settings, but not most of them. Drop the aligning entirely to be lazy.
2016-01-10sim: move many common settings from CPPFLAGS to config.hMike Frysinger96-2107/+3571
Rather than stuffing the command line with a bunch of -D flags, start moving things to config.h which is managed by autoheader. This makes the makefile a bit simpler and the build output tighter, and it makes the migration to automake easier as there are fewer vars to juggle. We'll want to move the other options out too, but it'll take more work.
2016-01-10sim: drop unused SIM_AC_OPTION_PACKAGESMike Frysinger62-229/+177
This was imported from the ppc sim, but that was only used to control a single file, and that is already governed by the hw models. There's no need to have a sep configure option here, especially since none of the other sims are using it. Even when the code is enabled, there's no runtime overhead.
2016-01-10sim: allow the environment configure option everywhereMike Frysinger73-411/+744
Currently ports have to call SIM_AC_OPTION_ENVIRONMENT explicitly in order to make the configure flag available. There's no real reason to not allow this flag for all ports, so move it to the common sim macro. This way we get standard behavior across all ports too.
2016-01-10sim: allow the assert configure option everywhereMike Frysinger56-54/+626
Currently ports have to call SIM_AC_OPTION_ASSERT explicitly in order to make the configure flag available, which none of them do. There's no real reason to not allow this flag for all ports, so move it to the common sim macro. This way we get standard behavior across all ports.
2016-01-10sim: drop targ-vals.def->nltvals.def indirectionMike Frysinger59-1557/+151
We don't have alternative nltvals.def files, so always symlinking the targ-vals.def file to it doesn't gain us anything. It does make the build more complicated though and a pain to convert to something newer (like automake). Drop the symlinking entirely. In the future, we'll want to explode this file anyways into the respective arch dirs so things can be selected dynamically at runtime, so it's not like we'll be bringing this back.
2016-01-10sim: mips: drop SIM_AC_OPTION_SMP callMike Frysinger3-43/+7
No other port calls this macro directly, and mips has it hardcoded to the default -- disabling smp. In the future we'll enable this for all targets in common code, so tidy up the mips code now.
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