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2018-05-09PR22069, Several instances of register accidentally spelled as regsiterAlan Modra3-2/+7
2018-01-22MAINTAINERS: Update my company e-mail addressMaciej W. Rozycki2-1/+5
2018-01-02Fix compile time warning (in the ARM simulator) about a print statement with ...Nick Clifton2-1/+7
2018-01-02Update copyright year range in all GDB filesJoel Brobecker618-618/+618
2017-12-12sim: testsuite: add testsuite for or1k simPeter Gavin28-0/+6510
2017-12-12sim: or1k: add autoconf generated filesStafford Horne5-0/+16427
2017-12-12sim: or1k: add cgen generated filesStafford Horne11-0/+27536
2017-12-12sim: or1k: add or1k target to simStafford Horne11-0/+1637
2017-12-12sim: cgen: add MUL2OFSI and MUL1OFSI functions (needed for OR1K l.mul[u])Peter Gavin2-0/+25
2017-12-12sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])Peter Gavin5-5/+149
2017-11-01FT32: support for FT32B processor - part 2/2James Bowman2-7/+19
2017-10-12FT32: support for FT32B processor - part 1James Bowman2-7/+15
2017-10-12Add myself as ft32 maintainer for sim.James Bowman2-0/+5
2017-10-03Update my email address.Jim Wilson2-1/+5
2017-09-21[SIM, ARM] Fix build failureYao Qi2-1/+8
2017-09-06Honor an existing CC_FOR_BUILD in the environment for sim.John Baldwin59-202/+434
2017-09-04Define an error function in the PPC simulator library.John Baldwin2-0/+15
2017-09-04Fix simulatorAnthony Green2-7/+16
2017-08-29Fix simulation of MSP430's open system call.Jozef Lawrynowicz2-10/+30
2017-06-02Correct check for endiannessMichael Eager2-1/+5
2017-05-24Refactor disassembler selectionYao Qi2-1/+9
2017-04-22Fix ldn/stn multiple instructions. Fix testcases with unaligned data.Jim Wilson14-202/+454
2017-04-08Add support for fcvtl and fcvtl2.Jim Wilson4-0/+112
2017-04-08Support the fcmXX zero instructions.Jim Wilson4-0/+232
2017-03-25Fix bug with cmn/adds where C flag was incorrectly set.Jim Wilson4-1/+27
2017-03-03Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.Jim Wilson5-9/+89
2017-02-25Add missing smov support, and clean up existing umov support.Jim Wilson4-75/+227
2017-02-25Add missing cnt (popcount) instruction support.Jim Wilson4-0/+94
2017-02-19Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.Jim Wilson8-36/+157
2017-02-14Add self to aarch64 maintainers. Fix mla instruction.Jim Wilson6-49/+128
2017-02-14Fix bit/bif instructions.Jim Wilson4-10/+107
2017-02-14Add ldn/stn single support, fix ldnr support.Jim Wilson6-269/+698
2017-02-13sim: use ARRAY_SIZE instead of ad-hoc sizeof calculationsMike Frysinger39-62/+141
2017-01-23Add support for cmtst.Jim Wilson4-0/+113
2017-01-17Fixes for addv and xtn2 instructions.Jim Wilson5-31/+158
2017-01-09Fix problems with the implementation of the uzp1 and uzp2 instructions.Jim Wilson4-17/+273
2017-01-04Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.Jim Wilson9-33/+618
2017-01-01update copyright year range in GDB filesJoel Brobecker576-576/+576
2016-12-21Fix bugs with float compare and Inf operands.Jim Wilson4-0/+184
2016-12-14MAINTAINERS: Add myself as a MIPS maintainerMaciej W. Rozycki2-0/+6
2016-12-13Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.Jim Wilson7-45/+309
2016-12-03Fix bugs with tbnz/tbz instructions.users/ARM/embedded-binutils-master-2016q4Jim Wilson2-3/+8
2016-12-01Fix typo in ChangeLog entry.Jim Wilson1-1/+1
2016-12-01Fix bug with FP stur instructions.Jim Wilson2-6/+11
2016-11-12sim: mips: add PR info to ChangeLogMike Frysinger1-0/+2
2016-11-11sim: mips: fix dv-tx3904cpu build errorMike Frysinger2-0/+10
2016-11-11sim: mips: fix builds for r3900 cpus due to missing check_u64Mike Frysinger2-0/+5
2016-10-18sim: avr: move changelog entries to subdirMike Frysinger2-7/+7
2016-08-16sim: m68hc11: use standard STATIC_INLINE helperMike Frysinger2-25/+34
2016-08-15sim: unify symbol table handlingMike Frysinger17-170/+164
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