| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2002-09-19 | Remove v850ea references | Nick Clifton | 1 | -316/+0 | |
| 2000-05-30 | Remove illegal instruciton pattern, since it is the same as the breakpoint | Nick Clifton | 1 | -7/+0 | |
| pattern. | |||||
| 2000-05-08 | * merge from internal tree | Frank Ch. Eigler | 1 | -4/+15 | |
| 2000-04-14 Gary Thomas <gthomas@redhat.com> * v850.igen: Define 'br *' as illegal since this is the only way to provide a breakpoint on some v850 family processors. | |||||
| 2000-03-25 | * more compatibility with v850 hardware | Frank Ch. Eigler | 1 | -0/+7 | |
| 2000-03-24 Frank Ch. Eigler <fche@redhat.com> * v850.igen (ilgop): New insn pattern for four-byte breakpoints. | |||||
| 1999-04-16 | Initial creation of sourceware repositorygdb-4_18-branchpoint | Stan Shebs | 1 | -0/+1407 | |
| 1999-04-16 | Initial creation of sourceware repository | Stan Shebs | 1 | -1461/+0 | |
| 1997-12-05 | Reverrt BREAK value back to its old value | Nick Clifton | 1 | -1/+1 | |
| 1997-12-04 | Fixed sanitization, | Nick Clifton | 1 | -208/+64 | |
| Changed pattern for break insn. | |||||
| 1997-09-19 | Clean up tracing for Bcond & jmp insns. | Andrew Cagney | 1 | -128/+100 | |
| Fix computation of disp16 and disp22. Clean up tracing of sld* insns. | |||||
| 1997-09-19 | Fix cmov immed. | Andrew Cagney | 1 | -12/+56 | |
| 1997-09-19 | Fix cmov insn. | Andrew Cagney | 1 | -1/+3 | |
| 1997-09-17 | Clean up more tracing. | Andrew Cagney | 1 | -3/+21 | |
| FIX interrupt delivery - was zapping PSW before it had been saved. FIX interrupt return, was one instruction out. | |||||
| 1997-09-17 | Fix tracing for: "ctret", "bsw", "hsw" | Andrew Cagney | 1 | -36/+72 | |
| Fix bugs in: "bsh", "callt", "stsr". | |||||
| 1997-09-16 | Smooth some of ALU tracing's rough edges. | Andrew Cagney | 1 | -39/+69 | |
| Fix switch insn. | |||||
| 1997-09-16 | Restrict ldsr (load system register) to modifying just non-reserved PSW bits. | Andrew Cagney | 1 | -2/+16 | |
| For v850eq, include PSW[US] in bits that can be modified. | |||||
| 1997-09-16 | Add v850e version of breakpoint instruction. | Andrew Cagney | 1 | -5/+16 | |
| 1997-09-15 | For instructions moved into v850.igen was computing (wrong) NIA when | Andrew Cagney | 1 | -10/+10 | |
| this wasn't needed. | |||||
| 1997-09-15 | Fix sanitization for v850 V v850e V v850eq | Andrew Cagney | 1 | -11/+267 | |
| 1997-09-15 | For v850eq start up with US bit set. | Andrew Cagney | 1 | -2/+26 | |
| Let sim_analyze_program determine the architecture. Fix various sanitizations. | |||||
| 1997-09-12 | Check reserved bits before executing instructions. | Andrew Cagney | 1 | -1/+48 | |
| Make v850[eq] the the default simulator. Report illegal instructions. Include v850e instructions in v850eq. | |||||
| 1997-09-08 | Add multi-sim support to v850/v850e/v850eq simulators. | Andrew Cagney | 1 | -0/+1151 | |
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index : rocket-tools/riscv-gnu-toolchain/gdb.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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