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2002-05-06This commit was manufactured by cvs2svn to create branch 'jimb-jimb-macro-020506-branchpointnobody1-13/+30
macro-020506-branch'. Sprout from gdb_5_2-branch 2002-03-27 05:12:36 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb_5_2-branch'.' Cherrypick from gdb_5_2-branch 2002-03-02 23:00:05 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb_5_2-branch'.': intl/ChangeLog intl/Makefile.in Cherrypick from master 2002-05-06 21:00:21 UTC Jim Blandy <jimb@codesourcery.com> 'Separate the job of reading the line number info statement program': ChangeLog MAINTAINERS Makefile.in bfd/ChangeLog bfd/ChangeLog-9495 bfd/Makefile.am bfd/Makefile.in bfd/aix5ppc-core.c bfd/aout-adobe.c bfd/aout-target.h bfd/aout-tic30.c bfd/aoutx.h bfd/archive.c bfd/archures.c bfd/bfd-in.h bfd/bfd-in2.h bfd/bfd.c bfd/binary.c bfd/bout.c bfd/coff-arm.c bfd/coff-h8300.c bfd/coff-mcore.c bfd/coff-ppc.c bfd/coff-rs6000.c bfd/coff-sh.c bfd/coff-z8k.c bfd/coff64-rs6000.c bfd/coffcode.h bfd/cofflink.c bfd/coffswap.h bfd/config.bfd bfd/configure bfd/configure.in bfd/cpu-h8300.c bfd/cpu-i370.c bfd/cpu-i386.c bfd/cpu-mips.c bfd/cpu-powerpc.c bfd/cpu-s390.c bfd/cpu-sh.c bfd/cpu-sparc.c bfd/dep-in.sed bfd/doc/ChangeLog bfd/doc/Makefile.in bfd/dwarf2.c bfd/ecoff.c bfd/elf-bfd.h bfd/elf-eh-frame.c bfd/elf-hppa.h bfd/elf-m10300.c bfd/elf.c bfd/elf32-arm.h bfd/elf32-cris.c bfd/elf32-hppa.c bfd/elf32-hppa.h bfd/elf32-i370.c bfd/elf32-i386.c bfd/elf32-m32r.c bfd/elf32-m68k.c bfd/elf32-mips.c bfd/elf32-ppc.c bfd/elf32-s390.c bfd/elf32-sh.c bfd/elf32-sh64.c bfd/elf32-sparc.c bfd/elf32-xstormy16.c bfd/elf64-alpha.c bfd/elf64-hppa.c bfd/elf64-mips.c bfd/elf64-mmix.c bfd/elf64-ppc.c bfd/elf64-ppc.h bfd/elf64-s390.c bfd/elf64-sh64.c bfd/elf64-sparc.c bfd/elf64-x86-64.c bfd/elfarm-nabi.c bfd/elflink.c bfd/elflink.h bfd/elfxx-ia64.c bfd/elfxx-mips.c bfd/elfxx-mips.h bfd/elfxx-target.h bfd/i386linux.c bfd/i386msdos.c bfd/i386os9k.c bfd/ieee.c bfd/ihex.c bfd/libbfd-in.h bfd/libbfd.c bfd/libbfd.h bfd/libcoff-in.h bfd/libcoff.h bfd/libecoff.h bfd/libxcoff.h bfd/linker.c bfd/m68klinux.c bfd/merge.c bfd/mmo.c bfd/nlm-target.h bfd/oasys.c bfd/opncls.c bfd/pdp11.c bfd/po/SRC-POTFILES.in bfd/po/fr.po bfd/ppcboot.c bfd/reloc.c bfd/rs6000-core.c bfd/som.c bfd/sparclinux.c bfd/srec.c bfd/sunos.c bfd/syms.c bfd/targets.c bfd/tekhex.c bfd/versados.c bfd/version.h bfd/vms.c bfd/xcofflink.c config.guess config.sub config/ChangeLog config/acinclude.m4 config/mh-a68bsd config/mh-apollo68 config/mh-cxux config/mh-decstation config/mh-dgux config/mh-dgux386 config/mh-djgpp config/mh-hp300 config/mh-hpux config/mh-hpux8 config/mh-interix config/mh-irix5 config/mh-irix6 config/mh-lynxrs6k config/mh-mingw32 config/mh-ncr3000 config/mh-ncrsvr43 config/mh-necv4 config/mh-openedition config/mh-riscos config/mh-sco config/mh-solaris config/mh-sysv config/mh-sysv4 config/mh-sysv5 config/mt-aix43 config/mt-alphaieee config/mt-linux configure configure.in gdb/ChangeLog gdb/MAINTAINERS gdb/Makefile.in gdb/NEWS gdb/PROBLEMS gdb/README gdb/acconfig.h gdb/acinclude.m4 gdb/aclocal.m4 gdb/alpha-linux-tdep.c gdb/alpha-nat.c gdb/alpha-osf1-tdep.c gdb/alpha-tdep.c gdb/alpha-tdep.h gdb/alphabsd-nat.c gdb/alphafbsd-tdep.c gdb/alphanbsd-nat.c gdb/alphanbsd-tdep.c gdb/arc-tdep.c gdb/arch-utils.c gdb/arch-utils.h gdb/arm-tdep.c gdb/arm-tdep.h gdb/avr-tdep.c gdb/bcache.c gdb/blockframe.c gdb/breakpoint.c gdb/builtin-regs.c gdb/builtin-regs.h gdb/c-exp.y gdb/c-lang.c gdb/cli-out.c gdb/cli/cli-cmds.c gdb/cli/cli-decode.c gdb/cli/cli-decode.h gdb/cli/cli-dump.c gdb/cli/cli-dump.h gdb/cli/cli-script.c gdb/coffread.c gdb/command.h gdb/completer.c gdb/config.in gdb/config/alpha/alpha-linux.mt gdb/config/alpha/alpha-osf1.mt gdb/config/alpha/nbsd.mh gdb/config/alpha/nbsd.mt gdb/config/alpha/nm-linux.h gdb/config/alpha/nm-nbsd.h gdb/config/alpha/nm-osf.h gdb/config/alpha/tm-alpha.h gdb/config/alpha/tm-alphalinux.h gdb/config/alpha/tm-fbsd.h gdb/config/alpha/tm-nbsd.h gdb/config/arc/tm-arc.h gdb/config/avr/avr.mt gdb/config/djgpp/README gdb/config/h8500/tm-h8500.h gdb/config/i386/fbsd.mh gdb/config/i386/i386gnu.mh gdb/config/i386/i386lynx.mh gdb/config/i386/i386v42mp.mh gdb/config/i386/nbsd.mt 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gdb/config/v850/tm-v850.h gdb/config/vax/tm-vax.h gdb/configure gdb/configure.host gdb/configure.in gdb/configure.tgt gdb/core-sol2.c gdb/corefile.c gdb/corelow.c gdb/cp-valprint.c gdb/cris-tdep.c gdb/d10v-tdep.c gdb/d30v-tdep.c gdb/dbxread.c gdb/defs.h gdb/doc/ChangeLog gdb/doc/gdb.texinfo gdb/doc/gdbint.texinfo gdb/dwarf2cfi.c gdb/dwarf2read.c gdb/elfread.c gdb/eval.c gdb/event-top.c gdb/exec.c gdb/f-exp.y gdb/f-lang.c gdb/fbsd-proc.c gdb/findvar.c gdb/frame.c gdb/frame.h gdb/gcore.c gdb/gdb-events.c gdb/gdb-events.h gdb/gdb-events.sh gdb/gdbarch.c gdb/gdbarch.h gdb/gdbarch.sh gdb/gdbserver/Makefile.in gdb/gdbserver/config.in gdb/gdbserver/configure gdb/gdbserver/configure.in gdb/gdbserver/gdbreplay.c gdb/gdbserver/inferiors.c gdb/gdbserver/linux-arm-low.c gdb/gdbserver/linux-i386-low.c gdb/gdbserver/linux-ia64-low.c gdb/gdbserver/linux-low.c gdb/gdbserver/linux-low.h gdb/gdbserver/linux-m68k-low.c gdb/gdbserver/linux-mips-low.c gdb/gdbserver/linux-ppc-low.c gdb/gdbserver/linux-s390-low.c gdb/gdbserver/linux-sh-low.c gdb/gdbserver/linux-x86-64-low.c gdb/gdbserver/mem-break.c gdb/gdbserver/mem-break.h gdb/gdbserver/regcache.c gdb/gdbserver/regcache.h gdb/gdbserver/remote-utils.c gdb/gdbserver/server.c gdb/gdbserver/server.h gdb/gdbserver/target.c gdb/gdbserver/target.h gdb/gdbserver/utils.c gdb/gdbtypes.c gdb/gdbtypes.h gdb/gnu-nat.c gdb/gnu-v3-abi.c gdb/go32-nat.c gdb/gregset.h gdb/h8300-tdep.c gdb/h8500-tdep.c gdb/hppa-tdep.c gdb/hpread.c gdb/i386-linux-tdep.c gdb/i386-tdep.c gdb/i386gnu-nat.c gdb/i387-nat.c gdb/i960-tdep.c gdb/ia64-tdep.c gdb/infcmd.c gdb/inferior.h gdb/inflow.c gdb/infrun.c gdb/jv-exp.y gdb/kod.c gdb/language.c gdb/lin-lwp.c gdb/linespec.c gdb/linux-proc.c gdb/m2-exp.y gdb/m3-nat.c gdb/m68hc11-tdep.c gdb/m68klinux-nat.c gdb/maint.c gdb/mcore-tdep.c gdb/mdebugread.c gdb/mem-break.c gdb/mi/ChangeLog gdb/mi/mi-cmd-break.c gdb/mi/mi-cmd-disas.c gdb/mi/mi-cmd-stack.c gdb/mi/mi-cmd-var.c gdb/mi/mi-console.c gdb/mi/mi-main.c gdb/mi/mi-out.c gdb/mi/mi-parse.c gdb/minsyms.c gdb/mips-tdep.c gdb/mipsread.c gdb/mn10300-tdep.c gdb/monitor.c gdb/ocd.c gdb/p-exp.y gdb/p-lang.c gdb/p-lang.h gdb/p-typeprint.c gdb/p-valprint.c gdb/parse.c gdb/parser-defs.h gdb/ppc-bdm.c gdb/ppc-linux-nat.c gdb/ppc-linux-tdep.c gdb/ppc-tdep.h gdb/printcmd.c gdb/proc-api.c gdb/regcache.c gdb/regformats/reg-ppc.dat gdb/regformats/reg-x86-64.dat gdb/remote-array.c gdb/remote-e7000.c gdb/remote-es.c gdb/remote-mips.c gdb/remote-os9k.c gdb/remote-rdi.c gdb/remote-rdp.c gdb/remote-st.c gdb/remote-utils.c gdb/remote-vxsparc.c gdb/remote.c gdb/rs6000-nat.c gdb/rs6000-tdep.c gdb/s390-tdep.c gdb/scm-lang.c gdb/ser-unix.h gdb/serial.c gdb/sh-tdep.c gdb/solib-legacy.c gdb/solib-svr4.c gdb/solib.c gdb/somread.c gdb/source.c gdb/sparc-nat.c gdb/sparc-tdep.c gdb/stabsread.c gdb/stack.c gdb/std-regs.c gdb/symfile.c gdb/symfile.h gdb/symmisc.c gdb/symtab.c gdb/symtab.h gdb/target.c gdb/target.h gdb/testsuite/ChangeLog gdb/testsuite/config/sid.exp gdb/testsuite/gdb.asm/Makefile.in gdb/testsuite/gdb.asm/asm-source.exp gdb/testsuite/gdb.asm/configure gdb/testsuite/gdb.asm/configure.in gdb/testsuite/gdb.asm/powerpc.inc gdb/testsuite/gdb.asm/sparc64.inc gdb/testsuite/gdb.base/annota1.exp gdb/testsuite/gdb.base/attach.exp gdb/testsuite/gdb.base/bar.c gdb/testsuite/gdb.base/baz.c gdb/testsuite/gdb.base/completion.exp gdb/testsuite/gdb.base/cvexpr.c gdb/testsuite/gdb.base/dbx.exp gdb/testsuite/gdb.base/default.exp gdb/testsuite/gdb.base/dump.c gdb/testsuite/gdb.base/dump.exp gdb/testsuite/gdb.base/ending-run.exp gdb/testsuite/gdb.base/foo.c gdb/testsuite/gdb.base/funcargs.c gdb/testsuite/gdb.base/funcargs.exp gdb/testsuite/gdb.base/gcore.exp gdb/testsuite/gdb.base/grbx.c gdb/testsuite/gdb.base/help.exp gdb/testsuite/gdb.base/list.exp gdb/testsuite/gdb.base/long_long.exp gdb/testsuite/gdb.base/maint.exp gdb/testsuite/gdb.base/opaque.exp gdb/testsuite/gdb.base/overlays.exp gdb/testsuite/gdb.base/ovlymgr.c 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gdb/testsuite/lib/gdb.exp gdb/thread-db.c gdb/thread.c gdb/top.c gdb/top.h gdb/tracepoint.c gdb/tui/ChangeLog gdb/tui/tui-out.c gdb/ui-file.c gdb/ui-out.c gdb/utils.c gdb/valarith.c gdb/valops.c gdb/valprint.c gdb/value.h gdb/varobj.c gdb/vax-tdep.c gdb/vax-tdep.h gdb/version.in gdb/win32-nat.c gdb/x86-64-linux-nat.c gdb/x86-64-tdep.c gdb/x86-64-tdep.h gdb/xcoffread.c gdb/xstormy16-tdep.c gdb/z8k-tdep.c include/ChangeLog include/coff/ChangeLog include/coff/rs6k64.h include/dyn-string.h include/elf/ChangeLog include/elf/dwarf2.h include/floatformat.h include/opcode/ChangeLog include/opcode/i386.h include/opcode/mips.h include/opcode/pdp11.h include/xregex2.h libiberty/ChangeLog libiberty/Makefile.in libiberty/config.table libiberty/configure libiberty/configure.in libiberty/cp-demangle.c libiberty/dyn-string.c libiberty/floatformat.c libiberty/functions.texi libiberty/hashtab.c libiberty/hex.c libiberty/splay-tree.c libiberty/strtod.c libiberty/xatexit.c libiberty/xmalloc.c ltmain.sh mmalloc/ChangeLog mmalloc/mmap-sup.c opcodes/ChangeLog opcodes/Makefile.am opcodes/Makefile.in opcodes/configure opcodes/configure.in opcodes/dep-in.sed opcodes/i386-dis.c opcodes/mips-dis.c opcodes/mips-opc.c opcodes/pdp11-dis.c opcodes/pdp11-opc.c opcodes/po/fr.po opcodes/po/id.po opcodes/ppc-opc.c opcodes/s390-dis.c opcodes/z8k-dis.c opcodes/z8k-opc.h opcodes/z8kgen.c sim/ChangeLog sim/MAINTAINERS sim/arm/ChangeLog sim/arm/wrapper.c sim/common/ChangeLog sim/common/callback.c sim/igen/ChangeLog sim/igen/gen.c sim/igen/igen.c sim/m68hc11/ChangeLog sim/m68hc11/dv-m68hc11.c sim/m68hc11/dv-m68hc11spi.c sim/m68hc11/dv-m68hc11tim.c sim/m68hc11/interp.c sim/m68hc11/interrupts.c sim/m68hc11/interrupts.h sim/m68hc11/m68hc11_sim.c sim/m68hc11/sim-main.h sim/mips/ChangeLog sim/mips/Makefile.in sim/mips/configure sim/mips/configure.in sim/mips/cp1.c sim/mips/interp.c sim/mips/mips.igen sim/mips/sim-main.h sim/ppc/ChangeLog sim/ppc/hw_disk.c sim/ppc/ppc-instructions sim/ppc/sim_calls.c sim/z8k/ChangeLog sim/z8k/writecode.c Delete: config/mh-irix4 config/mh-lynxos config/mh-sun3 config/mh-vaxult2 config/mt-armpic config/mt-elfalphapic config/mt-i370pic config/mt-ia64pic config/mt-m68kpic config/mt-papic config/mt-ppcpic config/mt-s390pic config/mt-sparcpic config/mt-x86pic gdb/a29k-tdep.c gdb/config/a29k/a29k-udi.mt gdb/config/a29k/a29k.mt gdb/config/a29k/tm-a29k.h gdb/config/a29k/tm-vx29k.h gdb/config/a29k/vx29k.mt gdb/remote-adapt.c gdb/remote-eb.c gdb/remote-mm.c gdb/remote-udi.c gdb/signals.c gdb/testsuite/gdb.hp/gdb.threads-hp/usrthbasic.c gdb/testsuite/gdb.hp/gdb.threads-hp/usrthbasic.exp gdb/testsuite/gdb.hp/gdb.threads-hp/usrthcore.c gdb/testsuite/gdb.hp/gdb.threads-hp/usrthcore.exp gdb/testsuite/gdb.hp/gdb.threads-hp/usrthfork.c gdb/testsuite/gdb.hp/gdb.threads-hp/usrthfork.exp
2001-11-18 2001-11-17 Fred Fish <fnf@redhat.com>Fred Fish1-7/+7
* sim-main.h (float_operation): Move enum declaration outside of _sim_cpu struct declaration.
2001-04-12* mips.igen (CFC1, CTC1): Pass the correct register numbers toJim Blandy1-1/+0
PENDING_FILL. Use PENDING_SCHED directly to handle the pending set of the FCSR. * sim-main.h (COCIDX): Remove definition; this isn't supported by PENDING_FILL, and you can get the intended effect gracefully by calling PENDING_SCHED directly.
2001-02-242001-02-23 Ben Elliston <bje@redhat.com>Ben Elliston1-0/+2
* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not already defined elsewhere.
2001-02-192001-02-19 Ben Elliston <bje@redhat.com>Ben Elliston1-1/+1
* sim-main.h (sim_monitor): Return an int. * interp.c (sim_monitor): Add return values. (signal_exception): Handle error conditions from sim_monitor.
2000-10-19* cleanupFrank Ch. Eigler1-5/+0
2000-10-19 Frank Ch. Eigler <fche@redhat.com> On advice from Chris G. Demetriou <cgd@sibyte.com>: * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
2000-05-29Define GPR_CLEARNick Clifton1-0/+7
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+785
1999-04-16Initial creation of sourceware repositoryStan Shebs1-1209/+0
1998-12-30* eCos->devo merge; tx3904 sanitize tags removedFrank Ch. Eigler1-4/+30
1998-12-29 Frank Ch. Eigler <fche@cygnus.com> * interp.c (sim_open): Allocate jm3904 memory in smaller chunks. (load_word): Call SIM_CORE_SIGNAL hook on error. (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before starting. For exception dispatching, pass PC instead of NULL_CIA. (decode_coproc): Use COP0_BADVADDR to store faulting address. * sim-main.h (COP0_BADVADDR): Define. (SIM_CORE_SIGNAL): Define hook to call mips_core_signal. (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*(). (_sim_cpu): Add exc_* fields to store register value snapshots. * mips.igen (*): Replace memory-related SignalException* calls with references to SIM_CORE_SIGNAL hook. * dv-tx3904irc.c (tx3904irc_port_event): printf format warning fix. * sim-main.c (*): Minor warning cleanups.
1998-12-08* sky->devo merge, final part of sim mergeFrank Ch. Eigler1-27/+18
[ChangeLog.sky] 1998-12-08 Frank Ch. Eigler <fche@cygnus.com> * sim-main.h (sim_state): Add multi-phase load tracking fields. * sky-gdb.c (sky_option_handler): Add --load-next option handling. * mips.igen (BREAK): Add multi-phase load and printf code handling.
1998-11-23Switch mips-lsi-elf mips16 simulator to igen (from gencode).Andrew Cagney1-2/+2
1998-11-12Add configury for mips-lsi-elf target (32 bit MIPS16).Andrew Cagney1-4/+12
Fix numerous problems with PENDING_* code. In old gencode simulator, don't double tick each cycle. Add BREAK instruction to MIPS16 gencode simulator.
1998-10-27* MONSTER sky -> devo mergeFrank Ch. Eigler1-46/+134
* ChangeLog / ChangeLog.sky entries were merged with original time stamps; a few were moved between the files
1998-09-08* Patch for PR 17142, brought over from sky branch.Frank Ch. Eigler1-6/+21
Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com> * r5900.igen (mtsab): Correct typo in input register. * sim-main.h (TMP_*): New macros for accessing local 128-bit temporary for multimedia instructions. * r5900.igen (*): Convert most instructions to use new TMP macros to store output result during computation.
1998-07-31 * sim-main.h: shadow NUM_CORE_REGS from tm-txvu.hRon Unrau1-6/+14
* interp.c: use NUM_CORE_REGS * sky-gdb.c (set_fifo_breakpoints): use VIF interrupt bit for break * sky-pke.c (pke_issue): use interrupt bit for break points
1998-06-29 * interp.c (OPTION_BRANCH_BUG_4011): Add.Gavin Romig-Koch1-1/+39
(mips_option_handler): Handle OPTION_BRANCH_BUG_4011. (mips_options): Define the option. * mips.igen (check_4011_branch_bug): New. (mark_4011_branch_bug): New. (all branch insn): Call mark_branch_bug, and check_branch_bug. * sim-main.h (branchbug4011_option, branchbug4011_last_target, branchbug4011_last_cia, BRANCHBUG4011_OPTION, BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA, check_branch_bug, mark_branch_bug): Define.
1998-06-16 * sky-pke.c(read_pke_pc): return source address of current pcRon Unrau1-2/+15
* sky-pke.c(read_pke_pcx): return index of current pc * sky-pke.h: export read_pke_pcx * interp.c(sim_fetch_registers): read pke pc/pcx * sky-libvpe.c: track name change from GDB * sim-main.h: add vif memory based pc - extend gdb comm area for fifo breakpoints - define SIM_ENGINE_RESTART_HOOK * sky-gdb.c: add support for VIF breakpoints
1998-06-14 * sky-engine.c: Set ordering of device issues to match enumerated typeRon Unrau1-7/+7
txvu_cpu_context (sim-main.h tm-txvu.h). This also allowed the issue structure to be simplified to an array of functions.
1998-06-09* Handle 10 and 20-bit versions of Break instruction. Move handlingIan Carmichael1-1/+19
* of special values from signal_exception() in interp.c into mips.igen. * * Modified: gencode.c interp.c mips.igen sim-main.h
1998-05-18* Monster patch - may destablize MIPS sims for a little while.Frank Ch. Eigler1-7/+72
* Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-07 * sim-main.h (INSN_NAME): New arg `cpu'.Doug Evans1-2/+8
1998-04-29 * sim-main.h, sky-libvpe.c: r59fp_op* functions were called withJames Lemke1-11/+12
1st parm of wrong type. Converted remaining "/" to "FDiv". * interp.c: Make "--float-type host" the default.
1998-04-22Move target specific stuff from sim/common/sim-base.h to sim/mips/sim-main.hJames Lemke1-0/+11
1998-04-21r5900.igen, sim-main.h, sky-libvpe.c: Add run-time option --float-typeJames Lemke1-0/+19
1998-04-21Fix sanitize tag. The proper keyword is "start-sanitize-*", notJason Molenda1-2/+2
"begin-sanitize-*".
1998-04-21For new IGEN simulators, rewrite checks validating correct use of theAndrew Cagney1-37/+47
HI/LO registers. For old gencode simulator, delete all checks.
1998-04-15Debug tx19 built from igen sources.Andrew Cagney1-1/+7
Rework ifetch{16,32} to match the more recent do_load function.
1998-04-14Implement 32 bit MIPS16 instructions listed in m16.igen.Andrew Cagney1-5/+7
1998-04-09* Backed out week-old attempt at enabling quadword memory access onFrank Ch. Eigler1-12/+0
MIPS sim; added PKE sim code fixes. No COP2 testing progress today. [ChangeLog] Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com> * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses instead of QUADWORD. * sim-main.h: Removed attempt at allowing 128-bit access. [ChangeLog.sky] Thu Apr 9 16:42:54 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-pke.c (read_pke_pc): Corrected PKE PC calculation to word granularity.
1998-04-09* Temporarily change LOADDRMASK in sky build.Ian Carmichael1-0/+2
1998-04-07* R5900 COP2 is now ready for testing. Let loose the dogs!Frank Ch. Eigler1-0/+11
Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (cop_[ls]q): Replaced stub with proper COP2 code. * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses for TARGET_SKY. * r5900.igen (SQC2): Thinko.
1998-04-05* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIFFrank Ch. Eigler1-2/+6
masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
1998-04-05aclocal.m4: Don't enable inlining when cross-compiling.Andrew Cagney1-9/+19
mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-02Re-do load/store operations so that they work for both 32 and 64 bitAndrew Cagney1-2/+9
ISAs. Enable tx39 as igen again.
1998-04-01sky-vu.[ch]: prototype decls, cast floats to ints before register transferRon Unrau1-3/+4
interp.c: integrate VU register read/writes sim-main.h : track tm-txvu.h
1998-03-30* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hideFrank Ch. Eigler1-4/+7
128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-27* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] codeFrank Ch. Eigler1-1/+13
into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-03Fix DIV, DIV1 (wrong check for overflow) and DIVU1 (shouldn't checkAndrew Cagney1-1/+1
for overflow). Pacify GCC.
1998-02-28Add generic sim-info.c:sim_info() function using module mechanism.Andrew Cagney1-1/+1
Clean up compile probs in mips/vr5400.
1998-02-25Finish implementation of r5900 instructions.Andrew Cagney1-0/+16
1998-02-23sim-main.h: Re-arange r5900 registers so that they have their ownAndrew Cagney1-51/+96
little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-02Rewrite the mipsI/II/III pending-slot code.Andrew Cagney1-36/+81
1998-02-01mips: Add multi-processor support for r5900. Others might work.Andrew Cagney1-65/+74
common, igen: Fix MP related bugs.
1998-01-31igen: Fix SMP simulator generator support.Andrew Cagney1-2/+4
Use the bfd-processor name in the sim-engine switch. Add nr_cpus argument to sim_engine_run. tic80, v850, d30v, mips, common: Update mips: Fill in bfd-processor field of model records so that they match ../bfd/archures.
1998-01-21Use macro GPR_SET(N,VAL) to clear zero registers.Andrew Cagney1-2/+5
1997-11-20o Add SIM_SIGFPE to sim-signalsAndrew Cagney1-10/+0
o Start SIM_SIG* at 64 so that the use of host signal numbers can be detected and reported. o Update MIPS simulator to use sim-signal.
1997-11-20Allow reads/writes to C0_CONFIG register.Andrew Cagney1-1/+18
1997-11-11Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1,Andrew Cagney1-0/+3
SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI, MFHI instructions. Trace nullified instruction.
1997-11-06Replace global IPC with function argument cia or current instructionAndrew Cagney1-2/+0
address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
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