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AgeCommit message (Expand)AuthorFilesLines
1998-02-16Implement "dbt" and "rtd" instructions.Andrew Cagney2-15/+40
1998-02-13Implement separate user (SPU) and interrupt (SPI) stack pointers.Andrew Cagney3-0/+15
1998-02-11Don't abort() when system call is unknown.Andrew Cagney2-1/+4
1998-02-11Ensure zero-hardwired bits in DPSW remain zero.Andrew Cagney3-4/+77
1998-02-10D10v memory map changed. Update.Andrew Cagney1-136/+173
1998-01-31Add config support for the size of the target address and OF cell.Andrew Cagney1-0/+4
1998-01-26Exit status is in r0, not r2Michael Meissner1-0/+4
1998-01-25If DEBUG has 0x20 set, turn traps into batch debuggingMichael Meissner1-0/+7
1998-01-23First round of d10v ABI changesMichael Meissner2-68/+78
1998-01-22 * interp.c (UMEM_SEGMENTS): New define, set to 128.Fred Fish2-54/+134
1998-01-20* aclocal.m4: Recognize --enable-maintainer-mode.Doug Evans2-43/+90
1997-12-08Fix typo, REP_S was refering to REP_E register.Andrew Cagney2-1/+5
1997-12-08For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: SteppingAndrew Cagney3-87/+165
1997-12-04Regenerate configure files.Doug Evans1-0/+4
1997-12-04Add DM (bit 4) to PSW. See 7-1 for more info.Andrew Cagney3-0/+10
1997-12-03* d10v_sim.h (SEXT56): Define.Andrew Cagney3-54/+48
1997-12-02 * interp.c (sim_resume): Call do_2_short with LEFT_FIRST orFred Fish2-26/+36
1997-12-02For "msbu", subtract unsigned product from ACC,Andrew Cagney2-4/+9
1997-12-02For "mulxu", store unsigned product in ACC.Andrew Cagney2-3/+7
1997-12-02For MACU add unsigned multiply to accumulator.Andrew Cagney2-4/+13
1997-12-02For sub2w, compute carry according to negated addition rules.Andrew Cagney2-4/+6
1997-12-01Rework sim/common/sim-alu.h to differentiate between direcctAndrew Cagney2-11/+40
1997-11-10* simops.c (OP_4201): "rachi". Sign extend bit 40 of ACC. SignAndrew Cagney1-0/+6
1997-10-25Correct name of file given in ChangeLog for change: Pass lma_p andAndrew Cagney1-1/+1
1997-10-24Address MSC compiler issues in d10v_sim.hAndrew Cagney1-0/+8
1997-10-22Add LMA_P and DO_WRITE arguments to sim/common/sim-load.c:sim_load_file().Andrew Cagney2-2/+29
1997-10-13 * simops.c (OP_6A01): Change OP_POSTDEC to OP_POSTINC and moveFred Fish2-8/+15
1997-10-11 * simops.c (OP_6401): postdecrement on r15 is OK, remove exception.Fred Fish1-15/+3
1997-10-11 * simops.c (OP_6401): postdecrement on r15 is OK, remove exception.Fred Fish1-0/+9
1997-09-27 * d10v_sim.h (INC_ADDR): Align MOD_E to increment before testingFred Fish1-0/+2
1997-09-27 * interp.c (pc_addr): Discard upper bit(s) of PC in caseFred Fish1-0/+9
1997-09-23Remove need to update <targ>/Makefile.in when adding optional optionsAndrew Cagney2-39/+125
1997-09-22Simplify logic behind the generic configuration option --enable-sim-alignment.Andrew Cagney1-0/+4
1997-09-22Add support for --enable-sim-alignment to simulator common aclocal.m4Andrew Cagney1-0/+8
1997-09-11Wed Sep 10 22:30:24 1997 Martin M. Hunt <hunt@cygnus.com>Martin Hunt1-0/+7
1997-09-05* configure: Regenerated to track ../common/aclocal.m4 changes.David Edelsohn2-71/+307
1997-08-27Fix doco on enable-sim-inline.Andrew Cagney1-0/+5
1997-08-27Add ABFD argument to sim_create_inferior. Document.Andrew Cagney2-7/+15
1997-08-26Flush defunct sim_kill.Andrew Cagney2-7/+4
1997-08-25Add ABFD argument to sim_open call. Pass through to sim_config soAndrew Cagney2-8/+23
1997-04-22 * interp.c (sim_open): Undo patch to add -E support.David Edelsohn1-0/+4
1997-04-18Ref gdb/11763 - can't stop a running simulator:Andrew Cagney2-0/+13
1997-04-17 * Makefile.in (SIM_OBJS): Add sim-load.o.David Edelsohn2-59/+114
1997-04-17Cleanups to compile under FreeBSDAndrew Cagney2-40/+34
1997-04-07Get configure to define RETSIGTYPEAndrew Cagney1-187/+97
1997-04-02 * interp.c (sim_open): New arg `kind'.David Edelsohn1-0/+2
1997-04-02 * aclocal.m4: Check for stdlib.h, string.h, strings.h, unistd.h.David Edelsohn2-132/+281
1997-04-02New file common/sim-config.c sets/checks simulator configuration options.Andrew Cagney2-46/+34
1997-03-17 * configure: Re-generate.Andrew Cagney1-191/+120
1997-03-14Add comment to changelogMichael Meissner1-1/+2