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2013-01-17include/opcode/Yufeng Zhang5-10/+28
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64.h (aarch64_op): Remove OP_V_MOVI_B. opcodes/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI. * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): For AARCH64_MOD_LSL, move the range check on the shift amount before the alignment check; change to call set_sft_amount_out_of_range_error instead of set_imm_out_of_range_error. * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL. (aarch64_opcode_table): Remove the OP enumerator from the asimdimm 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to SIMD_IMM_SFT. gas/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * config/tc-aarch64.c (output_operand_error_record): Change to output the out-of-range error message as value-expected message if there is only one single value in the expected range. (programmer_friendly_fixup): Remove the handling of 8-bit MOVI with LSL #0 as a programmer-friendly feature. gas/testsuite/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * gas/aarch64/diagnostic.l: Update. * gas/aarch64/movi.s: Add tests. * gas/aarch64/movi.d: Update. * gas/aarch64/programmer-friendly.s: Add comment.
2013-01-16Add OPERAND_TYPE_IMM32_64H.J. Lu4-2/+16
* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2013-01-15 * config/tc-v850.c (md_assemble): Allow signed values forNick Clifton3-2/+10
V850E_IMMEDIATE. * gas/v850/basic.exp: Allow for variations in reloc names. * gas/v850/split-lo16.d: Likewise. * gas/v850/v850e1.s: Add more tests of the PREPARE insn. * gas/v850/v850e1.d: Update expected disassembly. * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE values. * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
2013-01-14 * metag-dis.c (REG_WIDTH): Increase to 64.Nick Clifton2-1/+5
* gas/metag/metadsp21.d: Fix expected MMOV disassembly.
2013-01-11include/opcode/Peter Bergner3-1/+76
* ppc.h (PPC_OPCODE_POWER8): New define. (PPC_OPCODE_HTM): Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries. * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK, XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines. (SH6): Update. <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.", "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.", "treclaim.", "tsr.">: Add POWER8 HTM opcodes. <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes. gas/ * doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * config/tc-ppc.c (md_show_usage): Likewise. (ppc_handle_align): Handle power8's group ending nop. gas/testsuite/ * gas/ppc/htm.d: New test. * gas/ppc/htm.s: Likewise. * gas/ppc/power8.d: Likewise. * gas/ppc/power8.s: Likewise. * gas/ppc/ppc.exp: Run them.
2013-01-10 * common.h: Fix case of "Meta".Nick Clifton7-0/+3409
* metag.h: New file. * dis-asm.h (print_insn_metag): New declaration. * metag.h: New file. * Makefile.am: Add Meta. * Makefile.in: Regenerate. * configure: Regenerate. * configure.in: Add Meta. * disassemble.c: Add Meta support. * metag-dis.c: New file. * Makefile.am: Add Meta. * Makefile.in: Regenerate. * archures.c (bfd_mach_metag): New. * bfd-in2.h: Regenerate. * config.bfd: Add Meta. * configure: Regenerate. * configure.in: Add Meta. * cpu-metag.c: New file. * elf-bfd.h: Add Meta. * elf32-metag.c: New file. * elf32-metag.h: New file. * libbfd.h: Regenerate. * reloc.c: Add Meta relocations. * targets.c: Add Meta. * Makefile.am: Add Meta. * Makefile.in: Regenerate. * config/tc-metag.c: New file. * config/tc-metag.h: New file. * configure.tgt: Add Meta. * doc/Makefile.am: Add Meta. * doc/Makefile.in: Regenerate. * doc/all.texi: Add Meta. * doc/as.texiinfo: Document Meta options. * doc/c-metag.texi: New file. * gas/metag/labelarithmetic.d: New file. * gas/metag/labelarithmetic.s: New file. * gas/metag/metacore12.d: New file. * gas/metag/metacore12.s: New file. * gas/metag/metacore21-invalid.l: New file. * gas/metag/metacore21-invalid.s: New file. * gas/metag/metacore21.d: New file. * gas/metag/metacore21.s: New file. * gas/metag/metacore21ext.d: New file. * gas/metag/metacore21ext.s: New file. * gas/metag/metadsp21-invalid.l: New file. * gas/metag/metadsp21-invalid.s: New file. * gas/metag/metadsp21.d: New file. * gas/metag/metadsp21.s: New file. * gas/metag/metadsp21ext.d: New file. * gas/metag/metadsp21ext.s: New file. * gas/metag/metafpu21.d: New file. * gas/metag/metafpu21.s: New file. * gas/metag/metafpu21ext.d: New file. * gas/metag/metafpu21ext.s: New file. * gas/metag/metag.exp: New file. * gas/metag/tls.d: New file. * gas/metag/tls.s: New file. * Makefile.am: Add Meta. * Makefile.in: Regenerate. * configure.tgt: Add Meta. * emulparams/elf32metag.sh: New file. * emultempl/metagelf.em: New file. * ld-elf/merge.d: Mark Meta as xfail. * ld-gc/start.d: Skip this test on Meta. * ld-gc/personality.d: Skip this test on Meta. * ld-metag/external.s: New file. * ld-metag/metag.exp: New file. * ld-metag/pcrel.d: New file. * ld-metag/pcrel.s: New file. * ld-metag/shared.d: New file. * ld-metag/shared.r: New file. * ld-metag/shared.s: New file. * ld-metag/stub.d: New file. * ld-metag/stub.s: New file. * ld-metag/stub_pic_app.d: New file. * ld-metag/stub_pic_app.r: New file. * ld-metag/stub_pic_app.s: New file. * ld-metag/stub_pic_shared.d: New file. * ld-metag/stub_pic_shared.s: New file. * ld-metag/stub_shared.d: New file. * ld-metag/stub_shared.r: New file. * ld-metag/stub_shared.s: New file. * binutils/readelf.c: (guess_is_rela): Add EM_METAG. (dump_relocations): Add EM_METAG. (get_machine_name): Correct case for Meta. (is_32bit_abs_reloc): Add support for Meta ADDR32 reloc. (is_none_reloc): Add support for Meta NONE reloc.
2013-01-07oops - typo correction.Nick Clifton1-1/+1
2013-01-07 (make_instruction): Rename to cr16_make_instruction.Nick Clifton2-4/+9
(match_opcode): Rename to cr16_match_opcode.
2013-01-04 * archures.c: Add support for MIPS r5900Nick Clifton3-138/+341
* bfd-in2.h: Add support for MIPS r5900 * config.bfd: Add support for Sony Playstation 2 * cpu-mips.c: Add support for MIPS r5900 * elfxx-mips.c: Add support for MIPS r5900 (extension of r4000) * config/tc-mips.c: Add support for MIPS r5900 Add M_LQ_AB and M_SQ_AB to support large values for instructions lq and sq. * config/tc-mips.c (can_swap_branch_p, get_append_method): Detect some conditional short loops to fix a bug on the r5900 by NOP in the branch delay slot. * config/tc-mips.c (M_MUL): Support 3 operands in multu on r5900. * config/tc-mips.c (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I. * config/tc-mips.c (s_mipsset): Force 32 bit floating point on r5900. * configure.in: Detect CPU type when target string contains r5900 (e.g. mips64r5900el-linux-gnu). * config/tc-mips.c (mips_ip): Check parameter range of instructions mfps and mtps on r5900. * elf/mips.h: Add MIPS machine variant number for r5900 which is compatible with old Playstation 2 software. * opcode/mips.h: Add support for r5900 instructions including lq and sq. * configure.tgt: Support ELF files for Sony Playstation 2 (for ps2dev and ps2sdk). * emulparams/elf32lr5900n32.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI n32. * emulparams/elf32lr5900.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI o32. * Makefile.am: Add linker scripts for Sony Playstation 2 ELF files. * opcodes/mips-dis.c: Add names for CP0 registers of r5900. * opcodes/mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for instructions sq and lq. * opcodes/mips-opc.c: Add support for MIPS r5900 CPU. Add support for 128 bit MMI (Multimedia Instructions). Add support for EE instructions (Emotion Engine). Disable unsupported floating point instructions (64 bit and undefined compare operations). Enable instructions of MIPS ISA IV which are supported by r5900. Disable 64 bit co processor instructions. Disable 64 bit multiplication and division instructions. Disable instructions for co-processor 2 and 3, because these are not supported (preparation for later VU0 support (Vector Unit)). Disable cvt.w.s because this behaves like trunc.w.s and the correct execution can't be ensured on r5900. Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This will confuse less developers and compilers.
2013-01-04opcodes/Yufeng Zhang3-8/+33
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-opc.c (aarch64_print_operand): Change to print AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal in comment. * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and OP_MOV_IMM_WIDE. gas/testsuite/ 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> * gas/aarch64/int-insns.d: Update. * gas/aarch64/mov.d: Update. * gas/aarch64/reloc-insn.d: Update. ld/testsuite/ 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> * ld-aarch64/emit-relocs-264.d: Append the '-Mno-aliases' option to the objdump directive. * ld-aarch64/emit-relocs-266.d: Ditto. * ld-aarch64/emit-relocs-268.d: Ditto. * ld-aarch64/emit-relocs-269.d: Ditto. * ld-aarch64/emit-relocs-270.d: Ditto. * ld-aarch64/emit-relocs-271.d: Ditto. * ld-aarch64/emit-relocs-272.d: Ditto.
2013-01-04 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,Nick Clifton2-14/+19
PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM. * gas/aarch64/system.d: Update.
2013-01-02Update copyright year to 2013H.J. Lu2-2/+6
binutils/ 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> * version.c (print_version): Update copyright year to 2013. gas/ 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> * as.c (parse_args): Update copyright year to 2013. ld/ 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> * ldver.c (ldversion): Update copyright year to 2013. opcodes/ 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (process_copyright): Update copyright year to 2013.
2013-01-02opcodes/ChangeLogNick Clifton3-1111/+1140
* cr16-dis.c (match_opcode,make_instruction: Remove static declaration. (dwordU,wordU): Moved typedefs to opcode/cr16.h (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_' bfd/Changelog * config.bfd (cr16*-*-uclinux*): New target support. include/opcode/ChangeLog * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c (make_instruction,match_opcode): Added function prototypes. (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
2012-12-17Add copyright noticesNick Clifton11-2/+187
2012-12-13 PR binutils/14950Alan Modra2-65/+46
* ppc-opc.c (insert_sci8, extract_sci8): Rewrite. (insert_sci8n, extract_sci8n): Likewise.
2012-12-10Add copyright noticesNick Clifton13-0/+81
2012-11-302012-11-30 Oleg Raikhman <oleg@adapteva.com>Joern Rennecke4-121/+126
Joern Rennecke <joern.rennecke@embecosm.com> cpu: * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12. (load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l. (testset-insn): Add NO_DIS attribute to t.l. (store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l. (move-insns): Add NO-DIS attribute to cmov.l. (op-mmr-movts): Add NO-DIS attribute to movts.l. (op-mmr-movfs): Add NO-DIS attribute to movfs.l. (op-rrr): Add NO-DIS attribute to .l. (shift-rrr): Add NO-DIS attribute to .l. (op-shift-rri): Add NO-DIS attribute to i32.l. (bitrl, movtl): Add NO-DIS attribute. (op-iextrrr): Add NO-DIS attribute to .l (op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l. (op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise. opcodes: * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.
2012-11-29opcodes/Roland McGrath2-5/+9
* s390-mkopc.c (file_header): Add const.
2012-11-29opcodes/Changelog:Michael Eager3-7/+13
* microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to INST_TYPE_R1_R2_SPECIAL * microblaze-dis.c (print_insn_microblaze): Same. gas/Changelog * gas/config/tc-microblaze.c: Rename INST_TYPE_RD_R1_SPECIAL to INST_TYPE_R1_R2_SPECIAL, don't set RD for wic.
2012-11-23include/opcode/Alan Modra2-24/+76
* ppc.h (ppc_parse_cpu): Update prototype. opcodes/ * ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits set from ppc_opts.sticky in it. Delete "retain_mask". (powerpc_init_dialect): Choose default dialect from info->mach before parsing -M options. Handle more bfd_mach_ppc variants. Update common default to power7. gas/ * config/tc-ppc.c (sticky): New var. (md_parse_option, ppc_machine): Update ppc_parse_cpu calls. gas/testsuite/ * gas/ppc/astest2.d: Pass -Mppc to objdump. ld/testsuite/ * ld-powerpc/plt1.d: Update for default "at" branch hints. * ld-powerpc/tlsexe.d: Likewise. * ld-powerpc/tlsexetoc.d: Likewise. * ld-powerpc/tlsopt1.d: Likewise. * ld-powerpc/tlsopt1_32.d: Likewise. * ld-powerpc/tlsopt2.d: Likewise. * ld-powerpc/tlsopt2_32.d: Likewise. * ld-powerpc/tlsopt4.d: Likewise. * ld-powerpc/tlsopt4_32.d: Likewise. * ld-powerpc/tlsso.d: Likewise. * ld-powerpc/tlstocso.d: Likewise.
2012-11-21Add swap byte (swapb) and swap halfword (swaph) opcodes.Michael Eager3-2/+9
binutils/opcodes * microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES. * microblaze-opcm.h (microblaze_instr): Likewise binutils/gas/testsuite * gas/microblaze/allinsn.s: Add swapb, swaph * gas/microblaze/allinsn.d: Likewise
2012-11-21Add stack high register and stack low register for MicroBlazeMichael Eager3-0/+15
hardware assisted stack protection, stores stack low / stack high limits for detecting stack overflow / underflow binutils/opcodes * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK binutils/gas * config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR binutils/gas * gas/microblaze/allinsn.s: Test use of SHR, SLR * gas/microblaze/allinsn.d: Likewise
2012-11-20Fix opcode for 64-bit jecxzH.J. Lu3-2/+9
gas/testsuite/ PR gas/14859 * gas/i386/x86-64-opcode.s: Add jecxz. * gas/i386/x86-64-opcode.d: Updated. opcodes/ PR gas/14859 * i386-opc.tbl: Fix opcode for 64-bit jecxz. * i386-tbl.h: Regenerated.
2012-11-202012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel2-2/+6
* s390-opc.txt: Fix srstu and strag opcodes. 2012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/zarch-z9-109.d: Fix srstu opcode. * gas/s390/zarch-z900.d: Replace lasp with strag.
2012-11-14opcodes/Michael Eager4-4/+45
* microblaze-opc.h: Define new instruction type INST_TYPE_IMM5, update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5, and increase MAX_OPCODES. (op_code_struct): add mbar and sleep * microblaze-opcm.h (microblaze_instr): add mbar Define IMM_MBAR and IMM5_MBAR_MASK * microblaze-dis.c: Add get_field_imm5_mbar (print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE gas/ * config/tc-microblaze.c (md_assemble): Add support for INST_TYPE_IMM5 gas/testsuite/ * gas/microblaze/allinsn.s: Add mbar and sleep * gas/microblaze/allinsn.d: Likewise
2012-11-14Add clz opcode.Michael Eager3-2/+8
opcodes/ * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add clz insn * microblaze-opcm.h (microblaze_instr): add clz gas/testsuite/ * gas/microblaze/allinsn.s: Add clz insn * gas/microblaze/allinsn.d: Likewise
2012-11-14Add the endian reversing versions of load/store instructions;Michael Eager3-2/+16
2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com> * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur, lhur, lwr, sbr, shr, swr * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr, swr 2012-11-14 David Holsgrove <david.holsgrove@xilinx.com> * gas/microblaze/allinsn.exp: New file - test newly added opcodes * gas/microblaze/allinsn.s: Likewise * gas/microblaze/allinsn.d: Likewise
2012-11-092012-11-09 Nick Clifton <nickc@redhat.com>Nick Clifton4-0/+9
* Makefile.am (ALL_MACHINES): Add cpu-v850-rh850.lo. (ALL_MACHINES_CFILES): Add cpu-v850-rh850.c. * archures.c (bfd_arch_info): Add bfd_v850_rh850_arch. * config.bfd: Likewise. * configure.in: Add bfd_elf32_v850_rh850_vec. * cpu-v850.c: Update printed description. * cpu-v850_rh850.c: New file. * elf32-v850.c (v850_elf_check_relocs): Add support for RH850 ABI relocs. (v850_elf_perform_relocation): Likewise. (v850_elf_final_link_relocate): Likewise. (v850_elf_relocate_section): Likewise. (v850_elf_relax_section): Likewise. (v800_elf_howto_table): New. (v850_elf_object_p): Add support for RH850 ABI values. (v850_elf_final_write_processing): Likewise. (v850_elf_merge_private_bfd_data): Likewise. (v850_elf_print_private_bfd_data): Likewise. (v800_elf_reloc_map): New. (v800_elf_reloc_type_lookup): New. (v800_elf_reloc_name_lookup): New. (v800_elf_info_to_howto): New. (bfd_elf32_v850_rh850_vec): New. (bfd_arch_v850_rh850): New. * targets.c (_bfd_targets): Add bfd_elf32_v850_rh850_vec. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * readelf.c (get_machine_flags): Add support for E_FLAG_RX_ABI. (guess_is_rela): Add EM_V800. (dump_relocations): Likewise. (get_machine_name): Update EM_V800. (get_machine_flags): Add support for RH850 ABI flags. (is_32bit_abs_reloc): Add support for RH850 ABI reloc. * config/tc-v850.c (v850_target_arch): New. (v850_target_format): New. (set_machine): Use v850_target_arch. (md_begin): Likewise. (md_show_usage): Document new switches. (md_parse_option): Add -mgcc-abi, -mrh850-abi, -m8byte-align and -m4byte-align. * config/tc-v850.c (TARGET_ARCH) Use v850_target_arch. (TARGET_FORMAT): Use v850_target_format. * doc/c-v850.texi: Document new options. * v850.h: Add RH850 ABI values. * Makefile.am: (ALL_EMULATION_SOURCES): Add ev850_rh850.c. * Makefile.in: Regenerate. * configure.tgt (v850*-*-*): Make v850_rh850 the default emulation. Add vanilla v850 as an extra emulation. * emulparams/v850_rh850.sh: New file. * scripttempl/v850_rh850.sc: New file. * configure.in: Add bfd_v850_rh850_arch. * configure: Regenerate. * disassemble.c (disassembler): Likewise.
2012-11-09Remove trailing redundant `;'H.J. Lu3-2/+7
bfd/ * aout-tic30.c (MY_final_link_callback): Remove trailing redundant `;'. * coff-h8500.c (extra_case): Likewise. (bfd_coff_reloc16_get_value): Likewise. * dwarf2.c (_bfd_dwarf2_cleanup_debug_info): Likewise. * elf.c (_bfd_elf_slurp_version_tables): Likewise. * elf32-frv.c (elf32_frv_relocate_section): Likewise. * elf32-v850.c (v850_elf_perform_relocation): Likewise. * opncls.c (bfd_calc_gnu_debuglink_crc32): Likewise. * plugin.c (add_symbols): Likewise. * reloc.c (bfd_check_overflow): Likewise. * vms-lib.c (_bfd_vms_lib_archive_p): Likewise. binutils/ * coffgrok.c (coff_grok): Remove trailing redundant `;'. * resrc.c (open_input_stream): Likewise. gas/ * config/atof-ieee.c (gen_to_words): Remove trailing redundant `;'. * config/atof-vax.c (flonum_gen2vax): Likewise. * config/tc-d10v.c (write_2_short): Likewise. * config/tc-i386-intel.c (i386_intel_simplify): Likewise. * config/tc-s390.c (tc_s390_force_relocation): Likewise. * config/tc-v850.c (md_parse_option): Likewise. * config/tc-xtensa.c (find_address_of_next_align_frag): Likewise. * dwarf2dbg.c (out_header): Likewise. * symbols.c (dollar_label_name): Likewise. (fb_label_name): Likewise. ld/ * testplug.c (record_add_file): Remove trailing redundant `;'. opcodes/ * aarch64-opc.h (gen_mask): Remove trailing redundant `;'. * ia64-gen.c (fetch_insn_class): Likewise.
2012-11-08Regenerate.Alan Modra2-0/+15
2012-11-05 * configure.in: Apply 2012-09-10 change to config.in here.Alan Modra2-2/+7
2012-10-262012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel4-3/+32
* s390-mkopc.c: Accept empty lines in s390-opc.txt. * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2 and RRF_RMRR. * s390-opc.txt: Add new instructions. New instruction type for lptea. 2012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/testsuite/gas/s390/zarch-z10.d: Refreshed. * gas/testsuite/gas/s390/zarch-z10.s: Refreshed. * gas/testsuite/gas/s390/zarch-z196.d: Refreshed. * gas/testsuite/gas/s390/zarch-z196.s: Refreshed. * gas/testsuite/gas/s390/zarch-z9-109.d: Refreshed. * gas/testsuite/gas/s390/zarch-z990.d: Refreshed. * gas/testsuite/gas/s390/zarch-z990.s: Refreshed. * gas/testsuite/gas/s390/zarch-zEC12.d: Refreshed. * gas/testsuite/gas/s390/zarch-zEC12.s: Refreshed.
2012-10-26gas/testsuite:Christian Groessler3-61/+59
* gas/z8k/z8k.exp: Run translate-ops test. * gas/z8k/translate-ops.s: New file. * gas/z8k/translate-ops.d: New file. opcodes: * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb, trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove non-existing opcode trtrb. * z8k-opc.h: Regenerate.
2012-10-26 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.Alan Modra2-2/+6
2012-10-24gas/testsuite/Roland McGrath2-58/+66
* gas/i386/rex.s: Add test of REX prefix before fsave (i.e. fwait). * gas/i386/rex.d: Update. opcodes/ * i386-dis.c (ckprefix): When bailing out for fwait with prefixes, set rex_used to rex.
2012-10-22opcodes/Peter Bergner2-1/+5
* ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling. gas/testsuite/ * gas/ppc/altivec.s <vcfpsxws>: Fix opcode spelling.
2012-10-18 * tic54x-dis.c (print_instruction): Don't use K&R style.Tom Tromey2-38/+37
(print_parallel_instruction, sprint_dual_address) (sprint_indirect_address, sprint_direct_address, sprint_mmr) (sprint_cc2, sprint_condition): Likewise.
2012-10-18 * aarch64-asm.c (aarch64_ins_ldst_reglist): InitializeKai Tietz3-7/+16
value with a default. (do_special_encoding): Likewise. (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2 variables with default. * arc-dis.c (write_comments_): Don't use strncat due size of state->commentBuffer pointer isn't predictable.
2012-10-15Updated the system register table.Yufeng Zhang2-4/+8
opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and rmr_el3; remove daifset and daifclr. gas/testsuite/ * gas/aarch64/sysreg-1.s: Add tests of rmr_el1, rmr_el2 and rmr_el3. * gas/aarch64/sysreg-1.d: Update. * gas/aarch64/illegal.s: Add tests of daifset and daifclr. * gas/aarch64/illegal.d: Update.
2012-10-15Added the changelog for the previous commit.Yufeng Zhang1-0/+6
2012-10-15Added missing alignment check to load/store uimm12 immediate offset.Yufeng Zhang1-1/+1
opcodes/ * aarch64-opc.c (operand_general_constraint_met_p): Change to check the alignment of addr.offset.imm instead of that of shifter.amount for operand type AARCH64_OPND_ADDR_UIMM12. gas/testsuite/ * gas/aarch64/illegal-2.s: Add test case. * gas/aarch64/illegal-2.l: Likewise.
2012-10-112012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw2-5/+10
* arm-dis.c: Use preferred form of vrint instruction variants for disassembly. 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gas/arm/armv8-a+fp.d: Use preferred form of vrint instruction variants for disassembly. * gas/arm/armv8-a+fp.s: Likewise. * gas/arm/armv8-a+simd.d: Likewise. * gas/arm/armv8-a+simd.s: Likewise.
2012-10-09Add AMD bdver3 support.Nagajyothi Eggone3-0/+13
gas/ * config/tc-i386.c (cpu_arch): Add CPU_BDVER3_FLAGS. * doc/c-i386.texi: Add -march=bdver3 option. gas/testsuite/ * gas/i386/i386.exp: Run bdver3 test cases. * gas/i386/nops-1-bdver3.d: New. * gas/i386/arch-10-bdver3.d: New. * gas/i386/x86-64-nops-1-bdver3.d: New. * gas/i386/x86-64-arch-2-bdver3.d: New. opcodes/ * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS. * i386-init.h: Regenerated.
2012-10-05opcodes/Peter Bergner3-1/+21
* ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2; * ppc-opc.c (VBA): New define. (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot, mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics. gas/testsuite/ * gas/ppc/power7.d: Add tests for mfppr, mfppr32, mtppr and mtppr32. * gas/ppc/power7.s: Likewise. * gas/ppc/altivec.d: Add tests for all legacy Altivec instructions. * gas/ppc/altivec.s: Likewise. * gas/ppc/altivec2.d: New test file. * gas/ppc/altivec2.s: Likewise. * gas/ppc/ppc.exp: Run it.
2012-10-04 * v850-dis.c (disassemble): Place square parentheses around secondNick Clifton2-4/+21
register operand of clr1, not1, set1 and tst1 instructions. * config/tc-v850.c (v850_insert_operand): Use a static buffer for the error message. * gas/v850/v850e1.d: Fix expected disassembly of clr1, not1, set1 and tst1 insns.
2012-10-042012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel4-34/+90
* config/tc-s390.c (s390_parse_cpu): Add new option zEC12. * doc/as.texinfo: Document new option zEC12. * doc/c-s390.texi: Likewise. 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/s390.exp: Run zEC12 tests. * gas/s390/zarch-zEC12.d: New file. * gas/s390/zarch-zEC12.s: New file. 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-mkopc.c: Support new option zEC12. * s390-opc.c: Add new instruction formats. * s390-opc.txt: Add new instructions for zEC12. 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
2012-09-28Don't abort() when disassembling bad moxie instructions.Anthony Green3-29/+102
2012-09-25Add missing Cpu flags in bd and bt coresH.J. Lu3-16/+23
gas/testsuite/ 2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com> * gas/i386/arch-10-bdver1.d: New file to test bdver1 core. * gas/i386/x86-64-arch-2-bdver1.d: Likewise. * gas/i386/i386.exp: Run bdver1 testcases. * gas/i386/arch-10-bdver2.d: Updated -march flags. * gas/i386/arch-10-btver1.d: Likewise. * gas/i386/arch-10-btver2.d: Likewise. * gas/i386/x86-64-arch-2-bdver2.d: Likewise. * gas/i386/x86-64-arch-2-btver1.d: Likewise. * gas/i386/x86-64-arch-2-btver2.d: Likewise. opcodes/ 2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com> * gas/i386/arch-10-bdver1.d: New file to test bdver1 core. * gas/i386/x86-64-arch-2-bdver1.d: Likewise. * gas/i386/i386.exp: Run bdver1 testcases. * gas/i386/arch-10-bdver2.d: Updated -march flags. * gas/i386/arch-10-btver1.d: Likewise. * gas/i386/arch-10-btver2.d: Likewise. * gas/i386/x86-64-arch-2-bdver2.d: Likewise. * gas/i386/x86-64-arch-2-btver1.d: Likewise. * gas/i386/x86-64-arch-2-btver2.d: Likewise.
2012-09-20Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu6-2964/+2989
gas/ * config/tc-i386.c (cpu_arch): Add .cx16. * doc/c-i386.texi: Document .cx16. gas/testsuite/ * gas/i386/x86-64-arch-2.s: Add test for cmpxchg16b. * gas/i386/x86-64-arch-2.d: Update correspondingly. * gas/i386/x86-64-arch-2-bdver2.d: Likewise. * gas/i386/x86-64-arch-2-btver1.d: Likewise. * gas/i386/x86-64-arch-2-btver2.d: Likewise. * gas/i386/x86-64-arch-2-lzcnt.d: Likewise. * gas/i386/x86-64-arch-2-prefetchw.d: Likewise. * gas/i386/ilp32/x86-64-arch-2.d: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS, CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS, CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS, CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS. (cpu_flags): Add CpuCX16. * i386-opc.h (CpuCX16): New. (i386_cpu_flags): Add cpucx16. * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b. * i386-tbl.h: Regenerate. * i386-init.h: Likewise.
2012-09-182012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw2-28/+33
opcodes: * arm-dis.c: Changed ldra and strl-form mnemonics to lda and stl-form. gas: * config/tc-arm.c: Changed ldra and strl-form mnemonics to lda and stl-form for armv8. gas/testsuite: * gas/arm/armv8-a-bad.l: Updated for changed mnemonics. * gas/arm/armv8-a-bad.s: Likewise. * gas/arm/armv8-a.d: Likewise. * gas/arm/armv8-a.s: Likewise. * gas/arm/inst.s: Added test for ldrt encoding compatibly with ldralt. * gas/arm/inst.d: Updated.
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