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2020-01-16[binutils][arm] PR25376 Change MVE into a CORE_HIGH featureAndre Vieira2-232/+248
This patch moves MVE feature bits into the CORE_HIGH section. This makes sure .fpu and -mfpu does not reset the bits set by MVE. This is important because .fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose to define MVE as an architecture extension rather than put it together with other the legacy fpu features. This will enable the following behavior: .arch armv8.1-m.main .arch mve .fpu fpv5-sp-d16 #does not disable mve. vadd.i32 q0, q1, q2 This patch also makes sure MVE is not taken into account during auto-detect. This was already the case, but because we moved the MVE bits to the architecture feature space we must make sure ARM_ANY does not include MVE. gas/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH. (armv8_1m_main_ext_table): Use CORE_HIGH for mve. * testsuite/arm/armv8_1-m-fpu-mve-1.s: New. * testsuite/arm/armv8_1-m-fpu-mve-1.d: New. * testsuite/arm/armv8_1-m-fpu-mve-2.s: New. * testsuite/arm/armv8_1-m-fpu-mve-2.d: New. include/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to... (ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space. (ARM_ANY): Redefine to not include any MVE bits. (ARM_FEATURE_ALL): Removed. opcodes/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. (neon_opcodes): Likewise. (select_arm_features): Make sure we enable MVE bits when selecting armv8.1-m.main. Make sure we do not enable MVE bits when not selecting any architecture.
2020-01-16x86: drop stale Vec_Imm4 related commentJan Beulich2-2/+4
I overlooked this in commit 9d3bf266fd ("x86: drop Vec_Imm4"), presumably because of the mis-spelling.
2020-01-16x86: add a few more missing VexWIGJan Beulich3-8/+14
Alternatively it could also be VexW0 (to match other SSE2AVX), but the VexW attribute shouldn't be left unset.
2020-01-16x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit modeJan Beulich3-20/+28
The AVX512DQ patterns lacking a Cpu64 attribute made the memory operand forms accepted even outside of 64-bit mode, and this even without any {evex} pseudo-prefix (otherwise one could argue that this is an attempt to follow one possible, albeit somewhat odd, interpretation of the SDM wording to this effect). For consistency between the various involved templates drop the * (now) unnecessary IgnoreSize attributes * unnecessary (due to VexW1) Size64 attributes from VEX encoded forms * redundant (with Reg64) Qword operand attributes uniformly.
2020-01-16tic4x disassembly static variablesAlan Modra2-31/+54
tic4x uses a number of static variables for tables that are generated depending on the current machine (tic4x vs. tic3x). However, it is possible to change the machine from one invocation of print_insn_tic4x to the next. This patch throws away the old state if that happens, and uses a relatively small known size array of register names rather than a malloc'd table. * tic4x-dis.c (tic4x_version): Make unsigned long. (optab, optab_special, registernames): New file scope vars. (tic4x_print_register): Set up registernames rather than malloc'd registertable. (tic4x_disassemble): Delete optable and optable_special. Use optab and optab_special instead. Throw away old optab, optab_special and registernames when info->mach changes.
2020-01-14Fix various assembler testsuite failures for the Z80 target.Sergey Belyashov2-1/+7
PR 25377 gas * config/tc-z80.c: Add support for half precision, single precision and double precision floating point values. * config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes. * doc/as.texi: Add new z80 command line options. * doc/c-z80.texi: Document new z80 command line options. * testsuite/gas/z80/ez80_pref_dis.s: New test. * testsuite/gas/z80/ez80_pref_dis.d: New test driver. * testsuite/gas/z80/z80.exp: Run the new test. * testsuite/gas/z80/fp_math48.d: Use correct command line option. * testsuite/gas/z80/fp_zeda32.d: Likewise. * testsuite/gas/z80/strings.d: Update expected output. opcodes * z80-dis.c (suffix): Use .db instruction to generate double prefix.
2020-01-14ubsan: z8k: left shift cannot be represented in type 'int'Alan Modra2-8/+13
* z8k-dis.c (unpack_instr): Formatting. Cast unsigned short values to unsigned before shifting.
2020-01-13Add an option to objdump's disassembler to generate ascii art diagrams ↵Thomas Troeger3-4/+113
showing the destinations of flow control instructions. binutils* objdump.c (visualize_jumps, color_output, extended_color_output) (detected_jumps): New variables. (usage): Add the new jump visualization options. (option_values): Add new option value. (long_options): Add the new option. (jump_info_new, jump_info_free): New functions. (jump_info_min_address, jump_info_max_address): Likewise. (jump_info_end_address, jump_info_is_start_address): Likewise. (jump_info_is_end_address, jump_info_size): Likewise. (jump_info_unlink, jump_info_insert): Likewise. (jump_info_add_front, jump_info_move_linked): Likewise. (jump_info_intersect, jump_info_merge): Likewise. (jump_info_sort, jump_info_visualize_address): Likewise. (disassemble_jumps): New function - used to locate jumps. (disassemble_bytes): Add ascii art generation. (disassemble_section): Add scan to locate jumps. (main): Parse the new visualization option. * doc/binutils.texi: Document the new feature. * NEWS: Mention the new feature. opcodes * arm-dis.c (print_insn_arm): Fill in insn info fields for control flow instructions. (print_insn_thumb16, print_insn_thumb32): Likewise. (print_insn): Initialize the insn info. * i386-dis.c (print_insn): Initialize the insn info fields, and detect jumps.
2020-01-13[ARC][committed] Code cleanup and improvements.Claudiu Zissulescu2-1/+5
Code clean up and improvements when changing the cpu from command line. Also, remove unused/old emulations. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change the CPU. * config/tc-arc.h: Add header if/defs. * testsuite/gas/arc/pseudos.d: Improve matching pattern. ls/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * Makefile.am: Remove earcelf_prof.c and earclinux_prof.c emulations. * Makefile.in: Regenerate. * configure.tgt: Likewise. * emulparams/arcelf_prof.sh: Remove file. * emulparams/arclinux_prof.sh: Likewise. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (C_NE): Make it required.
2020-01-13[ARC] [COMMITTED] Change ACCL/ACCH reg name to generic.Claudiu Zissulescu2-1/+6
ACCL/ACCH register names are only available for ARCv2 architecture, leading to a confusion when disassembling for any other ARC variants. This patch is changing the default names for ACCL/ACCH to generic r58/r59. 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo reserved register name.
2020-01-13asan: ns32k: wild memory writeAlan Modra2-6/+10
index_offset isn't set up for "sfsr", resulting in a random offset being used when trying to disassemble the following. .byte 0x3e, 0xf7, 0x07, 0x00 * ns32k-dis.c (Is_gen): Use strchr, add 'f'. (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2020-01-13ubsan: wasm32: signed integer overflowAlan Modra2-209/+243
The signed integer overflow occurred when adding one to target_count for (i = 0; i < target_count + 1; i++) but that's the least of the worries here. target_count was long and i int, leading to the possibility of a loop that never ended. So to avoid this type of vulnerability, this patch uses what I believe to be the proper types for arguments of various wasm32 opcodes, rather than using "long" which may change in size. gas/ * testsuite/gas/wasm32/allinsn.d: Update expected output. opcodes/ * wasm32-dis.c (print_insn_wasm32): Localise variables. Store result of wasm_read_leb128 in a uint64_t and check that bits are not lost when copying to other locals. Use uint32_t for most locals. Use PRId64 when printing int64_t.
2020-01-13score formattingAlan Modra3-812/+808
* score-dis.c: Formatting. * score7-dis.c: Formatting.
2020-01-13ubsan: score: left shift of negative valueAlan Modra3-24/+31
* score-dis.c (print_insn_score48): Use unsigned variables for unsigned values. Don't left shift negative values. (print_insn_score32): Likewise. * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2020-01-13tic4x: sign extension using shiftsAlan Modra2-2/+5
Don't do that. Especially don't use shift counts that assume the type being shifted is 32 bits when the type is long/unsigned long. Also reverts part of a change I made on 2019-12-11 to tic4x_print_register that on closer inspection turns out to be unnecessary. include/ * opcode/tic4x.h (EXTR): Delete. (EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign extension using shifts. Do trim INSERTU value to specified bitfield. opcodes/ * tic4x-dis.c (tic4x_print_register): Remove dead code. gas/ * config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap insertion.
2020-01-13ubsan: fr30: left shift of negative valueAlan Modra2-5/+9
cpu/ * fr30.cpu (f-disp9, f-disp10, f-s10, f-rel9, f-rel12): Don't left shift signed values. opcodes/ * fr30-ibld.c: Regenerate.
2020-01-13ubsan: xgate: left shift of negative valueAlan Modra2-8/+13
* xgate-dis.c (print_insn): Don't left shift signed value. (ripBits): Formatting, use 1u.
2020-01-10ubsan: tilepro: signed integer overflowAlan Modra3-11/+10
* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned. * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2020-01-10ubsan: m10300: shift exponent -4Alan Modra3-30/+24
* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG, and XRREG value earlier to avoid a shift with negative exponent. * m10200-dis.c (disassemble): Similarly.
2020-01-09Fix the cast used to prevent compile time warning about an always false test.Nick Clifton2-1/+6
PR 25224 * z80-dis.c (ld_ii_ii): Use correct cast.
2020-01-09Fix compile time warnings about comparisons always being false.Sergey Belyashov2-7/+13
PR 25224 gas * config/tc-z80.c (emit_ld_m_rr): Use integer types when checking opcode byte values. (emit_ld_r_r): Likewise. (emit_ld_rr_m): Likewise. (emit_ld_rr_nn): Likewise. opcodes * z80-dis.c (ld_ii_ii): Use character constant when checking opcode byte value.
2020-01-09x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMDJan Beulich4-10/+61
The disassembler change is such that in default mode we'd disassemble the insns (for there not ebing any conflicts), but when AMD64 mode was explicitly requested, we'd show them as "(bad)".
2020-01-08ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]'Alan Modra4-11/+26
The fix is the additional ARRAY_SIZE test, the rest just tidies variable types rather than adding a cast to avoid warnings. opcodes/ * z8k-dis.c: Include libiberty.h (instr_data_s): Make max_fetched unsigned. (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. Don't exceed byte_info bounds. (output_instr): Make num_bytes unsigned. (unpack_instr): Likewise for nibl_count and loop. * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and idx unsigned. * z8k-opc.h: Regenerate. gas/ * config/tc-z8k.c (md_begin): Make idx unsigned. (get_specific): Likewise for this_index.
2020-01-07[ARC] Add finer details for LLOCK and SCONDShahab Vahedi2-21/+30
This patch changes the "class" of LLOCK/SCOND from "MEMORY" to "LLOCK/SCOND" respectively. Moreover, it corrects the "data_size_mode". These changes are necessary for GDB's atmoic sequence handler. Signed-off-by: Shahab Vahedi <shahab@synopsys.com>
2020-01-06ubsan: m32c: left shift of negative valueAlan Modra2-61/+65
There are probably a lot more of these still here. cpu/ * m32c.cpu (f-dsp-8-u16, f-dsp-8-s16): Rearrange to mask any sign bits before shifting rather than masking after shifting. (f-dsp-16-u16, f-dsp-16-s16, f-dsp-32-u16, f-dsp-32-s16): Likewise. (f-dsp-40-u16, f-dsp-40-s16, f-dsp-48-u16, f-dsp-48-s16): Likewise. (f-dsp-64-u16, f-dsp-8-s24): Likewise. (f-bitbase32-16-s19-unprefixed): Avoid signed left shift. opcodes/ * m32c-ibld.c: Regenerate.
2020-01-06PR25344, z80 disassembler recursionAlan Modra2-29/+40
PR 25344 * z80-dis.c (suffix): Don't use a local struct buffer copy. Peek at next byte to prevent recursion on repeated prefix bytes. Ensure uninitialised "mybuf" is not accessed. (print_insn_z80): Don't zero n_fetch and n_used here,.. (print_insn_z80_buf): ..do it here instead.
2020-01-04ubsan: m32r: left shift of negative valueAlan Modra2-3/+7
cpu/ * m32r.cpu (f-disp8): Avoid left shift of negative values. (f-disp16, f-disp24): Likewise. opcodes/ * m32r-ibld.c: Regenerate.
2020-01-04ubsan: cr16: left shift cannot be represented in type 'int'Alan Modra2-2/+5
* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2020-01-04ubsan: crx: left shift cannot be represented in type 'int'Alan Modra2-1/+5
* crx-dis.c (match_opcode): Avoid shift left of signed value.
2020-01-04ubsan: d30v: left shift cannot be represented in type 'int'Alan Modra2-12/+10
* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2020-01-03Arm64: correct address index operands for LD1RO{H,W,D}Jan Beulich2-7/+12
Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03Arm64: correct {su,us}dot SIMD encodingsJan Beulich2-3/+8
According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms.
2020-01-03Arm64: correct uzp{1,2} mnemonicsJan Beulich3-4/+10
According to the specification, and in line with the pre-existing predicate forms, the mnemonics do not include an 'i'.
2020-01-03Arm64: correct 64-bit element fmmla encodingJan Beulich3-46/+52
There's just one bit of difference to the 32-bit element form, as per the documentation.
2020-01-02Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. ↵Sergey Belyashov3-532/+878
Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-01Re: Update year range in copyright notice of binutils filesAlan Modra1-0/+4
Add the ChangeLog entry.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra275-279/+279
2020-01-01ChangeLog rotationAlan Modra2-2444/+2458
2019-12-30Re: Usage of unitialized heap in tic4x_print_condAlan Modra2-1/+6
PR 25319 * tic4x-dis.c (tic4x_print_cond): Correct order of xcalloc args.
2019-12-29ubsan: sparc: left shift cannot be represented in type 'int'Alan Modra2-9/+12
* sparc-dis.c (SEX): Don't use left and right shift to sign extend. (compare_opcodes): Avoid signed shift left overflow. (print_insn_sparc): Likewise.
2019-12-29Usage of unitialized heap in tic4x_print_condAlan Modra2-1/+6
PR 25319 * tic4x-dis.c (tic4x_print_cond): Init all of condtable.
2019-12-27x86-64: fix Intel64 handling of branch with data16 prefixJan Beulich2-3/+14
The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious direct destination to translate to an indirect _far_ branch is plain wrong. The operand size prefix should have no effect at all on the interpretation of the operand. The main underlying issue here is that the Intel64 templates of the direct branches don't include Disp16, yet various assumptions exist that it would always be there when there's also Disp32/Disp32S, toggled by the operand size prefix (which is being ignored by direct branches in Intel64 mode). Along these lines it was also wrong to base the displacement width decision solely on the operand size prefix: REX.W cancels this effect and hence needs taking into consideration, too. A disassembler change is needed here as well: XBEGIN was wrongly treated the same as direct CALL/JMP, which isn't the case - the operand size prefix does affect displacement size there, it's merely ignored when it comes to updating [ER]IP.
2019-12-27x86: consolidate Disp<NN> handling a littleJan Beulich4-121/+115
In memory operand addressing, which forms of displacement are permitted besides Disp8 is pretty clearly limited - outside of 64-bit mode, Disp16 or Disp32 only, depending on address size (MPX being special in not allowing Disp16), - in 64-bit mode, Disp32s or Disp64 without address size override, and solely Disp32 with one. Adjust assembler and i386-gen to match this, observing that templates already get adjusted before trying to match them against input depending on the presence of an address size prefix. This adjustment logic gets extended to all cases, as certain DispNN values should also be dropped when there's no such prefix. In fact behavior of the assembler, perhaps besides the exact diagnostics wording, should not differ between there being templates applicable to 64-bit and non-64-bit at the same time, or there being fully separate sets of templates, with their DispNN settings already reduced accordingly. This adjustment logic further gets guarded such that there wouldn't be and Disp<N> conversion based on address size prefix when this prefix doesn't control the width of the displacement (on branches other than absolute ones). These adjustments then also allow folding two MOV templates, which had been split between 64-bit and non-64-bits variants so far. Once in this area also - drop the bogus DispNN from JumpByte templates, leaving just the correct Disp8 there (compensated by i386_finalize_displacement() now setting Disp8 on their operands), - add the missing Disp32S to XBEGIN. Note that the changes make it necessary to temporarily mark a test as XFAIL; this will get taken care of by a subsequent patch. The failing parts are entirely bogus and will get replaced.
2019-12-26ubsan: crx: index 5 out of bounds for type 'operand_desc const[5]'Alan Modra2-1/+6
* crx-dis.c (get_number_of_operands): Don't access operands[] out of bounds.
2019-12-26ubsan: v850: left shift cannot be represented in type 'int'Alan Modra2-7/+12
Another 1 << 31 complaint. * v850-dis.c (disassemble): Avoid signed overflow. Don't use long vars when unsigned int will do.
2019-12-24ubsan: arm: shift exponent 32 is too large for 32-bit type 'unsigned int'Alan Modra2-3/+7
* arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
2019-12-23ppc: misc minor build correctionsJan Beulich3-8/+14
Avoid shadowing a libiberty symbol (which oldish gcc warns about by default), and allow building cleanly on 32-bit distros.
2019-12-23ubsan: score: left shift of 2 by 31 places cannot be represented in type 'int'Alan Modra2-25/+28
* score-dis.c (print_insn_score32): Avoid signed overflow. (print_insn_score48): Likewise. Don't cast to int when printing hex values.
2019-12-23ubsan: iq2000: left shift of negative valueAlan Modra2-1/+5
cpu/ * iq2000.cpu (f-offset): Avoid left shift of negative values. opcodes/ * iq2000-ibld.c: Regenerate.
2019-12-23ubsan: d30v: left shift cannot be represented in type 'long long'Alan Modra2-17/+25
* d30v-dis.c (extract_value): Make num param a uint64_t, constify oper. Use unsigned vars. (print_insn): Make num var uint64_t. Constify oper and remove now unnecessary casts on extract_value calls. (print_insn_d30v): Use unsigned vars. Adjust printf formats.
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