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2018-12-28PR24028, PPC_INT_FMTAlan Modra2-10/+16
2018-12-18Include bfd_stdint.h in bfd.hAlan Modra8-6/+17
2018-12-07RISC-V: Fix 4-arg add parsing.Jim Wilson2-1/+6
2018-12-06sim/opcodes: Allow use of out of tree cgen source directoryAndrew Burgess3-8/+26
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess3-0/+28
2018-12-03RISC-V: Accept version, supervisor ext and more than one NSE for -march.Jim Wilson2-1/+6
2018-12-03[aarch64] - Only use MOV for disassembly when shifter op is LSL #0Egeyar Bagcioglu2-1/+8
2018-11-29RISC-V: Add missing c.unimp instruction.Jim Wilson2-1/+7
2018-11-27RISC-V: Add .insn CA support.Jim Wilson2-2/+12
2018-11-21S12Z opcodes: Fix bug disassembling certain shift instructions.John Darrington2-19/+30
2018-11-13opcodes/nfp: Fix disassembly of crc[] with swapped operands.Francois H. Theron2-6/+10
2018-11-12[BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Exten...Sudakshina Das2-0/+48
2018-11-12[BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging ExtensionSudakshina Das2-0/+35
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das10-1642/+1724
2018-11-12[BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das5-1607/+1633
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das8-1841/+2036
2018-11-12[BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Taggin...Sudakshina Das5-1904/+1942
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das9-2913/+3010
2018-11-12[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-ASudakshina Das2-0/+10
2018-11-06[BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros.Sudakshina Das2-5/+10
2018-11-06PowerPC instruction mask checksAlan Modra2-141/+72
2018-11-06x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit modeJan Beulich2-1/+6
2018-11-06x86: correctly handle VMOVD with EVEX.W set outside of 64-bit modeJan Beulich3-14/+8
2018-11-06x86: correctly handle KMOVD with VEX.W set outside of 64-bit modeJan Beulich2-32/+17
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich5-62/+47
2018-11-06x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich3-32/+39
2018-11-06x86: fix various non-LIG templatesJan Beulich3-86/+106
2018-11-06x86: allow {store} to select alternative {,}PEXTRW encodingJan Beulich3-11/+16
2018-11-06x86: add more VexWIGJan Beulich3-285/+293
2018-11-06x86: XOP VPHADD* / VPHSUB* are VEX.W0Jan Beulich3-32/+40
2018-10-23S/390: Support vector alignment hintsAndreas Krebbel1-0/+7
2018-10-22S12Z: Disassembly: Fallback to show the address if the symbol table is empty.John Darrington2-0/+9
2018-10-19Arm: Fix disassembler crashing on -b binary when thumb file and thumb not for...Tamar Christina2-3/+14
2018-10-16AArch64: Fix error checking for SIMD udot (by element)Matthew Malcomson2-1/+7
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich5-15577/+11696
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das2-0/+23
2018-10-09[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registersSudakshina Das2-0/+26
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das8-1136/+1182
2018-10-09[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das2-0/+16
2018-10-09[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instructionSudakshina Das2-0/+11
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das7-1089/+1147
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das5-1014/+1030
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das5-2644/+2766
2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das2-0/+11
2018-10-08AArch64: Replace C initializers with memsetTamar Christina2-1/+7
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu4-1/+22
2018-10-05[Arm, 2/3] Add instruction SB for AArch32Sudakshina Das2-0/+11
2018-10-05or1k: Add the l.muld, l.muldu, l.macu, l.msbu insnsRichard Henderson6-29/+163
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne9-137/+320
2018-10-05or1k: Add relocations for high-signed and low-storesRichard Henderson2-272/+172
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