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2021-11-29opcodes: enable silent build rulesMike Frysinger4-54/+94
Also add $(AM_V_xxx) to various manual rules in here.
2021-11-26opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess2-9/+147
In preparation for the next commit, which will add GDB support for RISC-V disassembler options, this commit restructures how the disassembler options are managed within libopcodes. The implementation provided here is based on this mailing list patch which was never committed: https://sourceware.org/pipermail/binutils/2021-January/114944.html which in turn took inspiration from the MIPS implementation of the same feature. The biggest changes from the original mailing list post are: 1. The GDB changes have been split into a separate patch, and 2. The `riscv_option_args_privspec` variable, which held the valid priv-spec values is now gone, instead we use the `riscv_priv_specs` array from bfd/cpu-riscv.c instead. Co-authored-by: Simon Cook <simon.cook@embecosm.com> include/ChangeLog: * dis-asm.h (disassembler_options_riscv): Declare. opcodes/ChangeLog: * riscv-dis.c (enum riscv_option_arg_t): New enum typedef. (riscv_options): New static global. (disassembler_options_riscv): New function. (print_riscv_disassembler_options): Rewrite to use disassembler_options_riscv.
2021-11-25Fix building the AArch64 assembler and disassembler when assertions are ↵Nick Clifton4-32/+45
disabled. PR 28614 * aarch64-asm.c: Replace assert(0) with real code. * aarch64-dis.c: Likewise. * aarch64-opc.c: Likewise.
2021-11-25Updated French translation for the opcodes directory.Nick Clifton2-236/+264
* po/fr.po; Updated French translation.
2021-11-23Update bug reporting addressAlan Modra1-1/+1
https://sourceware.org/bugzilla/ everywhere bfd/ * configure.ac (ACX_BUGURL): Set to https://sourceware.org/bugzilla/ * po/Make-in (msgid-bugs-address): Likewise. * README: Report bugs to the above. * configure: Regenerate. binutils/ * po/Make-in (msgid-bugs-address): Update. gas/ * README: Update bug address. Delete mention of gcc. * po/Make-in: Update bug address. gold/ * po/Make-in: Update bug address. gprof/ * po/Make-in: Update bug address. ld/ * po/Make-in: Update bug address. opcodes/ * po/Make-in: Update bug address.
2021-11-18Re: Don't compile some opcodes files when bfd is 32-bit onlyAlan Modra2-10/+10
Put bpf back in the 32-bit targets, even though bpf requires a 64-bit bfd. bpf sim support apparently works without being 64-bit. * Makefile.am (TARGET64_LIBOPCODES_CFILES): Move bpf files.. (TARGET32_LIBOPCODES_CFILES): ..to here. * Makefile.in: Regenerate.
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei2-148/+152
Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to verify if z*inx enabled and use gpr instead of fpr when z*inx is enable. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added support for z*inx extension. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Added register choice for z*inx. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Added disassemble check for z*inx. * riscv-opc.c: Reused INSN_CLASS_* for z*inx. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus10-191/+387
This patch is adding new SVE2 instructions added to support SME extension. The following SVE2 instructions are added by the SME architecture: * PSEL, * REVD, SCLAMP and UCLAMP. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_pred_reg_with_index): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-9-illegal.d: New test. * testsuite/gas/aarch64/sme-9-illegal.l: New test. * testsuite/gas/aarch64/sme-9-illegal.s: New test. * testsuite/gas/aarch64/sme-9.d: New test. * testsuite/gas/aarch64/sme-9.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_PnT_Wm_imm. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index): New inserter. * aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index): New extractor. * aarch64-opc.c (aarch64_print_operand): Printout of OPND_SME_PnT_Wm_imm. * aarch64-opc.h (enum aarch64_field_kind): New bitfields FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl. * aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier. (OP_SVE_QMQ): New qualifier. (struct aarch64_opcode): New instructions PSEL, REVD, SCLAMP and UCLAMP. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add new SME system registersPrzemyslaw Wirkus1-1/+11
This patch is adding miscellaneous SME related system registers. gas/ChangeLog: * testsuite/gas/aarch64/sme-sysreg.d: New test. * testsuite/gas/aarch64/sme-sysreg.s: New test. * testsuite/gas/aarch64/sme-sysreg-illegal.d: New test. * testsuite/gas/aarch64/sme-sysreg-illegal.l: New test. * testsuite/gas/aarch64/sme-sysreg-illegal.s: New test. opcodes/ChangeLog: * aarch64-opc.c: New system registers id_aa64smfr0_el1, smcr_el1, smcr_el12, smcr_el2, smcr_el3, smpri_el1, smprimap_el2, smidr_el1, tpidr2_el0 and mpamsm_el1.
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus10-1514/+1641
This patch is adding new SME mode selection and state access instructions: * Add SMSTART and SMSTOP instructions. * Add SVCR system register. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_sm_za): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-8-illegal.d: New test. * testsuite/gas/aarch64/sme-8-illegal.l: New test. * testsuite/gas/aarch64/sme-8-illegal.s: New test. * testsuite/gas/aarch64/sme-8.d: New test. * testsuite/gas/aarch64/sme-8.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_SM_ZA. (enum aarch64_insn_class): New instruction classes sme_start and sme_stop. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_pstatefield): New inserter. (aarch64_ins_sme_sm_za): New inserter. * aarch64-dis.c (aarch64_ext_imm): New extractor. (aarch64_ext_pstatefield): New extractor. (aarch64_ext_sme_sm_za): New extractor. * aarch64-opc.c (operand_general_constraint_met_p): New pstatefield value for SME instructions. (aarch64_print_operand): Printout for OPND_SME_SM_ZA. (SR_SME): New register SVCR. * aarch64-opc.h (F_REG_IN_CRM): New register endcoding. * aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding. (PSTATE_ENCODE_CRM): Encode CRm field. (PSTATE_DECODE_CRM): Decode CRm field. (PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field. (PSTATE_DECODE_CRM_IMM): Decode CRm immediate field. (PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate field. * aarch64-tbl.h (struct aarch64_opcode): New SMSTART and SMSTOP instructions. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus9-236/+605
This patch is adding new loads and stores defined by SME instructions. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_address): New parser. (parse_sme_za_hv_tiles_operand_with_braces): New parser. (parse_sme_za_array): New parser. (output_operand_error_record): Print error details if present. (parse_operands): Support new operands. * testsuite/gas/aarch64/sme-5-illegal.d: New test. * testsuite/gas/aarch64/sme-5-illegal.l: New test. * testsuite/gas/aarch64/sme-5-illegal.s: New test. * testsuite/gas/aarch64/sme-5.d: New test. * testsuite/gas/aarch64/sme-5.s: New test. * testsuite/gas/aarch64/sme-6-illegal.d: New test. * testsuite/gas/aarch64/sme-6-illegal.l: New test. * testsuite/gas/aarch64/sme-6-illegal.s: New test. * testsuite/gas/aarch64/sme-6.d: New test. * testsuite/gas/aarch64/sme-6.s: New test. * testsuite/gas/aarch64/sme-7-illegal.d: New test. * testsuite/gas/aarch64/sme-7-illegal.l: New test. * testsuite/gas/aarch64/sme-7-illegal.s: New test. * testsuite/gas/aarch64/sme-7.d: New test. * testsuite/gas/aarch64/sme-7.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operands. (enum aarch64_insn_class): Added sme_ldr and sme_str. (AARCH64_OPDE_UNTIED_IMMS): New operand error kind. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. (aarch64_ins_sme_za_list): New inserter. (aarch64_ins_sme_za_array): New inserter. (aarch64_ins_sme_addr_ri_u4xvl): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): Added ins_sme_za_list, ins_sme_za_array and ins_sme_addr_ri_u4xvl. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. (aarch64_ext_sme_za_list): New extractor. (aarch64_ext_sme_za_array): New extractor. (aarch64_ext_sme_addr_ri_u4xvl): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): Added ext_sme_za_list, ext_sme_za_array and ext_sme_addr_ri_u4xvl. * aarch64-opc.c (operand_general_constraint_met_p): (aarch64_match_operands_constraint): Handle sme_ldr, sme_str and sme_misc. (aarch64_print_operand): New operands supported. * aarch64-tbl.h (OP_SVE_QUU): New qualifier. (OP_SVE_QZU): New qualifier. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus6-140/+204
This patch is adding ZERO (a list of 64-bit element ZA tiles) instruction. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_list_of_64bit_tiles): New parser. (parse_operands): Handle OPND_SME_list_of_64bit_tiles. * testsuite/gas/aarch64/sme-4-illegal.d: New test. * testsuite/gas/aarch64/sme-4-illegal.l: New test. * testsuite/gas/aarch64/sme-4-illegal.s: New test. * testsuite/gas/aarch64/sme-4.d: New test. * testsuite/gas/aarch64/sme-4.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_list_of_64bit_tiles. opcodes/ChangeLog: * aarch64-opc.c (print_sme_za_list): New printing function. (aarch64_print_operand): Handle OPND_SME_list_of_64bit_tiles. * aarch64-opc.h (enum aarch64_field_kind): New bitfield FLD_SME_zero_mask. * aarch64-tbl.h (struct aarch64_opcode): New ZERO instruction. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus10-175/+363
This patch is adding new MOV (alias) and MOVA SME instruction. gas/ChangeLog: * config/tc-aarch64.c (enum sme_hv_slice): new enum. (struct reloc_entry): Added ZAH and ZAV registers. (parse_sme_immediate): Immediate parser. (parse_sme_za_hv_tiles_operand): ZA tile parser. (parse_sme_za_hv_tiles_operand_index): Index parser. (parse_operands): Added ZA tile parser calls. (REGNUMS): New macro. Regs with suffix. (REGSET16S): New macro. 16 regs with suffix. * testsuite/gas/aarch64/sme-2-illegal.d: New test. * testsuite/gas/aarch64/sme-2-illegal.l: New test. * testsuite/gas/aarch64/sme-2-illegal.s: New test. * testsuite/gas/aarch64/sme-2.d: New test. * testsuite/gas/aarch64/sme-2.s: New test. * testsuite/gas/aarch64/sme-2a.d: New test. * testsuite/gas/aarch64/sme-2a.s: New test. * testsuite/gas/aarch64/sme-3-illegal.d: New test. * testsuite/gas/aarch64/sme-3-illegal.l: New test. * testsuite/gas/aarch64/sme-3-illegal.s: New test. * testsuite/gas/aarch64/sme-3.d: New test. * testsuite/gas/aarch64/sme-3.s: New test. * testsuite/gas/aarch64/sme-3a.d: New test. * testsuite/gas/aarch64/sme-3a.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New enums AARCH64_OPND_SME_ZA_HV_idx_src and AARCH64_OPND_SME_ZA_HV_idx_dest. (struct aarch64_opnd_info): New ZA tile vector struct. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_sme_za_hv_tiles. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_sme_za_hv_tiles. * aarch64-opc.c (aarch64_print_operand): Handle SME_ZA_HV_idx_src and SME_ZA_HV_idx_dest. * aarch64-opc.h (enum aarch64_field_kind): New enums FLD_SME_size_10, FLD_SME_Q, FLD_SME_V and FLD_SME_Rv. (struct aarch64_operand): Increase fields size to 5. * aarch64-tbl.h (OP_SME_BHSDQ_PM_BHSDQ): New qualifiers aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus6-133/+547
Patch is adding new SME matrix instructions. Please note additional instructions will be added in following patches. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_zada_operand): New parser. * config/tc-aarch64.c (parse_reg_with_qual): New reg parser. * config/tc-aarch64.c (R_ZA): New egister type. (parse_operands): New parser. * testsuite/gas/aarch64/sme-illegal.d: New test. * testsuite/gas/aarch64/sme-illegal.l: New test. * testsuite/gas/aarch64/sme-illegal.s: New test. * testsuite/gas/aarch64/sme.d: New test. * testsuite/gas/aarch64/sme.s: New test. * testsuite/gas/aarch64/sme-f64.d: New test. * testsuite/gas/aarch64/sme-f64.s: New test. * testsuite/gas/aarch64/sme-i64.d: New test. * testsuite/gas/aarch64/sme-i64.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operands AARCH64_OPND_SME_ZAda_2b, AARCH64_OPND_SME_ZAda_3b and AARCH64_OPND_SME_Pm. (enum aarch64_insn_class): New instruction class sme_misc. opcodes/ChangeLog: * aarch64-opc.c (aarch64_print_operand): Print OPND_SME_ZAda_2b and OPND_SME_ZAda_3b operands. (verify_constraints): Handle OPND_SME_Pm. * aarch64-opc.h (enum aarch64_field_kind): New bit fields FLD_SME_ZAda_2b, FLD_SME_ZAda_3b and FLD_SME_Pm. * aarch64-tbl.h (OP_SME_ZADA_PN_PM_ZN_S): New qualifier set. (OP_SME_ZADA_PN_PM_ZN_D): New qualifier. (OP_SME_ZADA_PN_PM_ZN_ZM): New qualifier. (OP_SME_ZADA_S_PM_PM_S_S): New qualifier. (OP_SME_ZADA_D_PM_PM_D_D): New qualifier. (OP_SME_ZADA_S_PM_PM_H_H): New qualifier. (OP_SME_ZADA_S_PM_PM_B_B): New qualifier. (OP_SME_ZADA_D_PM_PM_H_H): New qualifier. (SME_INSN): New instruction macro. (SME_F64_INSN): New instruction macro. (SME_I64_INSN): New instruction macro. (SME_INSNC): New instruction macro. (struct aarch64_opcode): New SME instructions. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus1-0/+11
This series of patches (tagged [SME]) add support for the Scalable Matrix Extension. Patch introduces new command line options: +sme, +sme-f64 and +sme-i64 to -march command line options. gas/ChangeLog: * NEWS: Updated docs. * config/tc-aarch64.c: New SME command line options. * doc/c-aarch64.texi: Update docs. include/ChangeLog: * opcode/aarch64.h (AARCH64_FEATURE_SME): New flag. (AARCH64_FEATURE_SME_F64): New flag. (AARCH64_FEATURE_SME_I64): New flag. opcodes/ChangeLog: * aarch64-tbl.h (SME): New feature object.
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu2-0/+893
2021-11-17 Jim Wilson <jimw@sifive.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> This patch is porting from the following riscv github, https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x And here is the vector spec, https://github.com/riscv/riscv-v-spec bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules of v, zve and zvl extensions. (riscv_supported_std_ext): Updated verison of v to 1.0. (riscv_supported_std_z_ext): Added zve and zvl extensions. (riscv_parse_check_conflicts): The zvl extensions need to enable either v or zve extension. (riscv_multi_subset_supports): Check the subset list to know if the INSN_CLASS_V and INSN_CLASS_ZVEF instructions are supported. gas/ * config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_V. (enum reg_class): Added RCLASS_VECR and RCLASS_VECM. (validate_riscv_insn): Check whether the rvv operands are valid. (md_begin): Initialize register hash for rvv registers. (macro_build): Added rvv operands when expanding rvv pseudoes. (vector_macro): Expand rvv macros into one or more instructions. (macro): Likewise. (my_getVsetvliExpression): Similar to my_getVsetvliExpression, but used for parsing vsetvli operands. (riscv_ip): Parse and encode rvv operands. Besides, The rvv loads and stores with EEW 64 cannot be used when zve32x is enabled. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Updated -march to rv32ifv_zkr. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg.s: Added rvv csr testcases. * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. * testsuite/gas/riscv/march-imply-v.d: New testcase. * testsuite/gas/riscv/vector-insns-fail-zve32xf.d: Likewise. * testsuite/gas/riscv/vector-insns-fail-zve32xf.l: Likewise. * testsuite/gas/riscv/vector-insns-fail-zvl.d: Likewise. * testsuite/gas/riscv/vector-insns-fail-zvl.l: Likewise. * testsuite/gas/riscv/vector-insns-vmsgtvx.d: Likewise. * testsuite/gas/riscv/vector-insns-vmsgtvx.s: Likewise. * testsuite/gas/riscv/vector-insns-zero-imm.d: Likewise. * testsuite/gas/riscv/vector-insns-zero-imm.s: Likewise. * testsuite/gas/riscv/vector-insns.d: Likewise. * testsuite/gas/riscv/vector-insns.s: Likewise. include/ * opcode/riscv-opc.h: Defined mask/match encodings and csrs for rvv. * opcode/riscv.h: Defined rvv immediate encodings and fields. (enum riscv_insn_class): Added INSN_CLASS_V and INSN_CLASS_ZVEF. (INSN_V_EEW64): Defined. (M_VMSGE, M_VMSGEU): Added for the rvv pseudoes. opcodes/ * riscv-dis.c (print_insn_args): Dump the rvv operands. * riscv-opc.c (riscv_vecr_names_numeric): Defined rvv registers. (riscv_vecm_names_numeric): Likewise. (riscv_vsew): Likewise. (riscv_vlmul): Likewise. (riscv_vta): Likewise. (riscv_vma): Likewise. (match_vs1_eq_vs2): Added for rvv Vu operand. (match_vd_eq_vs1_eq_vs2): Added for rvv Vv operand. (riscv_opcodes): Added rvv v1.0 instructions.
2021-11-16RISC-V: Scalar crypto instructions and operand set.jiawei2-20/+80
Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from zbb,zbc, we just change the class attribute to make them both support. The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd and Zkne extensions on rv64. Add new operand letter 'y' to present 'bs' symbol and 'Y' to present 'rnum' symbolc for zkn instructions. Also add a new Entropy Source CSR define 'seed' located at address 0x015. bfd/ * elfxx-riscv.c (riscv_multi_subset_supports): Added support for crypto extension. gas/ *config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_ZKR. (riscv_csr_address): Checked for CSR_CLASS_ZKR. (validate_riscv_insn): Added y and Y for bs and rnum operands. (riscv_ip): Handle y and Y operands. include/ * opcode/riscv-opc.h: Added encodings of crypto instructions. Also defined new csr seed, which address is 0x15. * opcode/riscv.h: Defined OP_* and INSN_CLASS_* for crypto. opcodes/ * riscv-dis.c (print_insn_args): Recognized new y and Y operands. * riscv-opc.c (riscv_opcodes): Added crypto instructions.
2021-11-12Don't compile some opcodes files when bfd is 32-bit onlyAlan Modra5-56/+74
* Makefile.am (TARGET_LIBOPCODES_CFILES): Split into.. (TARGET64_LIBOPCODES_CFILES): ..this and.. (TARGET32_LIBOPCODES_CFILES): ..this. (ALL_MACHINES): Likewise split to (ALL64_MACHINES, ALL32_MACHINES): ..this. * disassemble.c: Define some ARCH_* when ARCH_all only if BFD64. * configure.ac (BFD_MACHINES): Defined depending on BFD_ARCH_SIZE. * Makefile.in: Regenerate. * configure: Regenerate.
2021-11-11RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu1-6/+26
For now we should always generate the elf architecture attribute both for elf and linux toolchains, so that we could dump the objects correctly according to the generated architecture string. This patch resolves the problem that we probably dump an object with c.nop instructions, but in fact the c extension isn't allowed. Consider the following case, nelson@LAPTOP-QFSGI1F2:~/test$ cat temp.s .option norvc .option norelax .text add a0, a0, a0 .byte 0x1 .balign 16 nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-as temp.s -o temp.o nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o temp.o: file format elf32-littleriscv Disassembly of section .text: 00000000 <.text>: 0: 00a50533 add a0,a0,a0 4: 01 .byte 0x01 5: 00 .byte 0x00 6: 0001 nop 8: 00000013 nop c: 00000013 nop nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-readelf -A temp.o Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0" The c.nop at address 0x6 is generated for alignment, but since the rvc isn't allowed for this object, dump it as a c.nop instruction looks wrong. After applying this patch, I get the following result, nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o temp.o: file format elf32-littleriscv Disassembly of section .text: 00000000 <.text>: 0: 00a50533 add a0,a0,a0 4: 01 .byte 0x01 5: 00 .byte 0x00 6: 0001 .2byte 0x1 8: 00000013 nop c: 00000013 nop For the current objdump, we dump data to .byte/.short/.word/.dword, and dump the unknown or unsupported instructions to .2byte/.4byte/.8byte, which respectively are 2, 4 and 8 bytes instructions. Therefore, we shouldn't dump the 0x0001 as a c.nop instruction in the above case, we should dump it to .2byte 0x1 as a unknown instruction, since the rvc is disabled. However, consider that some people may use the new objdump to dump the old objects, which don't have any elf attributes. We usually set the default architecture string to rv64g by bfd/elfxx-riscv.c:riscv_set_default_arch. But this will cause rvc instructions to be unrecognized. Therefore, we set the default architecture string to rv64gc for disassembler, to keep the previous behavior. This patch pass the riscv-gnu-toolchain gcc/binutils regressions for rv32emc-elf, rv32gc-linux, rv32i-elf, rv64gc-elf and rv64gc-linux toolchains. Also, tested by --enable-targets=all and can build riscv-gdb successfully. bfd/ * elfnn-riscv.c (riscv_merge_arch_attr_info): Tidy the codes for riscv_parse_subset_t setting. * elfxx-riscv.c (riscv_get_default_ext_version): Updated. (riscv_subset_supports): Moved from gas/config/tc-riscv.c. (riscv_multi_subset_supports): Likewise. * elfxx-riscv.h: Added extern for riscv_subset_supports and riscv_multi_subset_supports. gas/ * config/tc-riscv.c (riscv_subset_supports): Moved to bfd/elfxx-riscv.c. (riscv_multi_subset_supports): Likewise. (riscv_rps_as): Defined for architectrue parser. (riscv_set_arch): Updated. (riscv_set_abi_by_arch): Likewise. (riscv_csr_address): Likewise. (reg_lookup_internal): Likewise. (riscv_ip): Likewise. (s_riscv_option): Updated. * testsuite/gas/riscv/mapping-04b.d: Updated. * testsuite/gas/riscv/mapping-norelax-03b.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04b.d: Likewise. opcodes/ * riscv-dis.c: Include elfxx-riscv.h since we need the architecture parser. Also removed the cpu-riscv.h, it is already included in elfxx-riscv.h. (default_isa_spec): Defined since the parser need this to set the default architecture string. (xlen): Moved out from riscv_disassemble_insn as a global variable, it is more convenient to initialize riscv_rps_dis. (riscv_subsets): Defined to recoed the supported extensions. (riscv_rps_dis): Defined for architectrue parser. (riscv_disassemble_insn): Call riscv_multi_subset_supports to make sure if the instructions are valid or not. (print_insn_riscv): Initialize the riscv_subsets by parsing the elf architectrue attribute. Otherwise, set the default architectrue string to rv64gc.
2021-11-05Missing va_end in aarch64-dis.cAlan Modra1-0/+1
* aarch64-dis.c (extract_fields): Invoke va_end.
2021-11-02opcodes: d10v: simplify header includesMike Frysinger1-2/+1
This file doesn't use anything from bfd (sysdep.h), so drop that include. This avoids an implicit dependency on the generated config.h which can be problematic for build-time tools. Also swap stdio.h for stddef.h. This file isn't doing or using any I/O structures, but it does need NULL.
2021-11-01arm: add armv9-a architecture to -marchPrzemyslaw Wirkus1-3/+2
Update also include: + New value of Tag_CPU_arch EABI attribute (22) is added. + Updated missing Tag_CPU_arch EABI attributes. + Updated how we combine archs 'v4t_plus_v6_m' as this mechanism have to handle new Armv9 as well. Regression tested on `arm-none-eabi` cross Binutils and no issues. bfd/ * archures.c: Define bfd_mach_arm_9. * bfd-in2.h (bfd_mach_arm_9): Define bfd_mach_arm_9. * cpu-arm.c: Add 'armv9-a' option to -march. * elf32-arm.c (using_thumb2_bl): Update assert check. (arch_has_arm_nop): Add TAG_CPU_ARCH_V9. (bfd_arm_get_mach_from_attributes): Add case for TAG_CPU_ARCH_V9. Update assert. (tag_cpu_arch_combine): Updated table. (v9): New table.. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Update with elfcpp/ * arm.h: Update TAG_CPU_ARCH_ enums with correct values. gas/ * NEWS: Update docs. * config/tc-arm.c (get_aeabi_cpu_arch_from_fset): Return Armv9-a for -amarch=all. (aeabi_set_public_attributes): Update assert. * doc/c-arm.texi: Update docs. * testsuite/gas/arm/armv9-a_arch.d: New test. * testsuite/gas/arm/attr-march-all.d: Update test with v9. include/ * elf/arm.h Update TAG_CPU_ARCH_ defines with correct values. * opcode/arm.h (ARM_EXT3_V9A): New macro. (ARM_ARCH_NONE): Updated with arm_feature_set.core size. (FPU_NONE): Updated. (ARM_ANY): Updated. (ARM_ARCH_UNKNOWN): New macro. (ARM_FEATURE_LOW): Updated. (ARM_FEATURE_CORE): Updated. (ARM_FEATURE_CORE_LOW): Updated. (ARM_FEATURE_CORE_HIGH): Updated. (ARM_FEATURE_COPROC): Updated. (ARM_FEATURE): Updated. (ARM_FEATURE_ALL): New macro. opcodes/ * arm-dis.c (select_arm_features): Support bfd_mach_arm_9. Also Update bfd_mach_arm_unknown to use new macro ARM_ARCH_UNKNOWN.
2021-10-28ubsan: arm: undefined shiftAlan Modra1-1/+1
left shift of 2 by 31 places cannot be represented in type 'int' * arm-dis.c (print_insn_thumb16): Avoid undefined behaviour.
2021-10-27RISC-V: Tidy riscv assembler and disassembler.Nelson Chu1-8/+10
Tidy the gas/config/tc-riscv.c and opcodes/riscv-dis.c, to prepare for moving the released extensions (including released vendor extensions) from integration branch back to mainline. * Added parts of missing comments. * Updated md_show_usage. * For validate_riscv_insn, riscv_ip and print_insn_args, unify the following pointer names, - oparg: pointed to the parsed operand defined in the riscv_opcodes. - asarg: pointed to the parsed operand from assembly. - opargStart: recorded the parsed operand name from riscv_opcodes. - asargStart: recorded the parsed operand name from assembly. gas/ * config/tc-riscv.c: Added parts of missind comments and updated the md_show_usage. (riscv_multi_subset_supports): Tidy codes. (validate_riscv_insn): Unify the pointer names, oparg, asarg, opargStart and asargStart, to prepare for moving the released extensions from integration branch back to mainline. (riscv_ip): Likewise. (macro_build): Added fmtStart, also used to prepare for moving released extensions. (md_show_usage): Added missing descriptions for new options. opcodes/ * riscv-dis.c (print_insn_args): Unify the pointer names, oparg and opargStart, to prepare for moving the released extensions from integration branch back to mainline.
2021-10-27opcodes: Fix RPATH not being set for dynamic libbfd dependencyMaciej W. Rozycki5-36/+10
If built as a shared library, libopcodes has a load-time dependency on libbfd, which is recorded in the dynamic section, however without a corresponding RPATH entry for the directory to find libbfd in. This causes loading to fail whenever libbfd is only pulled by libopcodes indirectly and libbfd has been installed in a directory that is not in the dynamic loader's search path. It does not happen with the programs included with binutils or GDB, because they all also pull libbfd when using libopcodes, but it can happen with external software, e.g.: $ gdbserver --help gdbserver: error while loading shared libraries: libbfd-[...].so: cannot open shared object file: No such file or directory $ (not our `gdbserver'). Indirect dynamic dependencies are handled by libtool automatically by adding RPATH entries as required, however our setup for libopcodes prevents this from happening by linking in libbfd with an explicit file reference sneaked through to the linker directly behind libtool's back via the `-Wl' linker command-line option rather than via `-l' combined with a suitable library search path specified via `-L', as it would be usually the case, or just referring to the relevant .la file in a fully libtool-enabled configuration such as ours. According to an observation in the discussion back in 2007[1][2][3] that has led to the current arrangement it is to prevent libtool from picking up the wrong version of libbfd. It does not appear to be needed though, not at least with our current libtool incarnation, as directly referring `libbfd.la' does exactly what it should, as previously suggested[4], and with no link-time reference to the installation directory other than to set RPATH. Uninstalled version of libopcodes has libbfd's build-time location prepended to RPATH too, as also expected. Use a direct reference to `libbfd.la' then, making the load error quoted above go away. Alternatively `-L' and `-l' could be used to the same effect, but it seems an unnecessary complication and just another way to circumvent rather than making use of libtool. References: [1] "compile failure due to undefined symbol", <https://sourceware.org/ml/binutils/2007-08/msg00476.html> [2] same, <https://sourceware.org/ml/binutils/2007-09/msg00000.html> [3] same, <https://sourceware.org/ml/binutils/2007-10/msg00019.html> [4] same, <https://sourceware.org/ml/binutils/2007-10/msg00034.html> opcodes/ * Makefile.am: Remove obsolete comment. * configure.ac: Refer `libbfd.la' to link shared BFD library except for Cygwin. * Makefile.in: Regenerate. * configure: Regenerate.
2021-10-24LoongArch opcodes supportliuzhensong10-0/+1637
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> include/ * opcode/loongarch.h: New. * dis-asm.h: Declare print_loongarch_disassembler_options. opcodes/ * Makefile.am: Add LoongArch. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Declare print_insn_loongarch. * loongarch-coder.c: New. * loongarch-dis.c: New. * loongarch-opc.c: New. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2021-10-11z80/disassembler: call memory_error_func when appropriateAndrew Burgess1-0/+2
If a call to the read_memory_func fails then we should call the memory_error_func to notify the user of the disassembler of the address that was a problem. Without this GDB will report all memory errors as being at address 0x0. opcodes/ChangeLog: * z80-dis.c (fetch_data): Call memory_error_func if the read_memory_func call fails.
2021-10-11s12z/disassembler: call memory_error_func when appropriateAndrew Burgess1-0/+3
If a call to the read_memory_func fails then we should call the memory_error_func to notify the user of the disassembler of the address that was a problem. Without this GDB will report all memory errors as being at address 0x0. opcodes/ChangeLog: * s12z-disc.c (abstract_read_memory): Call memory_error_func if the read_memory_func call fails.
2021-10-07RISC-V: Support aliases for Zbs instructionsPhilipp Tomsich1-0/+4
Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to yencode the respective immediate insn b{set,clr,inv,ext}i when the second source operand is an immediate. 2021-01-11 Philipp Tomsich <philipp.tomsich@vrull.eu> gas/ * testsuite/gas/riscv/b-ext.d: Add tests. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext-64.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Add aliases for Zbs. Suggested-by: Jan Beulich <jbeulich@suse.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2021-10-07RISC-V: Add support for Zbs instructionsPhilipp Tomsich1-0/+9
This change adds the Zbs instructions from the Zbs 1.0.0 specification. See https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0 for the frozen specification. 2021-01-09 Philipp Tomsich <philipp.tomsich@vrull.eu> bfd/ * elfxx-riscv.c (riscv_supported_std_z_ext): Added zbs. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZBS. * testsuite/gas/riscv/b-ext.d: Test Zbs instructions. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext-64.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for Zbs. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZBS. opcodes/ * riscv-opc.c (riscv_supported_std_z_ext): Add zbs. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2021-10-07RISC-V: Split Zb[abc] into commented sectionsPhilipp Tomsich1-0/+6
The Zb[abc] opcodes are bundled just below the Privileged opcodes in riscv_opcodes, possibly giving the appearance that they are part of the Privileged spec for an uninitiated reader. This separates them out and adds comments above each section to clearly identify them as Zba, Zbb or Zbc opcodes. 2021-10-04 Philipp Tomsich <philipp.tomsich@vrull.eu> opcodes/ * riscv-opc.c: Split of Zb[abc] instructions and add comments. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2021-09-28x86: Print {bad} on invalid broadcast in OP_E_memoryCui,Lili1-74/+81
Don't print broadcast for scalar_mode, and print {bad} for invalid broadcast. gas/ PR binutils/28381 * testsuite/gas/i386/bad-bcast.s: Add a new testcase. * testsuite/gas/i386/bad-bcast.d: Likewise. * testsuite/gas/i386/bad-bcast-intel.d: New. opcodes/ PR binutils/28381 * i386-dis.c (static struct): Add no_broadcast. (OP_E_memory): Mark invalid broadcast with no_broadcast=1 and Print "{bad}"for it. (intel_operand_size): mark invalid broadcast with no_broadcast=1. (OP_XMM): Mark scalar_mode with no_broadcast=1.
2021-09-27configure: regenerate in all projects that use libtool.m4Nick Alcock2-45/+50
(including sim/, which has no changelog.) bfd/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. binutils/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. gas/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. gprof/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. ld/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. libctf/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. * Makefile.in: Regenerate. opcodes/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. zlib/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate.
2021-09-25PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5Peter Bergner2-4/+9
SPR 896 and the mfppr mfppr32, mtppr and mtppr32 extended mnemonics were added in ISA 2.03, so enable them on POWER5 and later. opcodes/ * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable on POWER5 and later. gas/ * testsuite/gas/ppc/power5.s: New test. * testsuite/gas/ppc/power5.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. * testsuite/gas/ppc/power7.s: Remove tests for mfppr, mfppr32, mtppr and mtppr32. * testsuite/gas/ppc/power7.d: Likewise.
2021-09-20riscv: print .2byte or .4byte before an unknown instruction encodingAndrew Burgess2-1/+29
When the RISC-V disassembler encounters an unknown instruction, it currently just prints the value of the bytes, like this: Dump of assembler code for function custom_insn: 0x00010132 <+0>: addi sp,sp,-16 0x00010134 <+2>: sw s0,12(sp) 0x00010136 <+4>: addi s0,sp,16 0x00010138 <+6>: 0x52018b 0x0001013c <+10>: 0x9c45 My proposal, in this patch, is to change the behaviour to this: Dump of assembler code for function custom_insn: 0x00010132 <+0>: addi sp,sp,-16 0x00010134 <+2>: sw s0,12(sp) 0x00010136 <+4>: addi s0,sp,16 0x00010138 <+6>: .4byte 0x52018b 0x0001013c <+10>: .2byte 0x9c45 Adding the .4byte and .2byte opcodes. The benefit that I see here is that in the patched version of the tools, the disassembler output can be fed back into the assembler and it should assemble to the same binary format. Before the patch, the disassembler output is invalid assembly. I've started a RISC-V specific test file under binutils so that I can add a test for this change. binutils/ChangeLog: * testsuite/binutils-all/riscv/riscv.exp: New file. * testsuite/binutils-all/riscv/unknown.d: New file. * testsuite/binutils-all/riscv/unknown.s: New file. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode before an unknown instruction, '%d' is replaced with the instruction length.
2021-09-13[gdb/tdep] Reset force_thumb in parse_arm_disassembler_optionsTom de Vries1-0/+1
With a gdb build with --enable-targets=all, we have 2 arch-specific failures in selftest print_one_insn: ... $ gdb -q -batch a.out -ex "maint selftest print_one_insn" 2>&1 \ | grep "Self test failed: arch " Self test failed: arch armv8.1-m.main: self-test failed at \ disasm-selftests.c:165 Self test failed: arch arm_any: self-test failed at disasm-selftests.c:165 $ ... During the first failed test, force_thumb is set to true, and remains so until and during the second test, which causes the second failure. Fix this by resetting force_thumb to false in parse_arm_disassembler_options, such that we get just one failure: ... $ gdb -q -batch a.out -ex "maint selftest print_one_insn" 2>&1 \ | grep "Self test failed: arch " Self test failed: arch armv8.1-m.main: self-test failed at \ disasm-selftests.c:165 $ ... Tested on x86_64-linux.
2021-09-08RISC-V: Pretty print values formed with lui and addiw.Jim Wilson1-5/+18
The disassembler has support to pretty print values created by an lui/addi pair, but there is no support for addiw. There is also no support for c.addi and c.addiw. This patch extends the pretty printing support to handle these 3 instructions in addition to addi. Existing testcases serve as tests for the new feature. opcodes/ * riscv-dis.c (maybe_print_address): New arg wide. Sign extend when wide is true. (print_insn_args): Fix calls to maybe_print_address. Add checks for c.addi, c.addiw, and addiw, and call maybe_print_address for them. gas/ * testsuite/gas/riscv/insn.d: Update for disassembler change. * testsuite/gas/li32.d, testsuite/gas/li64.d: Likwise. * testsuite/gas/lla64.d: Likewise.
2021-09-06Add a sanity check to the init_nfp6000_mecsr_sec() function in the NFP ↵Yinjun Zhang1-2/+5
disassembler.
2021-09-03pj: asan: out of bounds, ubsan: left shift of negativeAlan Modra1-3/+4
* pj-dis.c: Include libiberty.h. (print_insn_pj): Don't index op->arg past array bound. Don't left shift negative int.
2021-09-02Add support for the haiku operating system. These are the os support ↵Alexander von Gluck IV1-1/+1
patches we have been grooming and maintaining for quite a few years over on git.haiku-os.org. All of these architectures are working and most have been stable for quite some time.
2021-09-02Fix the V850 assembler's generation of relocations for the st.b instruction.Nick Clifton2-1/+7
PR 28292 gas * config/tc-v850.c (handle_lo16): Also accept BFD_RELOC_V850_LO16_SPLIT_OFFSET. * testsuite/gas/v850/split-lo16.s: Add extra line. * testsuite/gas/v850/split-lo16.d: Update expected disassembly. opcodes * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place of BFD_RELOC_16.
2021-09-01nfp: add validity check of island and meYinjun Zhang1-1/+10
AddressSanitizer detects heap-buffer-overflow when running "objdump -D" for nfp .nffw files. PR 27854 * nfp-dis.c (_NFP_ISLAND_MAX, _NFP_ME_MAX): Define. (nfp_priv_data): ..and use here. (_print_instrs): Sanity check island and menum. Signed-off-by: Yinjun Zhang <yinjun.zhang@corigine.com> Signed-off-by: Simon Horman <simon.horman@corigine.com>
2021-08-30RISC-V: PR28291, Fix the gdb fails that PR27916 caused.Nelson Chu1-2/+2
* According to PR28291, we get the following unexpected gdb behavior, (gdb) disassemble 0x0,+4 Dump of assembler code from 0x0 to 0x4: 0x0000000000000000: 0x0000000000000001: 0x0000000000000002: 0x0000000000000003: End of assembler dump. * This patch should fix it to the right behavior, (gdb) disassemble 0x0,+4 Dump of assembler code from 0x0 to 0x4: 0x0000000000000000: Cannot access memory at address 0x0 opcodes/ pr 28291 * riscv-dis.c (print_insn_riscv): Return STATUS if it is not zero.
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu1-12/+233
Similar to ARM/AARCH64, we add mapping symbols in the symbol table, to mark the start addresses of data and instructions. The $d means data, and the $x means instruction. Then the disassembler uses these symbols to decide whether we should dump data or instruction. Consider the mapping-04 test case, $ cat tmp.s .text .option norelax .option norvc .fill 2, 4, 0x1001 .byte 1 .word 0 .balign 8 add a0, a0, a0 .fill 5, 2, 0x2002 add a1, a1, a1 .data .word 0x1 # No need to add mapping symbols. .word 0x2 $ riscv64-unknown-elf-as tmp.s -o tmp.o $ riscv64-unknown-elf-objdump -d tmp.o Disassembly of section .text: 0000000000000000 <.text>: 0: 00001001 .word 0x00001001 # Marked $d, .fill directive. 4: 00001001 .word 0x00001001 8: 00000001 .word 0x00000001 # .byte + part of .word. c: 00 .byte 0x00 # remaining .word. d: 00 .byte 0x00 # Marked $d, odd byte of alignment. e: 0001 nop # Marked $x, nops for alignment. 10: 00a50533 add a0,a0,a0 14: 20022002 .word 0x20022002 # Marked $d, .fill directive. 18: 20022002 .word 0x20022002 1c: 2002 .short 0x2002 1e: 00b585b3 add a1,a1,a1 # Marked $x. 22: 0001 nop # Section tail alignment. 24: 00000013 nop * Use $d and $x to mark the distribution of data and instructions. Alignments of code are recognized as instructions, since we usually fill nops for them. * If the alignment have odd bytes, then we cannot just fill the nops into the spaces. We always fill an odd byte 0x00 at the start of the spaces. Therefore, add a $d mapping symbol for the odd byte, to tell disassembler that it isn't an instruction. The behavior is same as Arm and Aarch64. The elf/linux toolchain regressions all passed. Besides, I also disable the mapping symbols internally, but use the new objudmp, the regressions passed, too. Therefore, the new objudmp should dump the objects corretly, even if they don't have any mapping symbols. bfd/ pr 27916 * cpu-riscv.c (riscv_elf_is_mapping_symbols): Define mapping symbols. * cpu-riscv.h: extern riscv_elf_is_mapping_symbols. * elfnn-riscv.c (riscv_maybe_function_sym): Do not choose mapping symbols as a function name. (riscv_elf_is_target_special_symbol): Add mapping symbols. binutils/ pr 27916 * testsuite/binutils-all/readelf.s: Updated. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/readelf.s-64-unused: Likewise. * testsuite/binutils-all/readelf.ss: Likewise. * testsuite/binutils-all/readelf.ss-64: Likewise. * testsuite/binutils-all/readelf.ss-64-unused: Likewise. gas/ pr 27916 * config/tc-riscv.c (make_mapping_symbol): Create a new mapping symbol. (riscv_mapping_state): Decide whether to create mapping symbol for frag_now. Only add the mapping symbols to text sections. (riscv_add_odd_padding_symbol): Add the mapping symbols for the riscv_handle_align, which have odd bytes spaces. (riscv_check_mapping_symbols): Remove any excess mapping symbols. (md_assemble): Marked as MAP_INSN. (riscv_frag_align_code): Marked as MAP_INSN. (riscv_init_frag): Add mapping symbols for frag, it usually called by frag_var. Marked as MAP_DATA for rs_align and rs_fill, and marked as MAP_INSN for rs_align_code. (s_riscv_insn): Marked as MAP_INSN. (riscv_adjust_symtab): Call riscv_check_mapping_symbols. * config/tc-riscv.h (md_cons_align): Defined to riscv_mapping_state with MAP_DATA. (TC_SEGMENT_INFO_TYPE): Record mapping state for each segment. (TC_FRAG_TYPE): Record the first and last mapping symbols for the fragments. The first mapping symbol must be placed at the start of the fragment. (TC_FRAG_INIT): Defined to riscv_init_frag. * testsuite/gas/riscv/mapping-01.s: New testcase. * testsuite/gas/riscv/mapping-01a.d: Likewise. * testsuite/gas/riscv/mapping-01b.d: Likewise. * testsuite/gas/riscv/mapping-02.s: Likewise. * testsuite/gas/riscv/mapping-02a.d: Likewise. * testsuite/gas/riscv/mapping-02b.d: Likewise. * testsuite/gas/riscv/mapping-03.s: Likewise. * testsuite/gas/riscv/mapping-03a.d: Likewise. * testsuite/gas/riscv/mapping-03b.d: Likewise. * testsuite/gas/riscv/mapping-04.s: Likewise. * testsuite/gas/riscv/mapping-04a.d: Likewise. * testsuite/gas/riscv/mapping-04b.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04a.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04b.d: Likewise. * testsuite/gas/riscv/no-relax-align.d: Updated. * testsuite/gas/riscv/no-relax-align-2.d: Likewise. include/ pr 27916 * opcode/riscv.h (enum riscv_seg_mstate): Added. opcodes/ pr 27916 * riscv-dis.c (last_map_symbol, last_stop_offset, last_map_state): Added to dump sections with mapping symbols. (riscv_get_map_state): Get the mapping state from the symbol. (riscv_search_mapping_symbol): Check the sorted symbol table, and then find the suitable mapping symbol. (riscv_data_length): Decide which data size we should print. (riscv_disassemble_data): Dump the data contents. (print_insn_riscv): Handle the mapping symbols. (riscv_symbol_is_valid): Marked mapping symbols as invalid.
2021-08-24FT32: Remove recursion in ft32_opcodeJames Bowman (FTDI-UK)1-114/+115
The function ft32_opcode used recursion. This could cause a stack overflow. Replaced with a pair of non-recursive functions. PR 28169 * ft32-dis.c: Formatting. (ft32_opcode1): Split out from.. (ft32_opcode): ..here.
2021-08-19x86: Put back 3 aborts in OP_E_memoryH.J. Lu1-3/+3
Put back 3 aborts where invalid lengths should have been filtered out. gas/ PR binutils/28247 * testsuite/gas/i386/bad-bcast.s: Add a comment. opcodes/ PR binutils/28247 * * i386-dis.c (OP_E_memory): Put back 3 aborts.
2021-08-19x86: Avoid abort on invalid broadcastH.J. Lu1-4/+4
Print "{bad}" on invalid broadcast instead of abort. gas/ PR binutils/28247 * testsuite/gas/i386/bad-bcast.d: New file. * testsuite/gas/i386/bad-bcast.s: Likewise. * testsuite/gas/i386/i386.exp: Run bad-bcast. opcodes/ PR binutils/28247 * i386-dis.c (OP_E_memory): Print "{bad}" on invalid broadcast instead of abort.
2021-08-17opcodes: Fix the auxiliary register numbers for ARC HSShahab Vahedi2-2/+6
The numbers for the auxiliary registers "tlbindex" and "tlbcommand" of ARCv2HS are incorrect. This patch makes the following changes to correct that error. ,------------.-----------------.---------------. | aux. reg. | old (incorrect) | new (correct) | |------------+-----------------+---------------| | tlbindex | 0x463 | 0x464 | | tlbcommand | 0x464 | 0x465 | `------------^-----------------^---------------' opcodes/ 2021-08-17 Shahab Vahedi <shahab@synopsys.com> * arc-regs.h (DEF): Fix the register numbers.
2021-08-13PR28168: [CSKY] Fix stack overflow in disassemblerLifang Xia1-4/+4
PR 28168: Stack overflow with a large float. %f is not a goot choice for this. %f should be replaced with %.7g. gas/ * testsuite/gas/csky/pr28168.d: New testcase for PR 28168. * testsuite/gas/csky/pr28168.s: Likewise. * testsuite/gas/csky/v2_float_part2.d: Following the new format. * opcodes/csky-dis.c (csky_output_operand): %.7g replaces %f.
2021-08-11Deprecate a.out support for NetBSD targets.John Ericson1-53/+53
As discussed previously, a.out support is now quite deprecated, and in some cases removed, in both Binutils itself and NetBSD, so this legacy default makes little sense. `netbsdelf*` and `netbsdaout*` still work allowing the user to be explicit about there choice. Additionally, the configure script warns about the change as Nick Clifton requested. One possible concern was the status of NetBSD on NS32K, where only a.out was supported. But per [1] NetBSD has removed support, and if it were to come back, it would be with ELF. The binutils implementation is therefore marked obsolete, per the instructions in the last message. With that patch and this one applied, I have confirmed the following: --target=i686-unknown-netbsd --target=i686-unknown-netbsdelf builds completely --target=i686-unknown-netbsdaout properly fails because target is deprecated. --target=vax-unknown-netbsdaout builds completely except for gas, where the target is deprecated. [1]: https://mail-index.netbsd.org/tech-toolchain/2021/07/19/msg004025.html --- bfd/config.bfd | 43 +++++++++++++-------- bfd/configure.ac | 5 +-- binutils/testsuite/binutils-all/nm.exp | 2 +- binutils/testsuite/lib/binutils-common.exp | 7 +--- config/picflag.m4 | 4 +- gas/configure.tgt | 9 +++-- gas/testsuite/gas/arm/blx-bl-convert.d | 2 +- gas/testsuite/gas/arm/blx-local-thumb.d | 2 +- gas/testsuite/gas/sh/basic.exp | 2 +- gdb/configure.host | 34 +++++++---------- gdb/configure.tgt | 2 +- gdb/testsuite/gdb.asm/asm-source.exp | 6 +-- intl/configure | 2 +- ld/configure.tgt | 44 +++++++++++----------- ld/testsuite/ld-arm/arm-elf.exp | 4 +- ld/testsuite/ld-elf/elf.exp | 2 +- ld/testsuite/ld-elf/shared.exp | 4 +- libiberty/configure | 4 +-
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