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2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy5-923/+976
2016-11-11[AArch64] Increase max_num_aliases in aarch64-genSzabolcs Nagy2-2/+6
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu5-12/+18
2016-11-09Update opcodes/ChangeLogH.J. Lu1-0/+1
2016-11-09X86: Merge AVX512F vmovqH.J. Lu3-81/+17
2016-11-08X86: Remove the THREE_BYTE_0F7A entryH.J. Lu2-295/+9
2016-11-07X86: Properly handle bad FPU opcodeH.J. Lu2-18/+37
2016-11-04arc/nps400: Validate address type operands correctlyAndrew Burgess3-2/+26
2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall4-1/+99
2016-11-03arc: Change max instruction length to 64-bitsAndrew Burgess7-963/+745
2016-11-03arc: Swap highbyte and lowbyte in print_insn_arcGraham Markall2-4/+8
2016-11-03arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall3-4/+21
2016-11-03arc/opcodes/nps400: Fix some instruction masksAndrew Burgess2-3/+7
2016-11-03X86: Reuse opcode 0x80 decoder for opcode 0x82H.J. Lu2-58/+24
2016-11-03X86: Decode opcode 0x82 as opcode 0x80 in 32-bit modeH.J. Lu2-1/+79
2016-11-03X86: Rename REG_82 to REG_83H.J. Lu2-3/+10
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist8-5340/+5517
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist7-10561/+10779
2016-11-01Add support for RISC-V architecture.Nick Clifton6-0/+1147
2016-10-21X86: Remove pcommit instructionH.J. Lu7-5391/+5365
2016-10-20Check invalid mask registersH.J. Lu2-17/+43
2016-10-18Check addr32flag instead of sizeflag for rip/eipH.J. Lu2-2/+8
2016-10-18Remove the remaining SSE5 supportH.J. Lu2-1/+6
2016-10-18AArch64/opcodes: Correct an `index' global shadowing errorMaciej W. Rozycki2-4/+9
2016-10-17Removed pseudo invalid instructions opcodes.Cupertino Miranda2-93/+4
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu2-2/+8
2016-10-11[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudoJiong Wang2-1/+6
2016-10-07[AArch64] PR target/20667, fix disassembler for the "special" optional SYS_Rt...Jiong Wang2-4/+14
2016-10-07bfd_merge_private_bfd_data tidyAlan Modra2-1/+4
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra13-4/+47
2016-10-06-Wimplicit-fallthrough error fixesAlan Modra4-99/+108
2016-10-06Don't use boolean OR in arithmetic expressionsAlan Modra3-2/+7
2016-09-30Don't assign alt twiceH.J. Lu2-1/+5
2016-09-30[AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang2-4/+9
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra2-73/+39
2016-09-26When building target binaries, ensure that the warning flags selected for the...Vlad Zakharov3-6/+56
2016-09-26[ARC] ISA alignment.Claudiu Zissulescu4-35/+67
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford2-8/+14
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford2-3/+8
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford3-20/+72
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford8-116/+9454
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford5-0/+217
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford7-20/+75
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford11-50/+239
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford11-100/+647
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford10-38/+290
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford11-41/+739
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford11-17/+126
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford7-11/+127
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford2-0/+13
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