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2015-09-10S/390: Fix instruction format of crj*, clrj*, and clgrj*.Andreas Krebbel1-3/+3
2015-09-10S/390: Remove F_20 and FE_20. Adjust comments.Andreas Krebbel1-70/+66
2015-09-10S/390: Fix MASK_RIE_R0PI and MASK_RIE_R0PU.Andreas Krebbel1-2/+2
2015-09-09S/390: Remove trailing zeros on 4-bytes opcodes.Andreas Krebbel2-7/+9
2015-09-09S/390: Fix opcode of ppno.Andreas Krebbel1-1/+1
2015-08-25Support for the sparc %pmcdper privileged register.Jose E. Marchesi2-2/+11
2015-08-24Fix the partial disassembly of a broken three byte instruction at the end of ...Jan Stancek2-2/+8
2015-08-21PR binutils/18257: Properly decode x86/Intel mask instructions.Alexander Fomin2-59/+450
2015-08-17Trailing space in opcodes/ generated filesAlan Modra5-845/+835
2015-08-13Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.Andre Vieira2-3/+19
2015-08-12[MIPS] Map 'move' to 'or'.Simon Dardis3-3/+8
2015-08-12Remove trailing spaces in opcodesH.J. Lu137-4012/+4012
2015-08-11Fix the disassembly of the AArch64 SIMD EXT instruction.Nick Clifton2-1/+7
2015-08-10Add SIGRIE instruction for MIPS R6Robert Suchanek2-0/+5
2015-08-07Remove CpuFMA4 support from CPU_ZNVER1_FLAGS.Amit Pawar3-2/+7
2015-07-30Properly disassemble movnti in Intel modeH.J. Lu2-5/+20
2015-07-27Regenerate configure filesH.J. Lu2-2/+6
2015-07-23Fix ubsan signed integer overflowAlan Modra2-3/+8
2015-07-22Fix memory operand size for vcvtt?ps2u?qq instructionsH.J. Lu2-4/+13
2015-07-16Updates the ARM disassembler's output of floating point constants to include ...Alessandro Marzocchi2-2/+40
2015-07-14Sync config/warnings.m4 with GCCH.J. Lu2-0/+16
2015-07-10Add missing changelog entriesAlan Modra1-0/+4
2015-07-03Remove ppc860, ppc750cl, ppc7450 insns from common ppc.Alan Modra3-5/+17
2015-07-01Opcodes and assembler support for Nios II R2Sandra Loosemore3-56/+952
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar7-5301/+5462
2015-06-22PPC sync instruction accepts invalid and incompatible operandsPeter Bergner2-13/+48
2015-06-22Stop "objdump -d" from disassembling past a symbolic address.Nick Clifton7-6/+33
2015-06-19Allow for optional operands with non-zero default values.Peter Bergner3-26/+34
2015-06-16[AArch64] Support id_mmfr4 system registerMatthew Wahab2-0/+5
2015-06-16Fixes a compile time warnng about left shifting a negative value.Szabolcs Nagy2-1/+5
2015-06-12Remove unused MTMSRD_L macro and re-add accidentally deleted comment.Peter Bergner2-2/+7
2015-06-04Add hwsync extended mnemonic.Peter Bergner1-0/+1
2015-06-04Fixes the check for emulated MSP430 instrucrtions that take no operands.Nick Clifton2-1/+6
2015-06-02[ARM] Support for ARMv8.1 Adv.SIMD extensionMatthew Wahab1-0/+19
2015-06-02[ARM] Add support for ARMv8.1 PAN extensionMatthew Wahab2-0/+10
2015-06-02[ARM] Rework CPU feature selection in the disassemblerMatthew Wahab2-29/+31
2015-06-02[AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab5-1249/+1359
2015-06-02[AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab5-401/+478
2015-06-01[AArch64][libopcode] Add support for PAN architecture extensionMatthew Wahab2-0/+46
2015-06-01x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s}Jan Beulich2-6/+10
2015-06-01x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand orderJan Beulich2-0/+12
2015-06-01x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich3-0/+143
2015-05-18Remove Disp32 from AMD64 direct call/jmpH.J. Lu3-4/+9
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu7-5296/+5387
2015-05-14Fix some PPC assembler errors.Peter Bergner2-3/+15
2015-05-13Add missing ChangeLog entries for PR binutis/18386H.J. Lu1-0/+13
2015-05-11Remove Disp16|Disp32 from 64-bit direct branchesH.J. Lu3-5/+26
2015-05-11Add Intel MCU support to opcodesH.J. Lu8-5817/+5853
2015-05-09Ignore 0x66 prefix for call/jmp/jcc in 64-bit modeH.J. Lu1-10/+40
2015-04-30Make RL78 disassembler and simulator respect ISA for mul/divDJ Delorie5-447/+509