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path: root/opcodes/riscv-opc.c
AgeCommit message (Expand)AuthorFilesLines
2021-04-16RISC-V: compress "addi d,CV,z" to "c.mv d,CV"Lifang Xia1-0/+1
2021-03-16RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen1-4/+49
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu1-12/+22
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu1-87/+0
2021-02-04RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu1-53/+4
2021-01-15RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu1-710/+707
2021-01-15RISC-V: Comments tidy and improvement.Nelson Chu1-17/+16
2021-01-07RISC-V: Add pause hint instruction.Philipp Tomsich1-0/+3
2021-01-07RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf1-4/+53
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-12-10RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu1-0/+5
2020-12-10RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu1-20/+20
2020-12-01RISC-V: Remove the unimplemented extensions.Nelson Chu1-11/+0
2020-12-01RISC-V: Add zifencei and prefixed h class extensions.Nelson Chu1-0/+3
2020-06-22RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu1-50/+0
2020-06-12RISC-V: Drop the privileged spec v1.9 support.Nelson Chu1-1/+0
2020-06-03RISC-V: Fix the error when building RISC-V linux native gdbserver.Nelson Chu1-8/+8
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu1-0/+144
2020-02-19RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson1-0/+2
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-11-12RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson1-60/+60
2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson1-658/+658
2019-07-30RISC-V: Fix minor issues with FP csr instructions.Jim Wilson1-16/+16
2019-07-05Kito's 5-part patch set to improve .insn support.Jim Wilson1-4/+26
2019-02-08RISC-V: Compress 3-operand beq/bne against x0.Jim Wilson1-0/+2
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-12-07RISC-V: Fix 4-arg add parsing.Jim Wilson1-1/+1
2018-11-29RISC-V: Add missing c.unimp instruction.Jim Wilson1-1/+2
2018-11-27RISC-V: Add .insn CA support.Jim Wilson1-2/+7
2018-10-02RISC-V: Add fence.tso instructionPalmer Dabbelt1-0/+1
2018-09-17RISC-V: bge[u] should get higher priority than ble[u].Jim Wilson1-2/+2
2018-08-31RISC-V: Correct the requirement of compressed floating point instructionsJim Wilson1-16/+16
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson1-629/+629
2018-07-30RISC-V: Set insn info fields correctly when disassembling.Jim Wilson1-178/+178
2018-06-20RISC-V: Accept constant operands in la and llaSebastian Huber1-2/+2
2018-05-08RISC-V: Add missing hint instructions from RV128I.Jim Wilson1-9/+45
2018-03-14RISC-V: Add .insn support.Jim Wilson1-0/+74
2018-01-17RISC-V: Fix bug in prior addi/c.nop patch.Jim Wilson1-1/+1
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson1-0/+8
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson1-13/+35
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson1-0/+4
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman1-7/+23
2017-09-27Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...Nick Clifton1-0/+5
2017-08-22RISC-V: Mark "c.nop" as an aliasPalmer Dabbelt1-1/+1
2017-06-23RISC-V: Fix SLTI disassemblyAndrew Waterman1-2/+2
2017-05-02RISC-V: Change CALL macro to use ra as the temporary address registerMichael Clark1-1/+1
2017-03-15RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng1-3/+3
2017-03-15RISC-V: Fix assembler for c.addi, rd can be x0Kito Cheng1-1/+1
2017-03-14RISC-V: Fix [dis]assembly of srai/srliAndrew Waterman1-4/+4