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path: root/opcodes/m10300-opc.c
AgeCommit message (Expand)AuthorFilesLines
1998-10-12 * m10300-opc.c: DSP instrutions which only write to one generalJeff Law1-96/+96
1998-10-12 * m10300-opc.c (lsr_add): Fix typo for "lsr_add imm,reg,reg,reg" case.Jeff Law1-1/+1
1998-10-08 * m10300-opc.c (asr, lsr, asl): Fix am33 single bit shift opcode.Jeff Law1-19/+19
1998-08-12 * m10300-opc.c: First cut at UDF instructions.Jeff Law1-2/+131
1998-07-28 * m10300-opc.c: Add entries for "no_match_operands" field inJeff Law1-1228/+884
1998-07-23 * m10300-opc.c: Add DSP autoincrement memory loads/stores.Jeff Law1-0/+44
1998-07-23 * m10300-opc.c: Add autoincrement memory loads/stores.Jeff Law1-3/+288
1998-07-17 * m10300-opc.c (mn10300_opcodes): Fix opcode for 4 operand "mul" andJeff Law1-12/+12
1998-06-30 * m10300-opc.c: Reorder "movbu" and "movhu" instructions too.Jeff Law1-34/+38
1998-06-29 * m10300-opc.c: Reorder more instructions so that we do notJeff Law1-33/+46
1998-06-26 * m10300-dis.c: Only recognize instructions from the currentlyJeff Law1-697/+710
1998-06-24 * mn10300-opc.c (mn10300_opcodes): Fix typo in IMM24 versions of theJeff Law1-3/+3
1998-06-24 * mn10300-opc.c (IMM32_HIGH8_MEM): New operand type.Jeff Law1-95/+159
1998-06-23 * m10300-opc.c: Support one operand "asr", "lsr" and "asl"Jeff Law1-0/+11
1998-06-22 * m10300-opc.c: Support 4 byte DSP instructions.Jeff Law1-45/+540
1998-06-19 * m10300-opc.c: Support for 3 byte and 4 byte extended instructionsJeff Law1-10/+272
1998-06-17start-sanitize-am33Jeff Law1-0/+589
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