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path: root/opcodes/i386-gen.c
AgeCommit message (Expand)AuthorFilesLines
2022-12-02x86: drop most OPERAND_TYPE_* (and rework the rest)Jan Beulich1-103/+0
2022-12-01x86: drop No_ldSufJan Beulich1-1/+0
2022-11-30x86: drop FloatRJan Beulich1-1/+0
2022-11-15Add AMD znver4 processor supportTejas Joshi1-0/+5
2022-11-14x86: fold special-operand insn attributes into a single enumJan Beulich1-9/+1
2022-11-08Support Intel RAO-INTKong Lingling1-0/+5
2022-11-04Support Intel AVX-NE-CONVERTkonglin11-1/+6
2022-11-02Support Intel MSRLISTHu, Lin11-0/+5
2022-11-02Support Intel WRMSRNSHu, Lin11-0/+5
2022-11-02Support Intel CMPccXADDHaochen Jiang1-0/+5
2022-11-02Support Intel AVX-VNNI-INT8Cui,Lili1-1/+6
2022-11-02Support Intel AVX-IFMAHongyu Wang1-1/+6
2022-10-31x86: minor improvements to optimize_imm() (part III)Jan Beulich1-2/+0
2022-10-31Support Intel PREFETCHICui, Lili1-0/+3
2022-10-21Support Intel AMX-FP16Cui,Lili1-1/+4
2022-10-20x86: re-work AVX-VNNI supportJan Beulich1-1/+0
2022-10-18x86: Disable AVX-VNNI when disabling AVX2H.J. Lu1-1/+1
2022-10-18x86: correct CPU_AMX_{BF16,INT8}_FLAGSJan Beulich1-2/+2
2022-09-30x86/Intel: restrict suffix derivationJan Beulich1-2/+0
2022-08-16x86: template-ize certain vector conversion insnsJan Beulich1-4/+26
2022-08-16x86: template-ize packed/scalar vector floating point insnsJan Beulich1-19/+24
2022-08-16revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl"Jan Beulich1-8/+27
2022-07-18x86: re-order insn template fieldsJan Beulich1-2/+2
2022-07-04x86: fold Disp32S and Disp32Jan Beulich1-14/+8
2022-07-04x86: restore masking of displacement kindsJan Beulich1-6/+6
2022-03-17x86: never set i386_cpu_flags' "unused" fieldJan Beulich1-4/+5
2022-03-17x86: unify CPU flag on/off processingJan Beulich1-21/+10
2022-03-17x86: drop L1OM/K1OM support from gasJan Beulich1-7/+1
2022-03-17x86: assorted IAMCU CPU checking fixesJan Beulich1-1/+1
2022-01-06x86: drop NoAVX insn attributeJan Beulich1-1/+0
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-2/+2
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili1-2/+8
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich1-1/+1
2021-03-29x86: undo Prefix_0X<nn> use in opcode tableJan Beulich1-6/+10
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich1-5/+35
2021-03-24x86: derive opcode length from opcode valueJan Beulich1-17/+15
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich1-53/+41
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich1-2/+1
2021-03-23x86: re-order two fields of struct insn_templateJan Beulich1-4/+4
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich1-0/+1
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich1-4/+1
2021-03-03x86: infer operand count of templatesJan Beulich1-34/+21
2021-02-16x86: have preprocessor expand macrosJan Beulich1-11/+0
2021-01-26Segmentation fault i386-genAlan Modra1-0/+2
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-2/+2
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+11
2020-10-16Enhancement for avx-vnni patchCui,Lili1-2/+2
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-0/+6
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-0/+7
2020-10-14x86: Support Intel UINTRLili Cui1-0/+5
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