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2024-05-22Support APX zero-upperCui, Lili1-0/+1
This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc. Since the spec only recommends one form of setzu, I won't be adding set<cc>reg32/reg64 support in this patch. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Handle ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64-apx-zu-intel.d: New test. * testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-zu.d: Ditto. * testsuite/gas/i386/x86-64-apx-zu.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~ PREFIX_EVEX_MAP4_4F. * i386-dis-evex.h: Ditto. * i386-dis.c (struct dis386): Add new micro 'ZU'. (putop): Handle %ZU. * i386-gen.c: Added ZU. * i386-opc.h: Ditto. * i386-opc.tbl: Added new templates to support ZU.
2024-05-03x86: zap value-less Disp8MemShift from non-EVEX templatesJan Beulich1-7/+19
In order to allow to continue to use templatized SSE2AVX templates when enhancing those to also cover eGPR usage, Disp8MemShift wants using to deviate from what general template attributes supply. That requires using Disp8MemShift in a way also affecting non-EVEX templates, yet having this attribute set would so far implicitly mean EVEX encoding. Recognize the case and instead zap the attribute if no other attribute indicates EVEX encoding. No change in generated tables.
2024-03-28x86: templatize INC/DECJan Beulich1-6/+18
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Start with the simplest case, accompanied by a necessary adjustment to i386-gen (such that template uses can also be at the start of a line). While there also drop a bogus (meaningless / unreachable) "break" as well as a unused variable (which I'm surprised compilers didn't warn about).
2024-01-15opcodes: gas: x86: define and use Rex2 as attribute not constraintIndu Bhagat1-0/+1
Rex2 is currently an operand constraint. For the upcoming SCFI implementation in GAS, we need to identify operations which implicitly update the stack pointer. An operand constraint enumerator for implicit stack op seems more appropriate than an attribute. However, two opcodes currently necessitate both Rex2 and an implicit stack op marker; this prompts revisiting the current representations a bit. Make Rex2 a standalone attribute, so that later a new operand constraint may be added for IMPLICIT_STACK_OP. ChangeLog: * gas/config/tc-i386.c (is_apx_rex2_encoding): Update the check. * opcodes/i386-gen.c: Add a new BITFIELD for Rex2. * opcodes/i386-opc.h (REX2_REQUIRED): Remove. * opcodes/i386-opc.tbl: Remove Rex2 operand constraint. * opcodes/i386-tbl.h: Regenerated.
2024-01-05Add AMD znver5 processor supportTejas Joshi1-0/+2
gas/ * config/tc-i386.c (cpu_arch): Add znver5 ARCH. * doc/c-i386.texi: Add znver5. * testsuite/gas/i386/arch-15.d: New. * testsuite/gas/i386/arch-15.s: Likewise. * testsuite/gas/i386/arch-15-znver5.d: Likewise. * testsuite/gas/i386/i386.exp: Add new znver5 test cases. * testsuite/gas/i386/x86-64.exp: Likewise. * testsuite/gas/i386/x86-64-arch-5.d: Likewise. * testsuite/gas/i386/x86-64-arch-5.s: Likewise. * testsuite/gas/i386/x86-64-arch-5-znver5.d: Likewise. opcodes/ * i386-gen.c (isa_dependencies): Add ZNVER5 dependencies. * i386-init.h: Re-generated.
2024-01-05x86: corrections to CPU attribute/flags splittingJan Beulich1-1/+10
There are a number of issues with 734dfd1cc966 ("x86: pack CPU flags in opcode table"): - the condition when two array slots need writing wasn't correct (with enough new Cpu* added an out of bounds array access would validly have been complained about by the compiler), - table generation didn't take into account CpuAttrUnused and CpuUnused being independent, and hence there not always (not) being an "unused" bitfield member in both structures, - cpu_flags_from_attr() wasn't ready for use on big-endian hosts, - there were two style violations.
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-2/+2
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili1-0/+2
This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-2/+48
APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. We added the NoEgpr flag in i386-gen.c for instructions that do not support EGPR. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (enum i386_error): Add unsupported_EGPR_for_addressing and invalid_pseudo_prefix. (struct _i386_insn): Add rex2 and rex2_encoding for gpr32. (cpu_arch): Add apx_f. (is_cpu): Ditto. (register_number): Handle RegRex2 for gpr32. (is_apx_rex2_encoding): New func. Test rex2 prefix encoding. (build_rex2_prefix): New func. Build legacy insn in opcode 0/1 use gpr32 with rex2 prefix. (establish_rex): Handle rex2 and rex2_encoding. (optimize_encoding): Handel add r16-r31 for registers. (md_assemble): Handle apx encoding. (parse_insn): Handle Prefix_REX2. (check_EgprOperands): New func. Check if Egprs operands are valid for the instruction (match_template): Handle Egpr operands check. (set_rex_rex2): New func. set i.rex and i.rex2. (build_modrm_byte): Ditto. (output_insn): Handle rex2 2-byte prefix output. (check_register): Handle check egpr illegal without target apx, 64-bit mode and with rex_prefix. * doc/c-i386.texi: Document .apx. * testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid in 64-bit mode. * testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/rex-bad: Adjust rex testcase. * testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.s: Ditto. * testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test. * testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64.exp: Run APX tests. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test. * testsuite/gas/i386/x86-64-apx-rex2.d: New test. * testsuite/gas/i386/x86-64-apx-rex2.s: New test. include/ChangeLog: * opcode/i386.h (REX2_OPCODE): New. (REX2_M): Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add erex for gpr32. Add last_erex_prefix for rex2 prefix. (REX2_M): Extend for gpr32. (PREFIX_REX2): Ditto. (PREFIX_REX2_ILLEGAL): Ditto. (ckprefix): Ditto. (prefix_name): Ditto. (print_insn): Ditto. (print_register): Ditto. (OP_E_memory): Ditto. (OP_REG): Ditto. (OP_EX): Ditto. * i386-gen.c (rex2_disallowed): Some instructions are not allowed rex2 prefix. (process_i386_opcode_modifier): Set NoEgpr for VEX and some special instructions. (output_i386_opcode): Handle if_entry_needs_special_handle. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h (enum i386_cpu): Add CpuAPX_F. (NoEgpr): New. (Prefix_NoOptimize): Ditto. (Prefix_REX2): Ditto. (RegRex2): Ditto. * i386-opc.tbl: Add rex2 prefix. * i386-reg.tbl: Add egprs (r16-r31). * i386-tbl.h: Regenerated.
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang1-1/+0
Since AVX10.1/256 will also allow 64 bit mask register, we will remove the restriction for size of the mask register in AVX10. gas/ChangeLog: * config/tc-i386.c (VSZ128, VSZ256, VSZ512): New. (VEX_check_encoding): Remove opcode_modifier check for vsz. * testsuite/gas/i386/avx10-vsz.l: Remove testcases for mask registers since they are not needed. * testsuite/gas/i386/avx10-vsz.s: Ditto. opcodes/ChangeLog: * i386-gen.c: Remove Vsz. * i386-opc.h: Ditto. * i386-opc.tbl: Remove kvsz. * i386-tbl.h: Regenerated.
2023-12-15x86: fold assembly dialect attributesJan Beulich1-3/+1
Now that ATTSyntax and ATTMnemonic aren't use in combination anymore, fold them and IntelSyntax into a single, enum-like attribute. Note that this shrinks i386_opcode_modifier back to 2 32-bit words (albeit that's not for long, seeing in-flight additions for APX).
2023-11-24x86: shrink opcode sets tableJan Beulich1-4/+7
Have i386-gen produce merely the offsets into i386_optab[]. Besides allowing to shrink the table even on 32-bit builds, this results in removing a level of indirection from the frequently accessed current_templates, in return for adding a level of indirection when looking up mnemonics (commonly happening just once per insn). Plus for PIE builds of gas it also reduces the number of relocations by about two thousand. Finally a somewhat ugly static variable can also be eliminated from i386_displacement().
2023-11-09x86: do away with is_evex_encoding()Jan Beulich1-0/+10
As we have grown more uses of it, it becomes increasingly more desirable to replace it by a simpler check. Have i386-gen do at build time what so far was done at runtime: Deal with templates indicating EVEX-encoding by other than the EVex attribute, and set that to "dynamic" in such cases. This then allows simplifying a number of other conditionals as well.
2023-11-09x86: split insn templates' CPU fieldJan Beulich1-23/+51
Right now the opcode table has entries with ISA restrictions of the form FEAT1|FEAT2, the meaning of which depends on context and requires special treatment in tc-i386.c: Sometimes this means "both features requires", whereas originally it was intended to solely mean "all of these features required". Split the field, with the original one regaining its original meaning. The new field now truly means "any of these". The combination of both fields is still and &&-type check, i.e. (all of these) && (any of these). In the opcode table more involved combinations of features then also need expressing this way: "all" entities first, follow by "any" entities enclosed in parentheses, e.g. x64&(AVX|AVX512F). If the "all" part is empty, parentheses may not be added around the "any" part (unless parsing logic was further relaxed). Note that this way AVX512VL no longer needs as much special treatment, and hence templates previously using AVX512F|AVX512VL are switched to just AVX512VL. Note further that this requires FMA handling as resulting from da0784f961d8 ("x86: fold FMA VEX and EVEX templates") to be slightly re-done: FMA now becomes more similar to AVX and AVX2.
2023-11-09x86: Cpu64 handling improvementsJan Beulich1-5/+41
First of all we want to also accumulate its reverse dependencies, such that we can use them in cpu_flags_match(). This is in particular in preparation of APX additions, such that e.g. BMI VEX-encoding templates can become combined VEX/EVEX ones. Once we have the reverse dependencies, we can further leverage them to omit explicit "&x64" from any insn templates dealing with 64-bit-mode- only ISA extensions. Besides helping readability for several insn templates we already have, this will also help with what is going to be added for APX (as all of the new templates would otherwise need to have "&x64"). Note that rather than leaving a meaningless CPU_64_FLAGS (which is unused anyway), its emitting is now also suppressed.
2023-11-09x86: Intel Core processors do not support CMPXCHG16BJan Beulich1-1/+1
This being a 64-bit-only instruction (see also i386-opc.tbl) it cannot possibly be supported by CPUs not supporting 64-bit mode.
2023-10-31Support Intel USER_MSRHu, Lin11-0/+2
This patches aims to support Intel USER_MSR. In addition to the usual support, this patch includes encoding and decoding support for MAP7 and immediate numbers as the last operand (ATT style). gas/ChangeLog: * NEWS: Support Intel USER_MSR. * config/tc-i386.c (smallest_imm_type): Reject imm32 in 64bit mode. (build_vex_prefix): Add VEXMAP7. (md_assemble): Handling the imm32 of USER_MSR. (match_template): Handling the unusual immediate. * doc/c-i386.texi: Document .user_msr. * testsuite/gas/i386/i386.exp: Run USER_MSR tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/user_msr-inval.l: New test. * testsuite/gas/i386/user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. * testsuite/gas/i386/x86-64-user_msr-inval.l: Ditto. * testsuite/gas/i386/x86-64-user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add a new attribute has_skipped_modrm. (Gq): New. (Rq): Ditto. (q_mm_mode): Ditto. (Nq): Change mode from q_mode to q_mm_mode. (VEX_LEN_TABLE): (get_valid_dis386): Add VEX_MAP7 in VEX prefix. and handle the map7_f8 for save space. (OP_Skip_MODRM): Set has_skipped_modrm. (OP_E): Skip codep++ when has skipped modrm byte. (OP_R): Support q_mode and q_mm_mode. (REG_VEX_MAP7_F8_L_0_W_0): New. (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto. (X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto. (VEX_LEN_MAP7_F8): Ditto. (VEX_W_MAP7_F8_L_0): Ditto. (MOD_0F38F8): Ditto. (PREFIX_0F38F8_M_0): Ditto. (PREFIX_0F38F8_M_1_X86_64): Ditto. (X86_64_0F38F8_M_1): Ditto. (PREFIX_0F38F8): Remove. (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. Remove PREFIX_0F38F8. (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0, PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64. (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1. (vex_table): Add VEX_MAP7. (vex_len_table): Add VEX_LEN_MAP7_F8, VEX_W_MAP7_F8_L_0. (mod_table): New entry for USER_MSR and add MOD_0F38F8. * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and CPU_ANY_USER_MSR_FLAGS. Add add VEXMAP7. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (SPACE_VEXMAP7): New. (CPU_USER_MSR_FLAGS): Ditoo. (CPU_ANY_USER_MSR_FLAGS): Ditto. (i386_cpu_flags): Add cpuuser_msr. * i386-opc.tbl: Add USER_MSR instructions. * i386-tbl.h: Regenerated.
2023-09-15x86: fold CpuLM and Cpu64Jan Beulich1-6/+8
Now that CpuLM is used solely in cpu_arch_flags and cpu_arch[] while Cpu64 is solely used in insn templates, they no longer need to be treated different from other "ordinary" flags; the only "unusual" one left if CpuNo64. Fold both, leaving just Cpu64.
2023-09-14x86: support AVX10.1 vector size restrictionsJan Beulich1-0/+1
Recognize "/<number>" suffixes on both -march=+avx10.1 and the corresponding .arch directive, setting an upper bound on the vector size that insns may use. Such a restriction can be reset by setting a new base architecture, by using a suffix-less form, by disabling AVX10, or by enabling any other VEX/EVEX-based vector extension. While for most insns we can suppress their use with too wide operands via registers becoming unavailable (or in Intel syntax memory operand size specifiers not being recognized), mask register insns have to have their minimum required vector size specified in a new attribute. (Of course this new attribute could also be used on other insns.) Note that .insn continues to be permitted to emit EVEX{512,256} (and VEX256 ones) encodings regardless of vector size restrictions in place. Of course these can't be expressed using zmm (or ymm) operands then, but need using the EVEX.512.* forms (broadcast forms may be usable right now, but this may go away so shouldn't be relied upon). This is why no assertions should be added to build_{e,}vex_prefix().
2023-09-14x86: support AVX10.1/512Jan Beulich1-0/+3
Since this is merely a re-branding of certain AVX512* features, there's little code to be added. The main aspect here are new testcases. In order to be able to re-use some of the existing testcases, several of them need their start symbols adjusted. Note that 256- and 128-bit tests want adding here, as these need to work right away. Subsequently they'll gain vector length constraints. Since it was missing and is wanted here, also add an AVX512VL+VPOPCNTDQ test.
2023-09-14x86: make AES/PCMULQDQ respectively prereqs of VAES/VPCMULQDQJan Beulich1-5/+12
These probably should have been put in place already anyway, but they're very much wanted in order to then put AVX10.1 support on top. Note that to avoid reverse dependencies towards SSE (just like we already do for AVX and XOP), add_isa_dependencies() needs some further tweaking. While there also address a related anomaly: Disabling AES but neither AVX nor VAES (similarly for {,V}PCLMULQDQ) would better keep the 128-bit VEX-encoded forms available. Note that for this the VAES insns are moved past the AVX+AES ones, to avoid the property-11 test suddenly failing. The test really is wrong, but let's not also make things inconsistent: Without the movement, YMM use would be correctly recorded for the 128-bit forms simply because the first template already matches, as long as VAES wasn't disabled. Yet it still wouldn't be if only AVX+AES were enabled. Nor would behavior here then be the same as for VPCLMUL* insns.
2023-09-01x86: rename CpuPCLMULJan Beulich1-5/+5
The name we use internally isn't in line with the SDM, and also isn't in line with CpuVPCLMULQDQ. Add the missing suffix, but of course leave alone user facing names.
2023-08-26opcodes i386 and ia64 gen file warningsAlan Modra1-1/+1
i386: warning: format ‘%u’ expects argument of type ‘unsigned int’, but argument 4 has type ‘size_t’ {aka ‘long unsigned int’} [-Wformat=] ia64: warning: ignoring return value of ‘fgets’ * i386-gen.c (process_i386_opcodes): Correct format string. * ia64-gen.c (load_insn_classes, load_depfile): Don't ignore fgets return value.
2023-08-11x86: pack CPU flags in opcode tableJan Beulich1-6/+36
The table constantly growing in two dimensions (number of table entries times number of ISA extension flags) doesn't scale very well. Use a more compact representation: Only identifiers which need to combine with other identifiers retain individual flag bits. All others are combined into an enum, with a new helper added to transform the table entries into the original i386_cpu_flags layout. This way the table in the final binary shrinks by almost a third (the generated source code shrinks by about half), and isn't likely to grow again in that dimension any time soon. While moving the 3DNow! fields, drop the stray inner 'a' from their names.
2023-08-02Revert "2.41 Release sources"Sam James1-0/+13
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-13/+0
2023-07-27Support Intel PBNDKBHu, Lin11-0/+1
gas/ChangeLog: * NEWS: Support Intel PBNDKB. * config/tc-i386.c: Add pbndkb. * doc/c-i386.texi: Document .pbndkb. * testsuite/gas/i386/i386.exp: Add PBNDKB tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/pbndkb-inval.l: New test. * testsuite/gas/i386/pbndkb-inval.s: Ditto. * testsuite/gas/i386/x86-64-pbndkb-intel.d: Ditto. * testsuite/gas/i386/x86-64-pbndkb.d: Ditto. * testsuite/gas/i386/x86-64-pbndkb.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_7): New. (X86_64_0F01_REG_0_MOD_3_RM_7_P_0): Ditto. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_7. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_7_P_0. (rm_table): New entry for pbndkb. * i386-gen.c (cpu_flag): Add PBNDKB. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuPBNDKB): New. (i386_cpu_flags): Add cpupbndkb. * i386-opc.tbl: Add PBNDKB instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel SM4Haochen Jiang1-0/+3
gas/ChangeLog: * NEWS: Support Intel SM4. * config/tc-i386.c: Add sm4. * doc/c-i386.texi: Document .sm4. * testsuite/gas/i386/i386.exp: Run SM4 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sm4-intel.d: Add SM4 tests. * testsuite/gas/i386/sm4.d: Ditto. * testsuite/gas/i386/sm4.s: Ditto. * testsuite/gas/i386/x86-64-sm4-intel.d: Ditto. * testsuite/gas/i386/x86-64-sm4.d: Ditto. * testsuite/gas/i386/x86-64-sm4.s: Ditto. opcodes/ChangeLog: * i386-dis.c (prefix_table): Add SM4 instructions. * i386-gen.c (isa_dependencies): Add SM4. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSM4): New. (i386_cpu_flags): Add cpusm4. * i386-opc.tbl: Add SM4 instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel SM3Haochen Jiang1-0/+3
gas/ChangeLog: * NEWS: Support Intel SM3. * config/tc-i386.c: Add sm3. * doc/c-i386.texi: Document .sm3. * testsuite/gas/i386/i386.exp: Run sm3 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sm3-intel.d: New test. * testsuite/gas/i386/sm3.d: Ditto. * testsuite/gas/i386/sm3.s: Ditto. * testsuite/gas/i386/x86-64-sm3-intel.d: Ditto. * testsuite/gas/i386/x86-64-sm3.d: Ditto. * testsuite/gas/i386/x86-64-sm3.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F38DA_W_0): New. (VEX_LEN_0F38DA_W_0_P_0): Ditto. (VEX_LEN_0F38DA_W_0_P_2): Ditto. (VEX_LEN_0F3ADE_W_0): Ditto. (VEX_W_0F38DA): Ditto. (VEX_W_0F3ADE): Ditto. (prefix_table): Add PREFIX_VEX_0F38DA_W_0. (vex_len_table): Add VEX_LEN_0F38DA_W_0_P_0, VEX_LEN_0F38DA_W_0_P_2, VEX_LEN_0F3ADE_W_0. (vex_w_table): Add VEX_W_0F38DA, VEX_W_0F3ADE. * i386-gen.c (isa_dependencies): Add SM3. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSM3): New. (i386_cpu_flags): Add cpusm3. * i386-opc.tbl: Add SM3 instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel SHA512Haochen Jiang1-0/+3
gas/ChangeLog: * NEWS: Support Intel SHA512. * config/tc-i386.c: Add sha512. * doc/c-i386.texi: Document .sha512. * testsuite/gas/i386/disassem.d: Add SHA512 tests. * testsuite/gas/i386/disassem.s: Ditto. * testsuite/gas/i386/i386.exp: Run SHA512 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sha512-intel.d: New test. * testsuite/gas/i386/sha512-inval.l: Ditto. * testsuite/gas/i386/sha512-inval.s: Ditto. * testsuite/gas/i386/sha512.d: Ditto. * testsuite/gas/i386/sha512.s: Ditto. * testsuite/gas/i386/x86-64-sha512-intel.d: Ditto. * testsuite/gas/i386/x86-64-sha512-inval.l: Ditto. * testsuite/gas/i386/x86-64-sha512-inval.s: Ditto. * testsuite/gas/i386/x86-64-sha512.d: Ditto. * testsuite/gas/i386/x86-64-sha512.s: Ditto. opcodes/ChangeLog: * i386-dis.c (Rxmmq): New. (Rymm): Ditto. (PREFIX_VEX_0F38CB): Ditto. (PREFIX_VEX_0F38CC): Ditto. (PREFIX_VEX_0F38CD): Ditto. (VEX_LEN_0F38CB_P_3_W_0): Ditto. (VEX_LEN_0F38CC_P_3_W_0): Ditto. (VEX_LEN_0F38CD_P_3_W_0): Ditto. (VEX_W_0F38CB_P_3): Ditto. (VEX_W_0F38CC_P_3): Ditto. (VEX_W_0F38CD_P_3): Ditto. (prefix_table): Add PREFIX_VEX_0F38CB, PREFIX_VEX_0F38CC, PREFIX_VEX_0F38CD. (vex_len_table): Add VEX_LEN_0F38CB_P_3_W_0, VEX_LEN_0F38CC_P_3_W_0, VEX_LEN_0F38CD_P_3_W_0. (vex_w_table): Add VEX_W_0F38CB_P_3, VEX_W_0F38CC_P_3, VEX_W_0F38CD_P_3. * i386-gen.c (isa_dependencies): Add SHA512. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSHA512): New. (i386_cpu_flags): Add cpusha512. * i386-opc.tbl: Add SHA512 instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel AVX-VNNI-INT16konglin11-0/+3
gas/ChangeLog: * NEWS: Support Intel AVX-VNNI-INT16. * config/tc-i386.c: Add avx_vnni_int16. * doc/c-i386.texi: Document avx_vnni_int16. * testsuite/gas/i386/i386.exp: Run AVX VNNI INT16 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx-vnni-int16-intel.d: New test. * testsuite/gas/i386/avx-vnni-int16.d: New test. * testsuite/gas/i386/avx-vnni-int16.s: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16-intel.d: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16.d: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16.s: New test. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F38D2_W_0): New. (PREFIX_VEX_0F38D3_W_0): Ditto. (VEX_W_0F38D2_P_0): Ditto. (VEX_W_0F38D2_P_1): Ditto. (VEX_W_0F38D2_P_2): Ditto. (VEX_W_0F38D3_P_0): Ditto. (VEX_W_0F38D3_P_1): Ditto. (VEX_W_0F38D3_P_2): Ditto. (prefix_table): Add PREFIX_VEX_0F38D2_W_0 and PREFIX_VEX_0F38D3_W_0. (vex_table): Add VEX_W_0F38D2 and VEX_W_0F38D3. (vex_w_table): Ditto. * i386-gen.c (isa_dependencies): Add AVX_VNNI_INT16. (cpu_flag): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h: (CpuAVX_VNNI_INT16): New. * i386-opc.tbl: Add Intel AVX_VNNI_INT16 instructions. * i386-tbl.h: Regenerated.
2023-05-23Support Intel FRED LKGSZhang, Jun1-0/+4
gas/ChangeLog: * NEWS: Support Intel FRED LKGS. * config/tc-i386.c: Add fred lkgs * doc/c-i386.texi: Document .fred, .lkgs. * testsuite/gas/i386/i386.exp: Add FRED LKGS tests * testsuite/gas/i386/x86-64-fred-intel.d: Ditto. * testsuite/gas/i386/x86-64-fred.d: Ditto. * testsuite/gas/i386/x86-64-fred.s: Ditto. * testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto. * testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto. * testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto. * testsuite/gas/i386/x86-64-lkgs.d: Ditto. * testsuite/gas/i386/x86-64-lkgs.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New entry for fred, lkgs. * i386-gen.c: Add CPU_FRED CPU_LKGS. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h: Add fred, lkgs. * i386-opc.tbl: Add FRED, LKGS instructions. * i386-tbl.h: Regenerated.
2023-05-23Revert "Support Intel FRED LKGS"liuhongt1-4/+0
This reverts commit e5a497fe38e0ab19e16bdd9e4b4ed5e4d0056478.
2023-05-23Support Intel FRED LKGSZhang, Jun1-0/+4
gas/ChangeLog: * NEWS: Support Intel FRED LKGS. * config/tc-i386.c: Add fred lkgs * doc/c-i386.texi: Document .fred, .lkgs. * testsuite/gas/i386/i386.exp: Add FRED LKGS tests * testsuite/gas/i386/x86-64-fred-intel.d: Ditto. * testsuite/gas/i386/x86-64-fred.d: Ditto. * testsuite/gas/i386/x86-64-fred.s: Ditto. * testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto. * testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto. * testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto. * testsuite/gas/i386/x86-64-lkgs.d: Ditto. * testsuite/gas/i386/x86-64-lkgs.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New entry for fred, lkgs. * i386-gen.c: Add CPU_FRED CPU_LKGS. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h: Add fred, lkgs. * i386-opc.tbl: Add FRED, LKGS instructions. * i386-tbl.h: Regenerated.
2023-04-07Support Intel AMX-COMPLEXHaochen Jiang1-0/+3
gas/ChangeLog: * NEWS: Support Intel AMX-COMPLEX. * config/tc-i386.c: Add amx_complex. * doc/c-i386.texi: Document .amx_complex. * testsuite/gas/i386/i386.exp: Run AMX-COMPLEX tests. * testsuite/gas/i386/amx-complex-inval.l: New test. * testsuite/gas/i386/amx-complex-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-complex-bad.d: Ditto. * testsuite/gas/i386/x86-64-amx-complex-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-complex-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-complex.d: Ditto. * testsuite/gas/i386/x86-64-amx-complex.s: Ditto. opcodes/ChangeLog: * i386-dis.c (MOD_VEX_0F386C_X86_64_W_0): New. (PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0): Ditto. (X86_64_VEX_0F386C): Ditto. (VEX_LEN_0F386C_X86_64_W_0_M_1): Ditto. (VEX_W_0F386C_X86_64): Ditto. (mod_table): Add MOD_VEX_0F386C_X86_64_W_0. (prefix_table): Add PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0. (x86_64_table): Add X86_64_VEX_0F386C. (vex_len_table): Add VEX_LEN_0F386C_X86_64_W_0_M_1. (vex_w_table): Add VEX_W_0F386C_X86_64. * i386-gen.c (cpu_flag_init): Add CPU_AMX_COMPLEX_FLAGS and CPU_ANY_AMX_COMPLEX_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_COMPLEX): New. (i386_cpu_flags): Add cpuamx_complex. * i386-opc.tbl: Add AMX-COMPLEX instructions. * i386-tbl.h: Regenerated.
2023-03-31x86: introduce .insn directiveJan Beulich1-0/+3
For starters this deals with only very basic constructs.
2023-02-24x86: MONITOR/MWAIT are not SSE3 insnsJan Beulich1-6/+7
These have their own CPUID bit and hence they should also have their own separate control.
2023-02-24x86-64: don't permit LAHF/SAHF with "generic64"Jan Beulich1-4/+5
The feature isn't universally available on 64-bit CPUs. Note that in i386-gen.c:isa_dependencies[] I'm only adding it to models where I'm certain the functionality exists. For Nocona and Core I'm uncertain in particular.
2023-02-10x86: drop use of VEX3SOURCESJan Beulich1-1/+0
The attribute really specifies that the sum of register and memory operands is 4. Express it like that in most places, while using the 2nd (apart from XOP) CPU feature flags (FMA4) in reversed operand matching logic. With the use in build_modrm_byte() gone, part of an assertion there also becomes meaningless - simplify that at the same time. With all uses of the opcode modifier field gone, also drop that.
2023-02-10x86: move (and rename) opcodespace attributeJan Beulich1-19/+53
This really isn't a "modifier" and rather ought to live next to the base opcode anyway. Use the bits we presently have available to fit in the field, renaming it to opcode_space. As an intended side effect this helps readability at the use sites, by shortening the references quite a bit. In generated code arrange for human readable output, by using the SPACE_* constants there rather than raw numbers. This may aid debugging down the road.
2023-01-27x86: remove internationalization from i386-gen.cJan Beulich1-26/+23
This is a build time helper utility, which doesn't require translation.
2023-01-20x86: split i386-gen's opcode hash entry structJan Beulich1-23/+28
All glibc malloc() implementations I've checked have a smallest allocation size worth of 3 pointers, with an increment worth of 2 pointers. Hence mnemonics with multiple templates can be stored more efficiently when maintaining the shared "name" field only in the actual hash entry. (To express the shared nature, also convert "name" to by pointer-to-const.) While doing the conversation also pull out common code from the involved if/else construct in expand_templates().
2023-01-20x86: absorb allocation in i386-genJan Beulich1-2/+5
When generating the mnemonic string table we already set up an identifier for the following entry in a number of cases. Re-use that on the next loop iteration rather than re-doing allocation and conversion.
2023-01-20x86: re-use insn mnemonic strings as much as possibleJan Beulich1-4/+37
Compact the mnemonic string table such that the tails of longer mnemonics are re-used for shorter ones, going beyond what compilers would typically do, but matching what ELF linkers may do when processing SHF_MERGE|SHF_STRINGS sections. This reduces table size by about 12.5%.
2023-01-20x86: move insn mnemonics to a separate tableJan Beulich1-4/+47
Using full pointers to reference the insn mnemonic strings is not very efficient. With overall string size presently just slightly over 20k, even a 16-bit value would suffice. Use "unsigned int" for now, as there's no good use we could presently make of the otherwise saved 16 bits. For 64-bit builds this reduces table size by 6.25% (prior to the recent ISA extension additions it would have been 12.5%), with a similar effect on cache occupation of table entries accessed. For PIE builds of gas this also reduces the number of base relocations quite a bit (obviously independent of bitness).
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-2/+2
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2022-12-22x86: correct/improve TSX controlsJan Beulich1-0/+4
TSXLDTRK takes RTM as a prereq. Additionally introduce an umbrella "tsx" extension option covering both RTM and HLE, paralleling the "abm" one we already have.
2022-12-22x86: add dependencies on SVMEJan Beulich1-0/+6
SEV-ES is an extension to SVME. SNP in turn is an extension to SEV-ES, and yet in turn RMPQUERY is a SNP extension. Note that cpu_arch[] has no SNP entry, so CPU_ANY_SNP_FLAGS remains unused (just like CPU_SNP_FLAGS already is).
2022-12-22x86: add dependencies on VMXJan Beulich1-0/+4
Both EPT and VMFUNC are extensions to VMX.
2022-12-22x86: correct XSAVE* dependenciesJan Beulich1-1/+3
Like various other features AMX-TILE takes XSAVE as a prereq. XSAVES, unconditionally using compacted format, in turn effectively takes XSAVEC as a prereq (an SDM clarification to this effect is in the works).
generated by cgit v1.1 at 2024-08-15 02:15:37 +0000