Age | Commit message (Expand) | Author | Files | Lines |
2020-10-26 | Change avxvnni disassembler output from {vex3} to {vex} | Cui,Lili | 1 | -1/+0 |
2020-10-20 | Add AMD znver3 processor support | Ganesh Gopalasubramanian | 1 | -0/+41 |
2020-10-14 | x86: Support Intel AVX VNNI | H.J. Lu | 1 | -6/+37 |
2020-10-14 | x86: Add support for Intel HRESET instruction | Lili Cui | 1 | -1/+24 |
2020-10-14 | x86: Support Intel UINTR | Lili Cui | 1 | -6/+69 |
2020-10-05 | x86-64: Always display suffix for %LQ in 64bit | H.J. Lu | 1 | -1/+1 |
2020-10-05 | x86: Clear modrm if not needed | H.J. Lu | 1 | -4/+8 |
2020-09-25 | Put together MOD_VEX_0F38* in i386-dis.c, | Cui,Lili | 1 | -62/+62 |
2020-09-24 | Add support for Intel TDX instructions. | Cui,Lili | 1 | -4/+61 |
2020-09-23 | Enable support to Intel Keylocker instructions | Terry Guo | 1 | -7/+100 |
2020-09-02 | ubsan: i386-dis.c | Alan Modra | 1 | -13/+13 |
2020-07-21 | Revert "x86: Don't display eiz with no scale" | Jan Beulich | 1 | -1/+1 |
2020-07-15 | x86: Don't display eiz with no scale | H.J. Lu | 1 | -1/+1 |
2020-07-15 | x86: move putop() case labels to restore alphabetic sorting | Jan Beulich | 1 | -49/+48 |
2020-07-15 | x86: make PUSH/POP disassembly uniform | Jan Beulich | 1 | -30/+20 |
2020-07-15 | x86: avoid attaching suffixes to unambiguous insns | Jan Beulich | 1 | -99/+44 |
2020-07-14 | x86-64: Zero-extend lower 32 bits displacement to 64 bits | H.J. Lu | 1 | -2/+7 |
2020-07-14 | x86/Intel: debug registers are named DRn | Jan Beulich | 1 | -1/+1 |
2020-07-14 | x86: drop Rm and the 'L' macro | Jan Beulich | 1 | -74/+54 |
2020-07-14 | x86: drop Rdq, Rd, and MaskR | Jan Beulich | 1 | -56/+60 |
2020-07-14 | x86: simplify decode of opcodes valid only without any (embedded) prefix | Jan Beulich | 1 | -135/+42 |
2020-07-14 | x86: also use %BW / %DQ for kshift* | Jan Beulich | 1 | -65/+17 |
2020-07-14 | x86: simplify decode of opcodes valid with (embedded) 66 prefix only | Jan Beulich | 1 | -3474/+788 |
2020-07-14 | x86: drop further EVEX table entries that can be served by VEX ones | Jan Beulich | 1 | -12/+8 |
2020-07-14 | x86: drop need_vex_reg | Jan Beulich | 1 | -48/+15 |
2020-07-14 | x86: drop Vex128 and Vex256 | Jan Beulich | 1 | -53/+45 |
2020-07-14 | x86: replace %LW by %DQ | Jan Beulich | 1 | -9/+9 |
2020-07-14 | x86: merge/move logic determining the EVEX disp8 shift | Jan Beulich | 1 | -29/+16 |
2020-07-14 | x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W} | Jan Beulich | 1 | -12/+7 |
2020-07-14 | x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel mode | Jan Beulich | 1 | -37/+15 |
2020-07-14 | x86: fold VCMP_Fixup() into CMP_Fixup() | Jan Beulich | 1 | -70/+45 |
2020-07-14 | x86: don't disassemble MOVBE with two suffixes | Jan Beulich | 1 | -43/+5 |
2020-07-14 | x86: avoid attaching suffix to register-only CRC32 | Jan Beulich | 1 | -75/+2 |
2020-07-14 | x86-64: don't hide an empty but meaningless REX prefix | Jan Beulich | 1 | -5/+9 |
2020-07-14 | x86: drop dead code from OP_IMREG() | Jan Beulich | 1 | -40/+6 |
2020-07-10 | x86: Add support for Intel AMX instructions | Lili Cui | 1 | -5/+346 |
2020-07-08 | x86: various XOP insns lack L and/or W bit decoding | Jan Beulich | 1 | -123/+573 |
2020-07-08 | x86: FMA4 scalar insns ignore VEX.L | Jan Beulich | 1 | -69/+14 |
2020-07-08 | x86: re-work operand swapping for XOP shift/rotate insns | Jan Beulich | 1 | -74/+24 |
2020-07-08 | x86: re-work operand handling for 5-operand XOP insns | Jan Beulich | 1 | -194/+9 |
2020-07-08 | x86: re-work operand swapping for FMA4 and 4-operand XOP insns | Jan Beulich | 1 | -65/+42 |
2020-07-07 | x86: introduce %BW to avoid going through vex_w_table[] | Jan Beulich | 1 | -11/+3 |
2020-07-06 | x86: adjust/correct VFRCZ{P,S}{S,D} decoding | Jan Beulich | 1 | -12/+36 |
2020-07-06 | x86: use %LW / %XW instead of going through vex_w_table[] | Jan Beulich | 1 | -102/+48 |
2020-07-06 | x86: most VBROADCAST{F,I}{32,64}x* only accept memory operands | Jan Beulich | 1 | -8/+16 |
2020-07-06 | x86: drop EVEX table entries that can be made served by VEX ones | Jan Beulich | 1 | -30/+15 |
2020-07-06 | x86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'L | Jan Beulich | 1 | -0/+4 |
2020-07-06 | x86: AVX512 extract/insert insns need to honor EVEX.L'L | Jan Beulich | 1 | -0/+9 |
2020-07-06 | x86: honor VEX.W for VCVT{PH2PS,PS2PH} | Jan Beulich | 1 | -4/+12 |
2020-07-06 | x86: drop EVEX table entries that can be served by VEX ones | Jan Beulich | 1 | -119/+27 |