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path: root/opcodes/aarch64-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich1-12/+0
2019-11-11Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich1-2/+2
2019-11-07[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson1-0/+5
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-0/+74
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-0/+80
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson1-0/+3
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv1-1/+1
2019-07-02[AArch64] Allow MOVPRFX to be used with FMOVRichard Sandiford1-1/+1
2019-07-02[AArch64] Add missing C_MAX_ELEM flags for SVE conversionsRichard Sandiford1-28/+28
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-5/+10
2019-05-09[binutils][aarch64] Add SVE2 instructions.Matthew Malcomson1-0/+419
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-0/+3
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-0/+3
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-2/+5
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-0/+3
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-0/+3
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-0/+2
2019-05-09[binutils][aarch64] SVE2 feature extension flags.Matthew Malcomson1-0/+36
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-0/+18
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-9/+12
2019-04-11[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instructionSudakshina Das1-0/+2
2019-02-07AArch64: Add verifier for By elem Single and Double sized instructions.Tamar Christina1-8/+10
2019-01-25AArch64: Update encodings for stg, st2g, stzg and st2zg.Sudi Das1-10/+10
2019-01-25AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.Sudi Das1-0/+1
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-4/+0
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-12-03[aarch64] - Only use MOV for disassembly when shifter op is LSL #0Egeyar Bagcioglu1-1/+1
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-0/+4
2018-11-12[BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-0/+7
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das1-0/+27
2018-11-12[BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Taggin...Sudakshina Das1-0/+3
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das1-0/+14
2018-11-12[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-ASudakshina Das1-0/+5
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-0/+8
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-0/+10
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das1-0/+6
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das1-0/+21
2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das1-0/+6
2018-10-03AArch64: Mark sve instructions that require MOVPRFX constraintsTamar Christina1-231/+234
2018-07-12This patch adds support for the SSBB and PSSBB speculation barrier instructio...Nick Clifton1-1/+3
2018-07-12Add remainder of Em16 restrictions for AArch64 gas.Tamar Christina1-26/+26
2018-07-06Fix SBO bit in disassembly mask for ldrah on AArch64.Tamar Christina1-1/+1
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-22/+24
2018-06-22Correct negs aliasing on AArch64.Tamar Christina1-1/+1
2018-06-08Prevent undefined FMOV instructions being accepted by the AArch64 assembler.Egeyar Bagcioglu1-2/+16
2018-05-16Fix disassembly mask for vector sdot on AArch64.Tamar Christina1-2/+2
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina1-3/+3
2018-04-25Fix the mask for the sqrdml(a|s)h instructions.Tamar Christina1-2/+2
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-0/+26
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-0/+1