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path: root/opcodes/aarch64-dis-2.c
AgeCommit message (Expand)AuthorFilesLines
2019-05-09[binutils][aarch64] Add SVE2 instructions.Matthew Malcomson1-941/+4120
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-11/+12
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-7/+8
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-10/+11
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-33/+34
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-7/+8
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-19/+20
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-940/+955
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-80/+81
2019-04-11[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instructionSudakshina Das1-1231/+1253
2019-01-25AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.Sudi Das1-1248/+1259
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-1305/+1281
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-1281/+1305
2018-11-12[BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-1275/+1286
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das1-1416/+1528
2018-11-12[BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Taggin...Sudakshina Das1-1514/+1538
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das1-2323/+2351
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-973/+975
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-946/+950
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das1-913/+914
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das1-2125/+2215
2018-07-12This patch adds support for the SSBB and PSSBB speculation barrier instructio...Nick Clifton1-903/+906
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-69/+70
2018-06-22Correct negs aliasing on AArch64.Tamar Christina1-3/+3
2018-05-16Fix disassembly mask for vector sdot on AArch64.Tamar Christina1-158/+178
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-62/+63
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-515/+548
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-899/+900
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina1-2924/+3464
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-89/+95
2017-07-24[AArch64] Fix the bit pattern order in the comments in auto-generated fileJiong Wang1-1686/+1686
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-179/+203
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-1856/+2294
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-2/+2
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-2121/+2158
2016-11-18[AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy1-1151/+1184
2016-11-18[AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy1-1270/+1281
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-1197/+1221
2016-11-11[AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy1-1508/+1640
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-1430/+1442
2016-11-11[AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy1-1442/+1640
2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy1-786/+799
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-115/+7931
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-10/+16
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-25/+32
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-38/+62
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-18/+27