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path: root/opcodes/aarch64-asm-2.c
AgeCommit message (Expand)AuthorFilesLines
2021-03-31Use bool in opcodesAlan Modra1-1/+1
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-124/+124
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-80/+81
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus1-343/+343
2020-10-30[PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus1-89/+92
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus1-122/+122
2020-10-28aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus1-89/+92
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-141/+146
2020-09-08aarch64: Add support for Armv8-R DFB aliasAlex Coplan1-98/+99
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan1-384/+385
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das1-102/+104
2020-04-20[AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das1-109/+109
2020-01-27AArch64: Fix cfinv disassembly issuesTamar Christina1-87/+87
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-38/+39
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-11/+12
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-7/+8
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-10/+11
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-33/+34
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-7/+8
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-19/+20
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-137/+138
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-76/+77
2019-04-11[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instructionSudakshina Das1-295/+295
2019-01-25AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.Sudi Das1-316/+316
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-348/+346
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-346/+348
2018-11-12[BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-316/+316
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das1-386/+388
2018-11-12[BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Taggin...Sudakshina Das1-356/+360
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das1-533/+535
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-151/+153
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-135/+139
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das1-93/+93
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das1-450/+450
2018-07-12This patch adds support for the SSBB and PSSBB speculation barrier instructio...Nick Clifton1-94/+99
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-68/+69
2018-06-22Correct negs aliasing on AArch64.Tamar Christina1-1/+1
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-59/+60
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-56/+57
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-105/+106
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-88/+94
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-72/+81
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-2/+2
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-506/+510
2016-11-18[AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy1-318/+318