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2016-07-11[ARC] Update test.Claudiu Zissulescu2-0/+6
ld/ 2016-07-11 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/nps-1b.err: Update test to handle more verbosity.
2016-07-09PR20337, Objdump makes poor choice of symbolsAlan Modra2-2/+6
binutils/ PR binutils/20337 * objdump.c (compare_symbols): For ELF, sort same value/type symbols according to size. ld/ * testsuite/ld-powerpc/elfv2exe.d: Update.
2016-07-06FT32 linker script cleanupjamesbowman2-1/+9
Fix a typo (__PMSIZE was written as __PMSIZE_) and add section alignment for DATA and BSS. ld/ChangeLog: * scripttempl/ft32.sc (__PMSIZE): Correct __PMSIZE_. (DATA): add ALIGN. (BSS): add ALIGN
2016-07-05Add -flto to PR ld/20321 testH.J. Lu2-1/+5
Before GCC 4.9, -flto is required for final LTO link. Add -flto to PR ld/20321 test to support older versions of GCC. * testsuite/ld-plugin/lto.exp: Add -flto to PR ld/20321 test.
2016-07-05[ARM] Purecode compatible long branch veneer for M-profile targets with MOVW.Andre Vieria4-0/+50
2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * elf32-arm.c (THUMB32_MOVT): New veneer macro. (THUMB32_MOVW): Likewise. (elf32_arm_stub_long_branch_thumb2_only_pure): New. (DEF_STUBS): Define long_branch_thumb2_only_pure. (arm_stub_is_thumb): Add new veneer stub. (arm_type_of_stub): Use new veneer. (arm_stub_required_alignment): Add new veneer. 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * testsuite/ld-arm/farcall-thumb2-purecode.d: New test result. * testsuite/ld-arm/farcall-thumb2-purecode.s: New test. * testsuite/ld-arm/arm-elf.exp: Run it.
2016-07-05[ARM] Change noread to purecode.Andre Vieria2-4/+10
bfd/ChangeLog 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * bfd-in2.h (SEC_ELF_NOREAD): Rename to ... (SEC_ELF_PURECODE): ... this. * elf32-arm.c (elf32_arm_post_process_headers): Rename SEC_ELF_NOREAD to SEC_ELF_NOREAD. (elf32_arm_fake_sections): Likewise. (elf_32_arm_section_flags): Likewise. (elf_32_arm_lookup_section_flags): Likewise. * section.c (SEC_ELF_NOREAD): Rename to ... (SEC_ELF_PURECODE): ... this. binutils/ChangeLog 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * objdump.c (dump_section_header): Rename SEC_ELF_NOREAD to SEC_ELF_NOREAD. * readelf.c (get_elf_section_flags): Rename ARM_NOREAD to ARM_PURECODE and SHF_ARM_NOREAD to SHF_ARM_PURECODE. (process_section_headers): Rename noread to purecode. * section.c (SEC_ELF_NOREAD): Rename to ... (SEC_ELF_PURECODE): ... this. include/ChangeLog 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * elf/arm.h (SHF_ARM_NOREAD): Rename to ... (SHF_ARM_PURECODE): ... this. ld/ChangeLog 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * testsuite/ld-arm/arm_noread.ld: Renamed to ... testsuite/ld-arm/arm_purecode.ld: ... this, and replaced all noread's by purecode.
2016-07-05ld: track linker-definedness of symbolsJan Beulich3-5/+14
Keep "lineno" as zero while not processing any script, and use it being zero to set the "linker_def" field to true.
2016-07-04Warn and return for duplicated pluginH.J. Lu4-0/+28
If a plugin has been loaded already, we should warn and return, instead of adding it on the plugin list. PR ld/20321 * plugin.c (plugin_opt_plugin): Warn and return if plugin has been loaded already. * testsuite/ld-plugin/lto.exp: Run PR ld/20321 test. * testsuite/ld-plugin/pr20321.c: New file.
2016-07-04Allow the flash and ram memory region sizes to be specified in the default ↵Nick Clifton2-4/+14
FT32 linker script. * scripttempl/ft32.sc (__PMSIZE_): If not defined, set to 256K. (__RAMSIZE): If not defined, set to 64K. (MEMORY): Set the flash region size to __PMSIZE and the ram region size to __RAMSIZE.
2016-07-02MIPS/LD/testsuite: Resurrect `branch-misc-2' testMaciej W. Rozycki3-0/+36
Revert: commit c9c1e416d7dd1a35bd7c1a96d034dca1d5071cd1 Author: Alexandre Oliva <aoliva@redhat.com> Date: Thu Dec 12 04:39:44 2002 +0000 <https://sourceware.org/ml/binutils/2002-11/msg00657.html>, ("mips: branches to external labels are broken"), complementing: commit bad36eacdad37042c4efb1c5fbf48476b47de82b Author: Daniel Jacobowitz <drow@false.org> Date: Wed Nov 23 14:04:18 2005 +0000 <https://sourceware.org/ml/binutils/2005-11/msg00324.html>, ("R_MIPS_PC16, again"). ld/ * testsuite/ld-mips-elf/branch-misc-2.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run it.
2016-07-01Fix Thumb-2 BL detectionThomas Preud'homme4-3/+12
2016-07-01 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * elf32-arm.c (using_thumb2_bl): New function. (arm_type_of_stub): Declare thumb2 variable together and change type to bfd_boolean. Use using_thumb2_bl () to determine whether THM_MAX_FWD_BRANCH_OFFSET or THM2_MAX_FWD_BRANCH_OFFSET should be checked for BL range. (elf32_arm_final_link_relocate): Use using_thumb2_bl () to determine the bit size of BL offset. ld/ * testsuite/ld-arm/arm-elf.exp (Thumb-2 BL): Assemble for ARMv7. (Thumb-2 BL on ARMv6-M): New testcase. * testsuite/ld-arm/thumb2-bl.d: Do not try to match testcase filename. * testsuite/ld-arm/thumb2-bl.s: Do not select architecture.
2016-07-01Add marker for 2.27 branch.Tristan Gingold2-0/+6
binutils/ 2016-07-01 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.27. gas/ 2016-07-01 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.27. ld/ 2016-07-01 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.27.
2016-06-28Skip version check for unreferenced and undefined symbolH.J. Lu4-0/+26
No need to check version if symbol is unreferenced and undefined. bfd/ PR ld/20306 * elflink.c (elf_link_check_versioned_symbol): Return false for unreferenced undefined symbol. ld/testsuite/ * testsuite/ld-gc/gc.exp: Run pr20306 test. * ld-gc/pr20306.c: New file. * ld-gc/pr20306.d: Likewise.
2016-06-28Fix more linker testsuite failures.Nick Clifton6-1/+44
bfin * elf32-bfin.c (bfin_adjust_dynamic_symbol): Fail if a COPY reloc is needed. ld * testsuite/ld-elf/comm-data.exp: Expect comm-data2 test to fail for bfin. * testsuite/ld-elf/elf.exp: Expect pr14170 and symbolic function tests to fail for bfin. * testsuite/ld-elf/endsym.d: Expect to fail with cr16, crx, dlx, nds32 and visium. * testsuite/ld-elf/var1.d: Expect to fail with d30v, dlx, ft32 and microblaze. * testsuite/ld-pe/pe.exp: Expect foreign symbol test to fail for mcore-pe.
2016-06-28Fix RX and M68HC11 linker testsuite failures.Nick Clifton8-10/+2
ld * testsuite/ld-elf/merge.d: Add m68hc11 to list of targets that expect to fail this test. * testsuite/ld-scripts/overlay-size.d: Skip the entire test for RX. * testsuite/ld-scripts/rgn-at10.d: No longer expect this test to fail for the RX. * testsuite/ld-scripts/rgn-at11.d: Likewise. * testsuite/ld-scripts/rgn-at2.d: Likewise. * testsuite/ld-scripts/rgn-at6.d: Likewise. * testsuite/ld-scripts/rgn-at7.d: Likewise. * testsuite/ld-scripts/rgn-at8.d: Likewise.
2016-06-28Don't convert R_SPARC_32 to R_SPARC_RELATIVE if class is ELFCLASS64.James Clarke2-1/+6
bfd * elfxx-sparc.c (_bfd_sparc_elf_relocate_section): Don't convert R_SPARC_32 to R_SPARC_RELATIVE if class is ELFCLASS64. gold * sparc.cc (Target_sparc::Scan::local): Don't convert R_SPARC_32 to R_SPARC_RELATIVE if class is ELFCLASS64. (Target_sparc::Scan::global): Likewise. ld * testsuite/ld-elf/symbolic-func.r: Allow non-zero offsets from .text.
2016-06-28MIPS/LD/testsuite: Accept any UNIX OS/ABI with GNU attribute testsMaciej W. Rozycki5-4/+11
Remove failures with FreeBSD targets, e.g: regexp_diff match failure regexp "^ OS/ABI: UNIX - System V$" line " OS/ABI: UNIX - FreeBSD" FAIL: ld-mips-elf/attr-gnu-4-50 introduced with commit 351cdf24d223 ("[MIPS] Implement O32 FPXX, FP64 and FP64A ABI extensions"). ld/ * testsuite/ld-mips-elf/attr-gnu-4-10.d: Match any UNIX OS/ABI. * testsuite/ld-mips-elf/attr-gnu-4-50.d: Likewise. * testsuite/ld-mips-elf/attr-gnu-4-60.d: Likewise. * testsuite/ld-mips-elf/attr-gnu-4-70.d: Likewise.
2016-06-28Don't run ld-scripts/pr20302 on linuxaoutAlan Modra2-1/+6
PR ld/20302 * testsuite/ld-scripts/pr20302.d: Exclude *-*-*aout.
2016-06-28MIPS16: Add R_MIPS16_PC16_S1 branch relocation supportMaciej W. Rozycki7-0/+107
For R_MIPS16_PC16_S1 the calculation is `(sign_extend(A) + S - P) >> 1' and the usual MIPS16 bit shuffling applies to relocated field handling, as per the encoding of the branch target in the extended form of the MIPS16 B, BEQZ, BNEZ, BTEQZ and BTNEZ instructions. include/ * elf/mips.h (R_MIPS16_PC16_S1): New relocation. bfd/ * elf32-mips.c (elf_mips16_howto_table_rel): Add R_MIPS16_PC16_S1. (mips16_reloc_map): Likewise. * elf64-mips.c (mips16_elf64_howto_table_rel): Likewise. (mips16_elf64_howto_table_rela): Likewise. (mips16_reloc_map): Likewise. * elfn32-mips.c (elf_mips16_howto_table_rel): Likewise. (elf_mips16_howto_table_rela): Likewise. (mips16_reloc_map): Likewise. * elfxx-mips.c (mips16_branch_reloc_p): New function. (mips16_reloc_p): Handle R_MIPS16_PC16_S1. (b_reloc_p): Likewise. (mips_elf_calculate_relocation): Likewise. (_bfd_mips_elf_check_relocs): Likewise. * reloc.c (BFD_RELOC_MIPS16_16_PCREL_S1): New relocation. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-mips.c (mips16_reloc_p): Handle BFD_RELOC_MIPS16_16_PCREL_S1. (b_reloc_p): Likewise. (limited_pcrel_reloc_p): Likewise. (md_pcrel_from): Likewise. (md_apply_fix): Likewise. (tc_gen_reloc): Likewise. (md_convert_frag): Likewise. (mips_fix_adjustable): Update comment. * testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-addend-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-addend-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-absolute.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file. * testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-2.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-3.l: Remove file. * testsuite/gas/mips/mips16-branch-absolute.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-2.s: Add padding. * testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid implicit instruction padding, avoid MIPS16 JR->JRC conversion. * testsuite/gas/mips/branch-weak-6.d: New test. * testsuite/gas/mips/branch-weak-7.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/mips16-branch-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-3.d: New test. * testsuite/ld-mips-elf/mips16-branch-addend-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-addend-3.d: New test. * testsuite/ld-mips-elf/mips16-branch.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-06-27Allow a second -T<section>=<addr> to override a previous version on the same ↵Nick Clifton4-0/+22
linker command line. PR ld/20302 * lexsup.c (set_segment_start): If resetting the start address of a section, remember to generate a new script element as well. * testsuite/ld-scripts/pr20302.d: New test. * testsuite/ld-scripts/scripts.exp: Run the new test.
2016-06-24aarch64 ld testsuiteAlan Modra2-10/+13
Fixes failure on aarch64-rtems. * testsuite/ld-aarch64/aarch64-elf.exp (aarch64_choose_ilp32_emul): Don't error out, always return an emulation.
2016-06-24Check DEFAULT_LD_Z_RELRO for -z relro help messageH.J. Lu2-1/+14
* lexsup.c (elf_shlib_list_options): Check DEFAULT_LD_Z_RELRO for -z relro help message.
2016-06-23MIPS/LD/testsuite: Use wildcard address matching in `undefweak-overflow'Maciej W. Rozycki2-20/+25
So that test case updates result in legible dump pattern changes. ld/ * testsuite/ld-mips-elf/undefweak-overflow.d: Use wildcard address matching.
2016-06-23MIPS/LD/testsuite: Uniquely identify `undefweak-overflow' testsMaciej W. Rozycki2-2/+9
ld/ * testsuite/ld-mips-elf/mips-elf.exp: Uniquely identify `undefweak-overflow' tests.
2016-06-22ld: Add a linker configure option --enable-relroH.J. Lu9-4/+112
Add a configure option --enable-relro to decide whether -z relro should be enabled in ELF linker by default. Default to yes for all Linux targets, except FRV, HPPA, IA64 and MIPS, since many relro tests fail on these targets. PR ld/20283 * NEWS: Mention --enable-relro. * configure.ac: Add --enable-relro. (DEFAULT_LD_Z_RELRO): New. Set by --enable-relro. * configure.tgt (ac_default_ld_z_relro): Default it to 1 for some Linux targets. * config.in: Regenerated. * configure: Likewise. * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set link_info.relro to DEFAULT_LD_Z_RELRO. * testsuite/config/default.exp (ld_elf_shared_opt): New. * testsuite/lib/ld-lib.exp (run_dump_test): Pass $ld_elf_shared_opt to ld for ELF targets with shared object support. (run_ld_link_tests): Likewise.
2016-06-21MIPS/BFD: Don't stop processing on a cross-mode jump conversion errorMaciej W. Rozycki3-1/+14
As with commit ed53407eec9e ("MIPS/BFD: Don't stop processing on `bfd_reloc_outofrange'") don't bail out right away and instead continue processing on a cross-mode jump conversion error, so that any further issues are also reported. Adjust message formatting accordingly, using `%X' to abort processing at conclusion. Remove the full stop from the end of the message, for consistency across error reporting. Adjust the corresponding test case accordingly and make it trigger the error twice. bfd/ * elfxx-mips.c (mips_elf_perform_relocation): Call `info->callbacks->einfo' rather than `*_bfd_error_handler' and use the `%X%H' format for the cross-mode jump conversion error message. Remove the full stop from the end of the message. Continue processing rather than returning failure. ld/ * testsuite/ld-mips-elf/mode-change-error-1a.s: Trigger an error twice rather than once. * testsuite/ld-mips-elf/mode-change-error-1.d: Adjust accordingly. Remove the full stop from the end of the message.
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall3-2/+7
gas * config/tc-arc.c (check_cpu_feature, md_parse_option): Add nps400 option and feature. Add check for nps400 feature. Refactor existing checks to check subclass before feature enablement. (md_show_usage): Document flags for NPS-400 and add some other undocumented flags. (cpu_type): Remove nps400 CPU type entry (check_zol): Remove bfd_mach_arc_nps400 case. (md_show_usage): Add help on -mcpu=nps400. (cpu_types): Add entry for nps400 as arc700 plus nps400 extension set. * doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and -fpuda flags. Document -mcpu=nps400. * testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change expected flags to match ARC700 instead of NPS400. * testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400. * testsuite/gas/arc/nps-400-2.d: Likewise. * testsuite/gas/arc/nps-400-3.d: Likewise. * testsuite/gas/arc/nps-400-4.d: Likewise. * testsuite/gas/arc/nps-400-5.d: Likewise. * testsuite/gas/arc/nps-400-6.d: Likewise. * testsuite/gas/arc/nps-400-7.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to avoid clash with cbba instruction. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using -mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags. binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400 case. ld * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400. * testsuite/ld-arc/nps-1b.d: Likewise. include * opcode/arc.h: Add nps400 extension and instruction subclass. Remove ARC_OPCODE_NPS400 * elf/arc.h: Remove E_ARC_MACH_NPS400 opcodes * arc-dis.c (arc_insn_length): Add comment on instruction length. Use same method for determining instruction length on ARC700 and NPS-400. (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions with the NPS400 subclass. * arc-opc.c: Likewise. bfd * archures.c: Remove bfd_mach_arc_nps400. * bfd-in2.h: Likewise. * cpu-arc.c (arch_info_struct): Likewise. * elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing): Likewise.
2016-06-20Use the IR symbol table for the IR input objectH.J. Lu4-0/+37
ELF linker shouldn't skip the IR object when searching the symbol table of an archive element. If linker doesn't know if the object file is an IR object, it should give LTO plugin a chance to get the correct symbol table and use the IR symbol table if the input is an IR object. bfd/ PR ld/18250 PR ld/20267 * elflink.c: Include plugin.h if BFD_SUPPORTS_PLUGINS is defined. (elf_link_is_defined_archive_symbol): Call bfd_link_plugin_object_p on unknown plugin object and use the IR symbol table if the input is an IR object. * plugin.c (bfd_link_plugin_object_p): New function. * plugin.h (bfd_link_plugin_object_p): New prototype. ld/ PR ld/20267 * testsuite/ld-plugin/lto.exp (lto_link_tests): Add test for PR ld/20267. (lto_run_tests): Likewise. * testsuite/ld-plugin/pr20267a.c: New file. * testsuite/ld-plugin/pr20267b.c: Likewise.
2016-06-20PR ld/20276: Set non_ir_ref on common symbolAlan Modra6-13/+58
Also, don't check alignment on symbol from plugin dummy input. bfd/ PR ld/20276 * elflink.c (elf_link_add_object_symbols): Don't check alignment on symbol from plugin dummy input. ld/ PR ld/20276 * plugin.c (plugin_notice): Set non_ir_ref on common symbols. * testsuite/ld-plugin/lto.exp (lto_link_tests): Add test for PR ld/20276. (lto_run_tests): Likewise. * testsuite/ld-plugin/pass.out: New file. * testsuite/ld-plugin/pr20276a.c: Likewise. * testsuite/ld-plugin/pr20276b.c: Likewise.
2016-06-18Rename bfd_plugin_uknown to bfd_plugin_unknownH.J. Lu2-1/+6
bfd/ * bfd.c (bfd_plugin_format): Rename bfd_plugin_uknown to bfd_plugin_unknown. * bfd-in2.h: Regenerated. * plugin.c (bfd_plugin_object_p): Replace bfd_plugin_uknown with bfd_plugin_unknown. ld/ * plugin.c (plugin_object_p): Replace bfd_plugin_uknown with bfd_plugin_unknown.
2016-06-18Don't generate PLT for IFUNC GOT/pointer referenceH.J. Lu83-115/+1342
If a backend supports it, PLT entry isn't needed when all references to a STT_GNU_IFUNC symbols are done via GOT or static function pointers. For GOT entries, We generate dynamic R_*_GLOB_DAT relocations for preemptable symbols and R_*_IRELATIVE relocations for non-preemptable symbols to update them with real function address. For static pointer pointers, we generate dynamic pointer relocations and store them in: 1. .rel[a].ifunc section in PIC object. 2. .rel[a].got section in dynamic executable. 3. .rel[a].iplt section in static executable. We don't allocate GOT entry if it isn't used. bfd/ PR ld/20253 * elf-bfd.h (_bfd_elf_allocate_ifunc_dyn_relocs): Add an bfd_boolean argument. * elf-ifunc.c (_bfd_elf_create_ifunc_sections): Replace "shared object" with "PIC object" in comments. (_bfd_elf_allocate_ifunc_dyn_relocs): Updated. Replace "shared object" with "PIC object" in comments. Avoid PLT if requested. Generate dynamic relocations for non-GOT references. Make room for the special first entry in PLT and allocate PLT entry only for PLT and PC-relative references. Store dynamic GOT relocations in .rel[a].iplt section for static executables. If PLT isn't used, always use GOT for symbol value. Don't allocate GOT entry if it isn't used. * elf32-i386.c (elf_i386_check_relocs): Increment PLT reference count only in the code section. Allocate dynamic pointer relocation against STT_GNU_IFUNC symbol in the non-code section. (elf_i386_adjust_dynamic_symbol): Increment PLT reference count only for PC-relative references. (elf_i386_allocate_dynrelocs): Pass TRUE to _bfd_elf_allocate_ifunc_dyn_relocs. (elf_i386_relocate_section): Allow R_386_GOT32/R_386_GOT32X relocations against STT_GNU_IFUNC symbols without PLT. Generate dynamic pointer relocation against STT_GNU_IFUNC symbol in the non-code section and store it in the proper REL section. Don't allow non-pointer relocation against STT_GNU_IFUNC symbol without PLT. (elf_i386_finish_dynamic_symbol): Generate dynamic R_386_IRELATIVE and R_386_GLOB_DAT GOT relocations against STT_GNU_IFUNC symbols without PLT. (elf_i386_finish_dynamic_sections): Don't handle local STT_GNU_IFUNC symbols here. (elf_i386_output_arch_local_syms): Handle local STT_GNU_IFUNC symbols here. (elf_backend_output_arch_local_syms): New. * elf32-x86-64.c (elf_i386_check_relocs): Increment PLT reference count only in the code section. Allocate dynamic pointer relocation against STT_GNU_IFUNC symbol in the non-code section. (elf_x86_64_adjust_dynamic_symbol): Increment PLT reference count only for PC-relative references. (elf_x86_64_allocate_dynrelocs): Pass TRUE to _bfd_elf_allocate_ifunc_dyn_relocs. (elf_x86_64_relocate_section): Allow R_X86_64_GOTPCREL, R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCREL64 relocations against STT_GNU_IFUNC symbols without PLT. Generate dynamic pointer relocation against STT_GNU_IFUNC symbol in the non-code section and store it in the proper RELA section. Don't allow non-pointer relocation against STT_GNU_IFUNC symbol without PLT. (elf_x86_64_finish_dynamic_symbol): Generate dynamic R_X86_64_IRELATIVE and R_X86_64_GLOB_DAT GOT relocations against STT_GNU_IFUNC symbols without PLT. (elf_x86_64_finish_dynamic_sections): Don't handle local STT_GNU_IFUNC symbols here. (elf_x86_64_output_arch_local_syms): Handle local STT_GNU_IFUNC symbols here. (elf_backend_output_arch_local_syms): New. * elfnn-aarch64.c (elfNN_aarch64_allocate_ifunc_dynrelocs): Pass FALSE to _bfd_elf_allocate_ifunc_dyn_relocs. ld/ PR ld/20253 * testsuite/ld-i386/i386.exp: Run PR ld/20253 tests. * testsuite/ld-i386/no-plt.exp: Likewise. * testsuite/ld-x86-64/no-plt.exp: Likewise. * testsuite/ld-i386/pr13302.d: Remove .rel.plt section. * testsuite/ld-ifunc/ifunc-13-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-13-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-15-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-15-x86-64.d: Likewise. * testsuite/ld-x86-64/pr13082-5a.d: Likewise. * testsuite/ld-x86-64/pr13082-5b.d: Likewise. * testsuite/ld-x86-64/pr13082-6a.d: Likewise. * testsuite/ld-x86-64/pr13082-6b.d: Likewise. * testsuite/ld-i386/pr20244-2a.d: Remove .plt section. * testsuite/ld-ifunc/ifunc-21-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-22-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise. * testsuite/ld-i386/pr20244-2b.d: Updated. * testsuite/ld-i386/pr20244-2c.d: Likewise. * testsuite/ld-ifunc/ifunc-18a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-18a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-x86-64.d: Likewise. * testsuite/ld-i386/pr20253-1a.c: New file. * testsuite/ld-i386/pr20253-1b.S: Likewise. * testsuite/ld-i386/pr20253-1c.S: Likewise. * testsuite/ld-i386/pr20253-1d.S: Likewise. * testsuite/ld-i386/pr20253-2a.c: Likewise. * testsuite/ld-i386/pr20253-2b.S: Likewise. * testsuite/ld-i386/pr20253-2c.S: Likewise. * testsuite/ld-i386/pr20253-2d.S: Likewise. * testsuite/ld-i386/pr20253-3.d: Likewise. * testsuite/ld-i386/pr20253-3.s: Likewise. * testsuite/ld-i386/pr20253-4.s: Likewise. * testsuite/ld-i386/pr20253-4a.d: Likewise. * testsuite/ld-i386/pr20253-4b.d: Likewise. * testsuite/ld-i386/pr20253-4c.d: Likewise. * testsuite/ld-i386/pr20253-5.d: Likewise. * testsuite/ld-i386/pr20253-5.s: Likewise. * testsuite/ld-ifunc/ifunc-23-x86.s: Likewise. * testsuite/ld-ifunc/ifunc-23a-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-23b-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-23c-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-24-x86.s: Likewise. * testsuite/ld-ifunc/ifunc-24a-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-24b-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-24c-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-25-x86.s: Likewise. * testsuite/ld-ifunc/ifunc-25a-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-25b-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-25c-x86.d: Likewise. * testsuite/ld-x86-64/pr20253-1.s: Likewise. * testsuite/ld-x86-64/pr20253-1a.d: Likewise. * testsuite/ld-x86-64/pr20253-1b.d: Likewise. * testsuite/ld-x86-64/pr20253-1c.d: Likewise. * testsuite/ld-x86-64/pr20253-1d.d: Likewise. * testsuite/ld-x86-64/pr20253-1e.d: Likewise. * testsuite/ld-x86-64/pr20253-1f.d: Likewise. * testsuite/ld-x86-64/pr20253-1g.d: Likewise. * testsuite/ld-x86-64/pr20253-1h.d: Likewise. * testsuite/ld-x86-64/pr20253-1i.d: Likewise. * testsuite/ld-x86-64/pr20253-1j.d: Likewise. * testsuite/ld-x86-64/pr20253-1k.d: Likewise. * testsuite/ld-x86-64/pr20253-1l.d: Likewise. * testsuite/ld-x86-64/pr20253-2a.c: Likewise. * testsuite/ld-x86-64/pr20253-2b.S: Likewise. * testsuite/ld-x86-64/pr20253-2c.S: Likewise. * testsuite/ld-x86-64/pr20253-2d.S: Likewise. * testsuite/ld-x86-64/pr20253-3.d: Likewise. * testsuite/ld-x86-64/pr20253-3.s: Likewise. * testsuite/ld-x86-64/pr20253-4.s: Likewise. * testsuite/ld-x86-64/pr20253-4a.d: Likewise. * testsuite/ld-x86-64/pr20253-4b.d: Likewise. * testsuite/ld-x86-64/pr20253-4c.d: Likewise. * testsuite/ld-x86-64/pr20253-4d.d: Likewise. * testsuite/ld-x86-64/pr20253-4e.d: Likewise. * testsuite/ld-x86-64/pr20253-4f.d: Likewise. * testsuite/ld-x86-64/pr20253-5.s: Likewise. * testsuite/ld-x86-64/pr20253-5a.d: Likewise. * testsuite/ld-x86-64/pr20253-5b.d: Likewise. * testsuite/ld-ifunc/ifunc-18a-i386.d: Remove extra IRELATIVE relocation. * testsuite/ld-ifunc/ifunc-18a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-18a.s: Fix a typo. * testsuite/ld-x86-64/x86-64.exp: Run pr20253-1 tests.
2016-06-17Add support for Thumb-2 long branch veneersThomas Preud'homme5-13/+34
2016-06-17 Thomas Preud'homme <thomas.preudhomme@arm.com> Tony Wang <tony.wang@arm.com> bfd/ * elf32-arm.c (elf32_arm_stub_long_branch_thumb2_only): Define stub sequence. (stub_long_branch_thumb2_only): Define stub. (arm_stub_is_thumb): Add case for arm_stub_long_branch_thumb2_only. (arm_stub_long_branch_thumb2_only): Likewise. (arm_type_of_stub): Use arm_stub_long_branch_thumb2_only for Thumb-2 capable targets. ld/ * testsuite/ld-arm/arm-elf.exp (Thumb-Thumb farcall M profile): Assemble for ARMv6-M. (Thumb2-Thumb2 farcall M profile): New testcase. * testsuite/ld-arm/farcall-thumb2-thumb2-m.d: New file. * testsuite/ld-arm/jump-reloc-veneers-cond-long-backward.d: Update to reflect the use of Thumb-2 veneers for Thumb-2 capable targets. * testsuite/ld-arm/jump-reloc-veneers-cond-long.d: Likewise.
2016-06-16Add missing ChangeLog entriesH.J. Lu1-0/+7
commit bf52d7c72035679e6b3ab601133c56a4388f4dc9 Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed Jun 15 10:35:38 2016 -0700 Don't check undefined symbol for IFUNC reloc
2016-06-16Don't check undefined symbol for IFUNC relocH.J. Lu3-4/+23
Since x86 elf_*_check_relocs is called after all symbols have been resolved, there is no need to check undefined symbols for relocations against IFUNC symbols. bfd/ * elf32-i386.c (elf_i386_check_relocs): Don't check undefined symbols for relocations against IFUNC symbols. * elf64-x86-64.c (elf_x86_64_check_relocs): Likewise. ld/ * testsuite/ld-i386/i386.exp: Run pr19636-2e-nacl. * testsuite/ld-i386/pr19636-2e.d: Skip for NaCl targets. Remove .rel.plt section. * testsuite/ld-i386/pr19636-2e-nacl.d: New file.
2016-06-15X86: Add tests for static function pointerH.J. Lu24-6/+116
* testsuite/ld-i386/no-plt-check1a.S (check): Test static function pointer. * testsuite/ld-i386/no-plt-check1b.S (check): Likewise. * testsuite/ld-x86-64/no-plt-check1.S (check): Likewise. * testsuite/ld-i386/no-plt-extern1a.S (func_p): New. Static function pointer. * testsuite/ld-i386/no-plt-extern1b.S (func_p): Likewise. * testsuite/ld-x86-64/no-plt-extern1.S (func_p): Likewise. * testsuite/ld-i386/no-plt-1a.dd: Updated. * testsuite/ld-i386/no-plt-1b.dd: Likewise. * testsuite/ld-i386/no-plt-1c.dd: Likewise. * testsuite/ld-i386/no-plt-1d.dd: Likewise. * testsuite/ld-i386/no-plt-1e.dd: Likewise. * testsuite/ld-i386/no-plt-1f.dd: Likewise. * testsuite/ld-i386/no-plt-1g.dd: Likewise. * testsuite/ld-i386/no-plt-1h.dd: Likewise. * testsuite/ld-i386/no-plt-1i.dd: Likewise. * testsuite/ld-i386/no-plt-1j.dd: Likewise. * testsuite/ld-x86-64/no-plt-1a.dd: Likewise. * testsuite/ld-x86-64/no-plt-1b.dd: Likewise. * testsuite/ld-x86-64/no-plt-1c.dd: Likewise. * testsuite/ld-x86-64/no-plt-1d.dd: Likewise. * testsuite/ld-x86-64/no-plt-1e.dd: Likewise. * testsuite/ld-x86-64/no-plt-1f.dd: Likewise. * testsuite/ld-x86-64/no-plt-1g.dd: Likewise.
2016-06-15Fix PR ld/20254Senthil Kumar Selvaraj3-0/+29
This patch fixes another edge case related to alignment property records - reloc offsets adjacent to property record offsets were not getting adjusted during relaxation. bfd/ PR ld/20254 * elf32-avr.c (elf32_avr_relax_delete_bytes): Adjust reloc offsets until reloc_toaddr. ld/ PR ld/20254 * testsuite/ld-avr/avr-prop-6.d: New test. * testsuite/ld-avr/avr-prop-6.s: New test.
2016-06-14Formatting fixes.Alan Modra10-185/+207
* ldbuildid.c: Formatting. * ldcref.c: Formatting. * ldctor.c: Formatting. * ldemul.c: Formatting. * ldexp.c: Formatting. * ldfile.c: Formatting. * ldlang.c: Formatting. * ldmain.c: Formatting. * ldwrite.c: Formatting.
2016-06-14Delete bfd_my_archive macroAlan Modra5-16/+23
Many more places use abfd->my_archive rather than bfd_my_archive (abfd), so let's make the code consistently use the first idiom. bfd/ * bfd-in.h (bfd_my_archive): Delete. * bfd-in2.h: Regenerate. binutils/ * ar.c: Expand uses of bfd_my_archive. * size.c: Likewise. ld/ * ldlang.c: Expand uses of bfd_my_archive. * ldmain.c: Likewise. * ldmisc.c: Likewise. * plugin.c: Likewise.
2016-06-14Set my_archive for thin archivesAlan Modra4-7/+23
LTO plugin support in plugin_maybe_claim wants to close the IR bfd after replacing it with the recompiled object, but can't do so for archive elements due to various pointers that access the archive bfd. Thin archives have the same problem. They too cannot have their element bfds closed. PR ld/20241 bfd/ * archive.c (open_nested_file): Set my_archive. * bfd.c (_bfd_default_error_handler <%B>): Exclude archive file name for thin archives. * bfdio.c (bfd_tell): Don't adjust origin for thin archives. (bfd_seek): Likewise. * bfdwin.c (bfd_get_file_window): Likewise. * cache.c (cache_bmmap): Likewise. (bfd_cache_lookup_worker): Don't look in my_archive for thin archives. * mach-o.c (bfd_mach_o_follow_dsym): Don't open my_archive for thin archives. * plugin.c (try_claim): Likewise. * xcofflink.c (xcoff_link_add_dynamic_symbols): Use import path of file within thin archive, not the archive. binutils/ * bucomm.c (bfd_get_archive_filename): Return file name within thin archive. ld/ * ldmain.c (add_archive_element): Just print file name of file within thin archives. * ldmisc.c (vfinfo): Likewise. * plugin.c (plugin_object_p): Open file within thin archives. (plugin_maybe_claim): Expand comment.
2016-06-13Add the GOT base for GOT32 relocs against IFUNCH.J. Lu12-0/+235
Add the GOT base for R_386_GOT32/R_386_GOT32X relocations against IFUNC symbols if there is no base register and disallow them for PIC. bfd/ PR ld/20244 * elf32-i386.c (elf_i386_relocate_section): Add the .got.plt section address for R_386_GOT32/R_386_GOT32X relocations against IFUNC symbols if there is no base register and return error for PIC. ld/ PR ld/20244 * testsuite/ld-i386/i386.exp: Run pr20244-2a, pr20244-2b, pr20244-2c and pr20244-2d. * testsuite/ld-i386/no-plt.exp: Run pr20244-3a and pr20244-3b. * testsuite/ld-i386/pr20244-2.s: New file. * testsuite/ld-i386/pr20244-2a.d: Likewise. * testsuite/ld-i386/pr20244-2b.d: Likewise. * testsuite/ld-i386/pr20244-2c.d: Likewise. * testsuite/ld-i386/pr20244-2d.d: Likewise. * testsuite/ld-i386/pr20244-3a.c: Likewise. * testsuite/ld-i386/pr20244-3b.S: Likewise. * testsuite/ld-i386/pr20244-3c.S: Likewise. * testsuite/ld-i386/pr20244-3d.S: Likewise.
2016-06-13Add 2 i386 tests to call IFUNC functions via GOTH.J. Lu6-0/+196
bfd/ * elf32-i386.c (elf_i386_relocate_section): Simplify IFUNC GOT32 adjustment for static executables. ld/ 2016-06-13 H.J. Lu <hongjiu.lu@intel.com> * testsuite/ld-i386/i386.exp: Run ifunc-1a and ifunc-1b. * testsuite/ld-i386/ifunc-1a.c: New file. * testsuite/ld-i386/ifunc-1b.S: Likewise. * testsuite/ld-i386/ifunc-1c.S: Likewise. * testsuite/ld-i386/ifunc-1d.S: Likewise.
2016-06-13[ARC] XFAIL S-Records tests for both little and big endian ARC target.Cupertino Miranda2-2/+7
ld/ 2016-06-13 Cupertino Miranda <cmiranda@synospsy.com> * testsuite/ld-srec/srec.exp: Changed to XFAIL on both little and big endian ARC targets.
2016-06-12Update x86-64 no-PLT tests for x32H.J. Lu16-40/+58
X32 has different output formats for readelf and objdump as well as a different conversion of load symbol address via GOT. * testsuite/ld-x86-64/libno-plt-1b.dd: Updated for x32. * testsuite/ld-x86-64/libno-plt-1b.rd: Likewise. * testsuite/ld-x86-64/no-plt-1a.dd: Likewise. * testsuite/ld-x86-64/no-plt-1a.rd: Likewise. * testsuite/ld-x86-64/no-plt-1b.dd: Likewise. * testsuite/ld-x86-64/no-plt-1b.rd: Likewise. * testsuite/ld-x86-64/no-plt-1c.dd: Likewise. * testsuite/ld-x86-64/no-plt-1c.rd: Likewise. * testsuite/ld-x86-64/no-plt-1d.dd: Likewise. * testsuite/ld-x86-64/no-plt-1e.dd: Likewise. * testsuite/ld-x86-64/no-plt-1e.rd: Likewise. * testsuite/ld-x86-64/no-plt-1f.dd: Likewise. * testsuite/ld-x86-64/no-plt-1f.rd: Likewise. * testsuite/ld-x86-64/no-plt-1g.dd: Likewise. * testsuite/ld-x86-64/no-plt-1g.rd: Likewise.
2016-06-11Subtract GOT base only with a base registerH.J. Lu6-0/+70
When relocating R_386_GOT32 in "op $0, bar@GOT", we shouldn't subtract GOT base without a base register and we should disallow it without a base register for PIC. bfd/ PR ld/20244 * elf32-i386.c (elf_i386_relocate_section): When relocating R_386_GOT32, return error without a base register for PIC and subtract the .got.plt section address only with a base register. ld/ PR ld/20244 * testsuite/ld-i386/i386.exp: Run pr20244-1a and pr20244-1b. * testsuite/ld-i386/pr20244-1.s: New file. * testsuite/ld-i386/pr20244-1a.d: Likewise. * testsuite/ld-i386/pr20244-1b.d: Likewise. * testsuite/ld-i386/pr20244-1c.d: Likewise.
2016-06-09Add missing ChangeLog entriesH.J. Lu1-0/+32
2016-06-09Fix PR 20221 - adjust syms and relocs only if relax shrunk section.Denis Chertykov3-0/+24
This patch fixes an edge case in linker relaxation that causes symbol values to be computed incorrectly in the presence of align directives in input source code. bfd/ * elf32-avr.c (elf32_avr_relax_delete_bytes): Adjust syms and relocs only if shrinking occurred. ld/ * testsuite/ld-avr/avr-prop-5.d: New. * testsuite/ld-avr/avr-prop-5.s: New.
2016-06-09Print symbol names in comments for LDS/STS disassembly.Denis Chertykov5-0/+81
This patch adds default data address space origin (0x800000) to the symbol addresses. when disassemble lds/sts instructions. So that symbol names shall be printed in comments for lds/sts instructions disassemble. ld/ * testsuite/ld-avr/lds-mega.d: New test. * testsuite/ld-avr/lds-mega.s: New test source. * testsuite/ld-avr/lds-tiny.d: New test. * testsuite/ld-avr/lds-tiny.s: New test source. opcodes/ * avr-dis.c (avr_operand): Add default data address space origin (0x800000) to the address and set as symbol address for LDS/ STS immediate operands.
2016-06-08i386: Test external function reference without PLTH.J. Lu29-0/+876
To call an external function, the direct branch to the PLT entry can be replaced by an indirect branch via the GOT slot, which is similar to the first instruction in the PLT slot. Instead using the PLT slot as function address, the function address is retrieved from the GOT slot. The R_386_GOT32X relocation can be used to compute the address of the symbol’s GOT entry without base register when PIC is disabled. In non-PIC executable, call/jmp *func@GOT should be used for indirect branch via the GOT slot and movl func@GOT, %eax should be used to load function address. Unlike PIC case, no register is needed to access GOT. If linker determines the function is defined locally, it converts indirect branch via the GOT slot to direct branch with a nop prefix and converts load via the GOT slot to load immediate or lea. * testsuite/ld-i386/libno-plt-1b.dd: New file. * testsuite/ld-i386/libno-plt-1b.rd: Likewise. * testsuite/ld-i386/no-plt-1a.dd: Likewise. * testsuite/ld-i386/no-plt-1a.rd: Likewise. * testsuite/ld-i386/no-plt-1b.dd: Likewise. * testsuite/ld-i386/no-plt-1b.rd: Likewise. * testsuite/ld-i386/no-plt-1c.dd: Likewise. * testsuite/ld-i386/no-plt-1c.rd: Likewise. * testsuite/ld-i386/no-plt-1d.dd: Likewise. * testsuite/ld-i386/no-plt-1d.rd: Likewise. * testsuite/ld-i386/no-plt-1e.dd: Likewise. * testsuite/ld-i386/no-plt-1e.rd: Likewise. * testsuite/ld-i386/no-plt-1f.dd: Likewise. * testsuite/ld-i386/no-plt-1f.rd: Likewise. * testsuite/ld-i386/no-plt-1g.dd: Likewise. * testsuite/ld-i386/no-plt-1g.rd: Likewise. * testsuite/ld-i386/no-plt-1h.dd: Likewise. * testsuite/ld-i386/no-plt-1h.rd: Likewise. * testsuite/ld-i386/no-plt-1i.dd: Likewise. * testsuite/ld-i386/no-plt-1i.rd: Likewise. * testsuite/ld-i386/no-plt-1j.dd: Likewise. * testsuite/ld-i386/no-plt-1j.rd: Likewise. * testsuite/ld-i386/no-plt-check1a.S: Likewise. * testsuite/ld-i386/no-plt-check1b.S: Likewise. * testsuite/ld-i386/no-plt-extern1a.S: Likewise. * testsuite/ld-i386/no-plt-extern1b.S: Likewise. * testsuite/ld-i386/no-plt-func1.c: Likewise. * testsuite/ld-i386/no-plt-main1.c: Likewise. * testsuite/ld-i386/no-plt.exp: Likewise.
2016-06-08Update test nameH.J. Lu2-1/+6
* testsuite/ld-x86-64/tls.exp (run_cc_link_tests): Update test name.
2016-06-08Support i386 TLS code sequences without PLTH.J. Lu30-0/+2554
We can generate i386 TLS code sequences for general and local dynamic models without PLT, which uses indirect call via GOT: call *___tls_get_addr@GOT(%reg) where EBX register isn't required as GOT base, instead of direct call: call ___tls_get_addr[@PLT] which requires EBX register as GOT base. Since direct call is 4-byte long and indirect call, is 5-byte long, the extra one byte must be handled properly. For general dynamic model, 7-byte lea instruction before call instruction is replaced by 6-byte one to make room for indirect call. For local dynamic model, we simply use 5-byte indirect call. TLS linker optimization is updated to recognize new instruction patterns. For local dynamic model to local exec model transition, we generate a 6-byte lea instruction as nop, instead of a 1-byte nop plus a 4-byte lea instruction. Since linker may convert call ___tls_get_addr[@PLT] to addr32 call ____tls_get_addr when producing static executable, both patterns are recognized. bfd/ * elf64-i386.c (elf_i386_link_hash_entry): Add tls_get_addr. (elf_i386_link_hash_newfunc): Initialize tls_get_addr to 2. (elf_i386_check_tls_transition): Check indirect call and direct call with the addr32 prefix for general and local dynamic models. Set the tls_get_addr feild. (elf_i386_convert_load_reloc): Always use addr32 prefix for indirect ___tls_get_addr call via GOT. (elf_i386_relocate_section): Handle GD->LE, GD->IE and LD->LE transitions with indirect call and direct call with the addr32 prefix. ld/ * testsuite/ld-i386/i386.exp: Run libtlspic2.so, tlsbin2, tlsgd3, tlsld2, tlsgd4, tlspie3a, tlspie3b and tlspie3c. * testsuite/ld-i386/pass.out: New file. * testsuite/ld-i386/tls-def1.c: Likewise. * testsuite/ld-i386/tls-gd1.S: Likewise. * testsuite/ld-i386/tls-ld1.S: Likewise. * testsuite/ld-i386/tls-main1.c: Likewise. * testsuite/ld-i386/tls.exp: Likewise. * testsuite/ld-i386/tlsbin2-nacl.rd: Likewise. * testsuite/ld-i386/tlsbin2.dd: Likewise. * testsuite/ld-i386/tlsbin2.rd: Likewise. * testsuite/ld-i386/tlsbin2.sd: Likewise. * testsuite/ld-i386/tlsbin2.td: Likewise. * testsuite/ld-i386/tlsbinpic2.s: Likewise. * testsuite/ld-i386/tlsgd3.dd: Likewise. * testsuite/ld-i386/tlsgd3.s: Likewise. * testsuite/ld-i386/tlsgd4.d: Likewise. * testsuite/ld-i386/tlsgd4.s: Likewise. * testsuite/ld-i386/tlsld2.s: Likewise. * testsuite/ld-i386/tlspic2-nacl.rd: Likewise. * testsuite/ld-i386/tlspic2.dd: Likewise. * testsuite/ld-i386/tlspic2.rd: Likewise. * testsuite/ld-i386/tlspic2.sd: Likewise. * testsuite/ld-i386/tlspic2.td: Likewise. * testsuite/ld-i386/tlspic3.s: Likewise. * testsuite/ld-i386/tlspie3.s: Likewise. * testsuite/ld-i386/tlspie3a.d: Likewise. * testsuite/ld-i386/tlspie3b.d: Likewise. * testsuite/ld-i386/tlspie3c.d: Likewise.
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