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2023-09-25Revert "arc: Update opcode related include files for ARCv3."Claudiu Zissulescu6-452/+96
This reverts commit 04414221df53bb5129e34bec354dae3121db436a.
2023-09-25arc: Update opcode related include files for ARCv3.Claudiu Zissulescu6-96/+452
Add new ARCv3 CPUs and required bits to decode/encode ARCv3 ISA opcodes. Fix 32 bit relocations which were set as signed but should be bitfield: ARC_32_ME, ARC_GLOB_DAT, ARC_JMP_SLOT, ARC_RELATIVE. Remove non-ABI relocation ARC_32_ME_S. include/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> Cupertino Miranda <cupertinomiranda@gmail.com> Bruno Mauricio <brunoasmauricio@gmail.com> * include/elf/arc-cpu.def: Add new HS5x and HS6x CPUs. * include/elf/arc-reloc.def: Add new ARC64 relocations. * include/elf/arc.h (EF_ARC_CPU_ARC64): New define. * include/opcode/arc-attrs.h (FEATURE_LIST_NAME): Update predicate. * include/opcode/arc-func.h: Update formating. (replace_disp8ls): New function. (replace_disp9s): Likewise. (replace_disp6s): Likewise. (replace_disp7s): Likewise. (replace_disp12s): Likewise. * include/opcode/arc.h (ARC_OPCODE_ARC64): New define. (ARC_OPCODE_ARC32): Likewise. (ARC_OPERAND_FP): Likewise. (HARD_FIELDF): Likewise. (ARC_OPCODE_ARCVx): New macro. (arc_flag_class): Update structure to hold new extract/insert functions for flags. (INSN3OP): Update macro. (FP_SIZE, TPOF, DPOF, SOPF, COPF, CONVOPS): New enums. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-05RISC-V: fold duplicate code in vector_macro()Jan Beulich1-1/+0
There's no need to have almost identical code twice. Do away with M_VMSGEU and instead simply use an unused (for these macros) field to tell apart both variants.
2023-09-05RISC-V: Add 'Smcntrpmf' extension and its CSRsTsukasa OI1-4/+12
This commit adds now stable and approved 'Smcntrpmf' extension defined by the RISC-V Cycle and Instret Privilege Mode Filtering specification. Note that, because mcyclecfg and minstretcfg CSRs conflict with the privileged specification version 1.9.1, CSRs for this extension are only enabled on the privileged specification version 1.10 or later. By checking the base privileged specification, we no longer need to change the design of base CSR handling. This is based on the specification version v1.0_rc1 (Frozen): <https://github.com/riscv/riscv-smcntrpmf/commit/32b752c40d59c1b5e95de83399c1f54be6669163> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add implication rule from the new 'Smcntrpmf' extension. (riscv_supported_std_s_ext): Add 'Smcntrpmf' to the supported S extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add new CSR classes CSR_CLASS_SMCNTRPMF and CSR_CLASS_SMCNTRPMF_32. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. Move "mscounteren" and "mhcounteren" CSRs and note that they are now aliases. * testsuite/gas/riscv/csr-dw-regnums.d: Reflect the change. * testsuite/gas/riscv/csr.s: Add new CSRs. Move "mscounteren" and "mhcounteren" CSRs and note that they are now reused for the 'Smcntrpmf' extension. * testsuite/gas/riscv/csr-version-1p9p1.d: Reflect the changes of csr.s. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h: Add new CSRs noting that this extension is incompatible with the privileged specification version 1.9.1. Move "mscounteren" and "mhcounteren" CSRs, make them aliases and reuse the CSR numbers from the 'Smcntrpmf' extension. (CSR_MSCOUNTEREN, CSR_MHCOUNTEREN) Remove as "mscounteren" and "mhcounteren" are now aliases and new CSR macros are used instead. (CSR_MCYCLECFG, CSR_MINSTRETCFG, CSR_MCYCLECFGH, CSR_MINSTRETCFGH): New CSR macros.
2023-08-27PE dos_messageAlan Modra3-3/+3
I was looking at dos_message and wondering why we have H_PUT_32 in _bfd_XXi_only_swap_filehdr_out but no H_GET_32 in pe_bfd_object_p. On a big-endian machine this would result in scrambling the code and strings constained in dos_message. Rather than fix the lack of H_GET_32 in pe_bfd_object_p, I decided it doesn't make sense to store dos_message internally as an array of ints. include/ * coff/internal.h (struct internal_extra_pe_filehdr): Make dos_message a char array. * coff/msdos.h (struct external_DOS_hdr): Flatten dos_message. * coff/pe.h (struct external_PEI_filehdr): Likewise. bfd/ * libcoff-in.h (struct pe_tdata): Make dos_message a char array. * libcoff.h: Regenerate. * peXXigen.c (_bfd_XXi_only_swap_filehdr_out): memcpy dos_message to output. * peicode.h (pe_mkobject): Don't memset already zeroed pe_opthdr. Tidy allocation of tdata.pe_obj_data. Set up dos_message from.. (default_dos_message): ..this. New static array.
2023-08-22aarch64: Improve naming conventions for A and R-profile architectureVictor Do Nascimento1-54/+54
Historically, flags and variables relating to architectural revisions for the A-profile architecture omitted the trailing `A' such that, for example, assembling for `-march=armv8.4-a' set the `AARCH64_ARCH_V8_4' flag in the assembler. This leads to some ambiguity, since Binutils also targets the R-profile Arm architecture. Therefore, it seems prudent to have everything associated with the A-profile cores end in `A' and likewise `R' for the R-profile. Referring back to the example above, the flag set for `-march=armv8.4-a' is better characterized if labeled `AARCH64_ARCH_V8_4A'. The only exception to the rule of appending `A' to variables is found in the handling of the `AARCH64_FEATURE_V8' macro, as it is the baseline from which ALL processors derive and should therefore be left unchanged. In reflecting the `ARM' architectural nomenclature choices, where we have `ARM_ARCH_V8A' and `ARM_ARCH_V8R', the choice is made to not have an underscore separating the numerical revision number and the A/R-profile indicator suffix. This has meant that renaming of R-profile related flags and variables was warranted, thus going from `.*_[vV]8_[rR]' to `.*_[vV]8[rR]'. Finally, this is more in line with conventions within GCC and adds consistency across the toolchain. gas/ChangeLog: * gas/config/tc-aarch64.c: (aarch64_cpus): Reference to arch feature macros updated. (aarch64_archs): Likewise. include/ChangeLog: * include/opcode/aarch64.h: (AARCH64_FEATURE_V8A): Updated name: V8_A -> V8A. (AARCH64_FEATURE_V8_1A): A-suffix added. (AARCH64_FEATURE_V8_2A): Likewise. (AARCH64_FEATURE_V8_3A): Likewise. (AARCH64_FEATURE_V8_4A): Likewise. (AARCH64_FEATURE_V8_5A): Likewise. (AARCH64_FEATURE_V8_6A): Likewise. (AARCH64_FEATURE_V8_7A): Likewise. (AARCH64_FEATURE_V8_8A):Likewise. (AARCH64_FEATURE_V9A): Likewise. (AARCH64_FEATURE_V8R): Updated name: V8_R -> V8R. (AARCH64_ARCH_V8A_FEATURES): Updated name: V8_A -> V8A. (AARCH64_ARCH_V8_1A_FEATURES): A-suffix added. (AARCH64_ARCH_V8_2A_FEATURES): Likewise. (AARCH64_ARCH_V8_3A_FEATURES): Likewise. (AARCH64_ARCH_V8_4A_FEATURES): Likewise. (AARCH64_ARCH_V8_5A_FEATURES): Likewise. (AARCH64_ARCH_V8_6A_FEATURES): Likewise. (AARCH64_ARCH_V8_7A_FEATURES): Likewise. (AARCH64_ARCH_V8_8A_FEATURES): Likewise. (AARCH64_ARCH_V9A_FEATURES): Likewise. (AARCH64_ARCH_V9_1A_FEATURES): Likewise. (AARCH64_ARCH_V9_2A_FEATURES): Likewise. (AARCH64_ARCH_V9_3A_FEATURES): Likewise. (AARCH64_ARCH_V8A): Updated name: V8_A -> V8A. (AARCH64_ARCH_V8_1A): A-suffix added. (AARCH64_ARCH_V8_2A): Likewise. (AARCH64_ARCH_V8_3A): Likewise. (AARCH64_ARCH_V8_4A): Likewise. (AARCH64_ARCH_V8_5A): Likewise. (AARCH64_ARCH_V8_6A): Likewise. (AARCH64_ARCH_V8_7A): Likewise. (AARCH64_ARCH_V8_8A): Likewise. (AARCH64_ARCH_V9A): Likewise. (AARCH64_ARCH_V9_1A): Likewise. (AARCH64_ARCH_V9_2A): Likewise. (AARCH64_ARCH_V9_3A): Likewise. (AARCH64_ARCH_V8_R): Updated name: V8_R -> V8R. opcodes/ChangeLog: * opcodes/aarch64-opc.c (SR_V8A): Updated name: V8_A -> V8A. (SR_V8_1A): A-suffix added. (SR_V8_2A): Likewise. (SR_V8_3A): Likewise. (SR_V8_4A): Likewise. (SR_V8_6A): Likewise. (SR_V8_7A): Likewise. (SR_V8_8A): Likewise. (aarch64_sys_regs): Reference to arch feature macros updated. (aarch64_pstatefields): Reference to arch feature macros updated. (aarch64_sys_ins_reg_supported_p): Reference to arch feature macros updated. * opcodes/aarch64-tbl.h: (aarch64_feature_v8_2a): a-suffix added. (aarch64_feature_v8_3a): Likewise. (aarch64_feature_fp_v8_3a): Likewise. (aarch64_feature_v8_4a): Likewise. (aarch64_feature_fp_16_v8_2a): Likewise. (aarch64_feature_v8_5a): Likewise. (aarch64_feature_v8_6a): Likewise. (aarch64_feature_v8_7a): Likewise. (aarch64_feature_v8r): Updated name: v8_r-> v8r. (ARMV8R): Updated name: V8_R-> V8R. (ARMV8_2A): A-suffix added. (ARMV8_3A): Likewise. (FP_V8_3A): Likewise. (ARMV8_4A): Likewise. (FP_F16_V8_2A): Likewise. (ARMV8_5): Likewise. (ARMV8_6A): Likewise. (ARMV8_6A_SVE): Likewise. (ARMV8_7A): Likewise. (V8_2A_INSN): `A' added to macro symbol. (V8_3A_INSN): Likewise. (V8_4A_INSN): Likewise. (FP16_V8_2A_INSN): Likewise. (V8_5A_INSN): Likewise. (V8_6A_INSN): Likewise. (V8_7A_INSN): Likewise. (V8R_INSN): Updated name: V8_R-> V8R.
2023-08-21bpf: correct neg and neg32 instruction encodingDavid Faust1-2/+2
The neg/neg32 BPF instructions always use BPF_SRC_K (=0) in their header source bit, despite operating on registers. If BPF_SRC_X (=1) is set, the instructions are rejected by the kernel. Because of this there are also no neg/neg32 instructions which operate on immediates, so remove them. bd434cc4d94ec3d2f9fc1e7c00c27b074f962bc1 was a similar fix in the old CGEN-based port, but was not carried forward in the new port. include/ * opcode/bpf.h (enum bpf_insn_id): Remove spurious entries BPF_INSN_NEGI and BPF_INSN_NEG32I. opcodes/ * bpf-opc.c (bpf_opcodes): Remove erroneous NEGI and NEG32I instructions. gas/ * doc/c-bpf.texi (BPF Instructions): Remove erroneous neg and neg32 instructions operating on immediates. * testsuite/gas/bpf/alu.s: Adapt accordingly. * testsuite/gas/bpf/alu.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise * testsuite/gas/bpf/alu32.s: Likewise. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-08-21aarch64/sme2: Teach binutils/BFD about the NT_ARM_ZT register setLuis Machado1-0/+2
The Scalable Matrix Extension v2 (SME2) defines a new register, ZT0, that the Linux Kernel handles through a new NT_ARM_ZT register set. Teach binutils/BFD about it so that gdb can make use of it for reading and writing core files. This also enables readelf/objdump to show the correct identification for the NT_ARM_ZT register set. Validated under Fast Models.
2023-08-16kvx: New port.Paul Iannetta4-0/+3356
2023-08-15RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'Tsukasa OI1-0/+1
The documentation of the 'Zfa' extension states that "fli.h" is available "if the Zfh or Zvfh extension is implemented" (both the latest and the oldest editions are checked). This fact was not reflected in Binutils ('Zvfh' implies 'Zfhmin', not full 'Zfh' extension and "fli.h" required 'Zfh' and 'Zfa' extensions). This commit makes "fli.h" also available when both 'Zfa' and 'Zvfh' extensions are implemented. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add new instruction class handling. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zfa-zvfh.s: New test. * testsuite/gas/riscv/zfa-zvfh.d: Ditto. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add new instruction class. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Change instruction class of "fli.h" from INSN_CLASS_ZFH_AND_ZFA to new INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA.
2023-08-15RISC-V: Add support for the 'Zihintntl' extensionTsukasa OI2-0/+28
This commit adds 'Zihintntl' extension and its hint instructions. This is based on: <https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6da7791d5a733c553e6e2506ddcab5>, the first ISA Manual noting that the 'Zihintntl' extension is ratified. Note that compressed 'Zihintntl' hints require either 'C' or 'Zca' extension. Co-authored-by: Nelson Chu <nelson@rivosinc.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zihintntl' standard hint 'Z' extension. (riscv_multi_subset_supports): Support new instruction classes. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zihintntl.s: New test for 'Zihintntl' including auto-compression without C prefix and explicit C prefix. * testsuite/gas/riscv/zihintntl.d: Likewise. * testsuite/gas/riscv/zihintntl-na.d: Likewise. * testsuite/gas/riscv/zihintntl-base.s: New test for correspondence between 'Zihintntl' and base 'I' or 'C' instructions. * testsuite/gas/riscv/zihintntl-base.d: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add new instruction classes: INSN_CLASS_ZIHINTNTL and INSN_CLASS_ZIHINTNTL_AND_C. (MASK_NTL_P1, MATCH_NTL_P1, MASK_NTL_PALL, MATCH_NTL_PALL, MASK_NTL_S1, MATCH_NTL_S1, MASK_NTL_ALL, MATCH_NTL_ALL, MASK_C_NTL_P1, MATCH_C_NTL_P1, MASK_C_NTL_PALL, MATCH_C_NTL_PALL, MASK_C_NTL_S1, MATCH_C_NTL_S1, MASK_C_NTL_ALL, MATCH_C_NTL_ALL): New. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add instructions from the 'Zihintntl' extension.
2023-08-15RISC-V: remove indirection from register tablesJan Beulich1-7/+9
The longest register name is 4 characters (plus a nul one), so using a 4- or 8-byte pointer to get at it is neither space nor time efficient. Embed the names right into the array. For PIE this also reduces the number of base relocations in the final image. To avoid old gcc, when generating 32-bit code, bogusly warning about bounds being exceeded in the code processing Cs/Cw, Ct/Cx, and CD, an adjustment to EXTRACT_BITS() is needed: This macro shouldn't supply a 64-bit value, and it also doesn't need to - all operand fields to date are far more narrow than 32 bits. This in turn allows dropping a number of casts elsewhere.
2023-08-12gcc: xtensa: add data alignment properties to dynconfigMax Filippov1-1/+58
include/ * xtensa-dynconfig.h (xtensa_config_v4): New struct. (XCHAL_DATA_WIDTH, XCHAL_UNALIGNED_LOAD_EXCEPTION) (XCHAL_UNALIGNED_STORE_EXCEPTION, XCHAL_UNALIGNED_LOAD_HW) (XCHAL_UNALIGNED_STORE_HW, XTENSA_CONFIG_V4_ENTRY_LIST): New definitions. (XTENSA_CONFIG_INSTANCE_LIST): Add xtensa_config_v4 instance. (XTENSA_CONFIG_ENTRY_LIST): Add XTENSA_CONFIG_V4_ENTRY_LIST.
2023-08-12gcc: xtensa: add XCHAL_HAVE_{CLAMPS, DEPBITS, EXCLUSIVE, XEA3} to dynconfigMax Filippov1-1/+49
include/ * xtensa-dynconfig.h (xtensa_config_v3): New struct. (xtensa_get_config_v3): New declaration. (XCHAL_HAVE_CLAMPS, XCHAL_HAVE_DEPBITS, XCHAL_HAVE_EXCLUSIVE) (XCHAL_HAVE_XEA3, XTENSA_CONFIG_V3_ENTRY_LIST): New definitions. (XTENSA_CONFIG_INSTANCE_LIST): Add xtensa_config_v3 instance. (XTENSA_CONFIG_ENTRY_LIST): Add XTENSA_CONFIG_V3_ENTRY_LIST.
2023-08-12LoongArch: implement count_{leading,trailing}_zerosXi Ruoyao1-0/+12
LoongArch always support clz and ctz instructions, so we can always use __builtin_{clz,ctz} for count_{leading,trailing}_zeros. This improves the code of libgcc, and also benefits Glibc once we merge longlong.h there. Bootstrapped and regtested on loongarch64-linux-gnu. include/ * longlong.h [__loongarch__] (count_leading_zeros): Define. [__loongarch__] (count_trailing_zeros): Likewise. [__loongarch__] (COUNT_LEADING_ZEROS_0): Likewise.
2023-08-12Updated constants from <https://dwarfstd.org/Languages.php>Meghan Denny1-0/+10
include/ * dwarf2.h: Update with additional languages from dwarf standard.
2023-08-12c++: source position of lambda captures [PR84471]Jason Merrill1-1/+1
include/ * ansidecl.h (ATTRIBUTE_WARN_UNUSED_RESULT): Add __.
2023-08-12Libvtv: Add loongarch support.Lulu Cheng1-0/+4
The loongarch64 specification permits page sizes of 4KiB, 16KiB and 64KiB, but only 16KiB pages are supported for now. Co-Authored-By: qijingwen <qijingwen@loongson.cn> include/ * vtv-change-permission.h (defined): Determines whether the macro __loongarch_lp64 is defined (VTV_PAGE_SIZE): Set VTV_PAGE_SIZE to 16KiB for loongarch64.
2023-08-03Remove PEI_HEADERS defineTom Tromey4-0/+21
I noticed a few files double-included libcoff.h, and digging deeper I found that the PEI_HEADERS define is a sort of external include guard. This patch adds include guards to the few files in include/coff that were missing one, and then removes the PEI_HEADERS workaround and the redundant includes. I didn't see anything in these files that indicated that double-inclusion would be useful, so it seems to me that this approach is ok. Tested by rebuilding with --enable-targets=all. 2023-08-02 Tom Tromey <tromey@adacore.com> * pei-x86_64.c (PEI_HEADERS): Do not define. * pei-loongarch64.c (PEI_HEADERS): Do not define. * pei-aarch64.c (PEI_HEADERS): Do not define. * pe-x86_64.c (PEI_HEADERS): Do not define. * pe-aarch64.c (PEI_HEADERS): Do not define. * libpei.h (_LIBPEI_H): Add include guard. * coff-x86_64.c (PEI_HEADERS): Do not check. * coff-loongarch64.c (PEI_HEADERS): Do not check. * coff-aarch64.c (PEI_HEADERS): Do not check. include/ChangeLog 2023-08-02 Tom Tromey <tromey@adacore.com> * coff/x86_64.h (COFF_X86_64_H): Add include guard. * coff/loongarch64.h (COFF_LOONGARCH64_H): Add include guard. * coff/aarch64.h (COFF_AARCH64_H): Add include guard.
2023-08-02Revert "2.41 Release sources"Sam James6-3/+92
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton6-92/+3
2023-07-30bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flagsJose E. Marchesi3-1/+12
This patch adds support for EF_BPF_CPUVER bits in the ELF machine-dependent header flags. These bits encode the BPF CPU version for which the object file has been compiled for. The BPF assembler is updated so it annotates the object files it generates with these bits. The BPF disassembler is updated so it honors EF_BPF_CPUVER to use the appropriate ISA version if the user didn't specify an explicit ISA version in the command line. Note that a value of zero in EF_BPF_CPUVER is interpreted by the disassembler as "use the later supported version" (the BPF CPU versions start with v1.) The readelf utility is updated to pretty print EF_BPF_CPUVER when it prints out the ELF header: $ readelf -h a.out ELF Header: ... Flags: 0x4, CPU Version: 4 Tested in bpf-unknown-none. include/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/bpf.h (EF_BPF_CPUVER): Define. * opcode/bpf.h (BPF_XBPF): Change from 0xf to 0xff so it fits in EF_BPF_CPUVER. binutils/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * readelf.c (get_machine_flags): Recognize and pretty print BPF machine flags. opcodes/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-dis.c: Initialize asm_bpf_version to -1. (print_insn_bpf): Set BPF ISA version from the cpu version ELF header flags if no explicit version set in the command line. * disassemble.c (disassemble_init_for_target): Remove unused code. gas/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.h (elf_tc_final_processing): Define. * config/tc-bpf.c (bpf_elf_final_processing): New function.
2023-07-25bpf: Add atomic compare-and-exchange instructionsDavid Faust1-1/+5
This patch adds the two remaining BPF v3 atomic instructions: - BPF_INSN_ACMP{,32}: atomic compare-and-swap - BPF_INSN_AXCHG{,32}: atomic (non-conditional) exchange Tests and documentation are also updated. gas/ * doc/c-bpf.texi (BPF Instructions): Document atomic exchange and atomic compare-and-swap instructions. * testsuite/gas/bpf/atomic.s: Test ACMP, ACMP32, AXCHG, AXCGH32 instructions. * testsuite/gas/bpf/atomic.d: Likewise. * testsuite/gas/bpf/atomic-be.d: Likewise. * testsuite/gas/bpf/atomic-pseudoc.s: Likewise. * testsuite/gas/bpf/atomic-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-be-pseudoc.d: Likewise. include/ * opcode/bpf.h (BPF_IMM32_ACMP): Fix typo. (enum bpf_insn_id): New entries for BPF_INSN_ACMP{,32} and BPF_INSN_AXCHG{,32}. opcodes/ * bpf-opc.c (bpf_opcodes): Add entries for ACMP{,32} and AXCHG{,32} instructions.
2023-07-24bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64}Jose E. Marchesi2-0/+13
This patch adds support for the BPF V4 ISA byte swap instructions to opcodes, assembler and disassembler. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (BPF_IMM32_BSWAP16): Define. (BPF_IMM32_BSWAP32): Likewise. (BPF_IMM32_BSWAP64): Likewise. (enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}. opcodes/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP* instructions. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions. * testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions. * testsuite/gas/bpf/alu.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
2023-07-24bpf: add support for jal/gotol jump instruction with 32-bit targetJose E. Marchesi2-1/+7
This patch adds support for the V4 BPF instruction jal/gotol, which is like ja/goto but it supports a signed 32-bit PC-relative (in number of 64-bit words minus one) target operand instead of the 16-bit signed operand of the other instruction. This greatly increases the jump range in BPF programs. Tested in bpf-unkown-none. bfd/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32. * elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc. * libbfd.h (bfd_reloc_code_real_names): Regenerate. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (struct bpf_insn): New field `id'. (md_assemble): Save the ids of successfully parsed instructions and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate. (md_apply_fix): Adapt to the new BFD reloc. * testsuite/gas/bpf/jump.s: Test JAL. * testsuite/gas/bpf/jump.d: Likewise. * testsuite/gas/bpf/jump-pseudoc.d: Likewise. * testsuite/gas/bpf/jump-be.d: Likewise. * testsuite/gas/bpf/jump-be-pseudoc.d: Likewise. * doc/c-bpf.texi (BPF Instructions): Document new instruction jal/gotol. Document new operand type disp32. include/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL. (enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI. opcodes/ChangeLog: 2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entry for jal.
2023-07-21bpf: opcodes, gas: support for signed load V4 instructionsJose E. Marchesi2-0/+9
This commit adds the signed load to register (ldxs*) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Add entries for signed load instructions. (BPF_MODE_SMEM): Define. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW} instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: Add signed load instructions. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be.d: Likewise. * doc/c-bpf.texi (BPF Instructions): Document the signed load instructions.
2023-07-21bpf: opcodes, gas: support for signed register move V4 instructionsJose E. Marchesi2-0/+13
This commit adds the signed register move (movs) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. (BPF_OFFSET16_MOVS16): Likewise. (BPF_OFFSET16_MOVS32): Likewise. (enum bpf_insn_id): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R instructions. and MOVS32I instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.s: Test movs instructions. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu.d: Add expected results. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-21DesCGENization of the BPF binutils portJose E. Marchesi3-0/+308
CGEN is cool, but the BPF architecture is simply too bizarre for it. The weird way of BPF to handle endianness in instruction encoding, the weird C-like alternative assembly syntax, the weird abuse of multi-byte (or infra-byte) instruction fields as opcodes, the unusual presence of opcodes beyond the first 32-bits of some instructions, are all examples of what makes it a PITA to continue using CGEN for this port. The bpf.cpu file is becoming so complex and so nested with p-macros that it is very difficult to read, and quite challenging to update. Also, every time we are forced to change something in CGEN to accommodate BPF requirements (which is often) we have to do extensive testing to make sure we do not break any other target using CGEN. This is getting un-maintenable. So I have decided to bite the bullet and revamp/rewrite the port so it no longer uses CGEN. Overall, this involved: * To remove the cpu/bpf.{cpu,opc} descriptions. * To remove the CGEN generated files. * To replace the CGEN generated opcodes table with a new hand-written opcodes table for BPF. * To replace the CGEN generated disassembler wih a new disassembler that uses the new opcodes. * To replace the CGEN generated assembler with a new assembler that uses the new opcodes. * To replace the CGEN generated simulator with a new simulator that uses the new opcodes. [This is pushed in GDB in another patch.] * To adapt the build systems to the new situation. Additionally, this patch introduces some extensions and improvements: * A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These relocations are used for section-relative 16-bit offsets used in load/store instructions. * The disassembler now has support for the "pseudo-c" assembly syntax of BPF. What dialect to use when disassembling is controlled by a command line option. * The disassembler now has support for dumping instruction immediates in either octal, hexadecimal or decimal. The used output base is controlled by a new command-line option. * The GAS BPF test suite has been re-structured and expanded in order to test the disassembler pseudoc syntax support. Minor bugs have been also fixed there. The assembler generic tests that were disabled for bpf-*-* targets due to the previous implementation of pseudoc syntax are now re-enabled. Additional tests have been added to test the new features of the assembler. .dump files are no longer used. * The linker BPF test suite has been adapted to the command line options used by the new disassembler. The result is very satisfactory. This patchs adds 3448 lines of code and removes 10542 lines of code. Tested in: * Target bpf-unknown-none with 64-bit little-endian host and 32-bit little-endian host. * Target x86-64-linux-gnu with --enable-targets=all Note that I have not tested in a big-endian host yet. I will do so once this lands upstream so I can use the GCC compiler farm. I have not included ChangeLog entries in this patch: these would be massive and not very useful, considering this is pretty much a rewrite of the port. I beg the indulgence of the global maintainers.
2023-07-18RISC-V: Supports Zcb extension.Jiawei2-0/+52
This patch support Zcb extension, contains new compressed instructions, some instructions depend on other existed extension, like 'zba', 'zbb' and 'zmmul'. Zcb also imply Zca extension to enable the compressing features. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcb.d: New test. * testsuite/gas/riscv/zcb.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_C_LBU): New opcode. (MASK_C_LBU): New mask. (MATCH_C_LHU): New opcode. (MASK_C_LHU): New mask. (MATCH_C_LH): New opcode. (MASK_C_LH): New mask. (MATCH_C_SB): New opcode. (MASK_C_SB): New mask. (MATCH_C_SH): New opcode. (MASK_C_SH): New mask. (MATCH_C_ZEXT_B): New opcode. (MASK_C_ZEXT_B): New mask. (MATCH_C_SEXT_B): New opcode. (MASK_C_SEXT_B): New mask. (MATCH_C_ZEXT_H): New opcode. (MASK_C_ZEXT_H): New mask. (MATCH_C_SEXT_H): New opcode. (MASK_C_SEXT_H): New mask. (MATCH_C_ZEXT_W): New opcode. (MASK_C_ZEXT_W): New mask. (MATCH_C_NOT): New opcode. (MASK_C_NOT): New mask. (MATCH_C_MUL): New opcode. (MASK_C_MUL): New mask. (DECLARE_INSN): New opcode. * opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func. (EXTRACT_ZCB_HALFWORD_UIMM): Ditto. (ENCODE_ZCB_BYTE_UIMM): Ditto. (ENCODE_ZCB_HALFWORD_UIMM): Ditto. (VALID_ZCB_BYTE_UIMM): Ditto. (VALID_ZCB_HALFWORD_UIMM): Ditto. (enum riscv_insn_class): New extension class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operators. * riscv-opc.c: New instructions.
2023-07-14AIX_WEAK_SUPPORTAlan Modra1-1/+1
Making target code depend on a host define like _AIX52 is never correct, so out it goes. Also, sort some config.bfd entries a little to make it more obvious there is a config difference between aix5.1 and aix5.2. These two changes should make no difference to anything in binutils. The gas define of AIX_WEAK_SUPPORT on the other hand was wrong, so fix that. Finally, fix some testsuite fails on aix < 5.2 by simply not running the tests. include/ * coff/internal.h (C_WEAKEXT): Don't depend on _AIX52. bfd/ * coffcode.h (coff_slurp_symbol_table): Don't depend on _AIX52. (coff_classify_symbol): Likewise. * config.bfd: Sort some entries. gas/ * configure.ac (AIX_WEAK_SUPPORT): Don't set for aix5.[01]. * configure: Regenerate. * testsuite/gas/ppc/aix.exp (xcoff-visibility-1*) Don't run for aix < 5.2.
2023-07-03RISC-V: Zvkh[a,b]: Remove individual instruction classChristoph Müllner1-2/+0
Currently we have three instruction classes defined for Zvkh[a,b]: - INSN_CLASS_ZVKNHA - INSN_CLASS_ZVKNHB - INSN_CLASS_ZVKNHA_OR_ZVKNHB The encodings of all instructions in Zvknh[a,b] are identical. Therefore, we don't need the individual instruction classes and can remove them. This patch also adds the missing support of the combined instruction class in riscv_multi_subset_supports_ext(). Fixes: 62edb233ef5 ("RISC-V: Add support for the Zvknh[a,b] ISA extensions") Reported-By: Nelson Chu <nelson@rivosinc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-03Add markers for the 2.41 branchNick Clifton1-0/+4
2023-07-01RISC-V: Add support for the Zvksh ISA extensionChristoph Müllner2-0/+9
Zvksh is part of the vector crypto extensions. This extension adds the following instructions: - vsm3me.vv - vsm3c.vi bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvksh. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvksh.d: New test. * testsuite/gas/riscv/zvksh.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSM3C_VI): New. (MASK_VSM3C_VI): New. (MATCH_VSM3ME_VV): New. (MASK_VSM3ME_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvksh. opcodes/ChangeLog: * riscv-opc.c: Add Zvksh instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvksed ISA extensionChristoph Müllner2-0/+12
Zvksed is part of the vector crypto extensions. This extension adds the following instructions: - vsm4k.vi - vsm4r.[vv,vs] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvksed. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvksed.d: New test. * testsuite/gas/riscv/zvksed.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSM4K_VI): New. (MASK_VSM4K_VI): New. (MATCH_VSM4R_VS): New. (MASK_VSM4R_VS): New. (MATCH_VSM4R_VV): New. (MASK_VSM4R_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvksed. opcodes/ChangeLog: * riscv-opc.c: Add Zvksed instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvknh[a,b] ISA extensionsChristoph Müllner2-0/+14
Zvknh[a,b] are parts of the vector crypto extensions. This extension adds the following instructions: - vsha2ms.vv - vsha2c[hl].vv bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvknh[a,b]. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvknha.d: New test. * testsuite/gas/riscv/zvknha_zvknhb.s: New test. * testsuite/gas/riscv/zvknhb.d: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New. (MASK_VSHA2CH_VV): New. (MATCH_VSHA2CL_VV): New. (MASK_VSHA2CL_VV): New. (MATCH_VSHA2MS_VV): New. (MASK_VSHA2MS_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvknh[a,b]. opcodes/ChangeLog: * riscv-opc.c: Add Zvknh[a,b] instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkned ISA extensionChristoph Müllner2-0/+36
Zvkned is part of the vector crypto extensions. This extension adds the following instructions: - vaesef.[vv,vs] - vaesem.[vv,vs] - vaesdf.[vv,vs] - vaesdm.[vv,vs] - vaeskf1.vi - vaeskf2.vi - vaesz.vs bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvkned. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvkned.d: New test. * testsuite/gas/riscv/zvkned.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VAESDF_VS): New. (MASK_VAESDF_VS): New. (MATCH_VAESDF_VV): New. (MASK_VAESDF_VV): New. (MATCH_VAESDM_VS): New. (MASK_VAESDM_VS): New. (MATCH_VAESDM_VV): New. (MASK_VAESDM_VV): New. (MATCH_VAESEF_VS): New. (MASK_VAESEF_VS): New. (MATCH_VAESEF_VV): New. (MASK_VAESEF_VV): New. (MATCH_VAESEM_VS): New. (MASK_VAESEM_VS): New. (MATCH_VAESEM_VV): New. (MASK_VAESEM_VV): New. (MATCH_VAESKF1_VI): New. (MASK_VAESKF1_VI): New. (MATCH_VAESKF2_VI): New. (MASK_VAESKF2_VI): New. (MATCH_VAESZ_VS): New. (MASK_VAESZ_VS): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvkned. opcodes/ChangeLog: * riscv-opc.c: Add Zvkned instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkg ISA extensionChristoph Müllner2-0/+9
Zvkg is part of the vector crypto extensions. This extension adds the following instructions: - vghsh.vv - vgmul.vv bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvkg. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvkg.d: New test. * testsuite/gas/riscv/zvkg.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VGHSH_VV): New. (MASK_VGHSH_VV): New. (MATCH_VGMUL_VV): New. (MASK_VGMUL_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvkg. opcodes/ChangeLog: * riscv-opc.c: Add Zvkg instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvbc extensionNathan Huckleberry2-0/+15
Zvbc is part of the crypto vector extensions. This extension adds the following instructions: - vclmul.[vv,vx] - vclmulh.[vv,vx] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvbc. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvbc.d: New test. * testsuite/gas/riscv/zvbc.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VCLMUL_VV): New. (MASK_VCLMUL_VV): New. (MATCH_VCLMUL_VX): New. (MASK_VCLMUL_VX): New. (MATCH_VCLMULH_VV): New. (MASK_VCLMULH_VV): New. (MATCH_VCLMULH_VX): New. (MASK_VCLMULH_VX): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvbc. opcodes/ChangeLog: * riscv-opc.c: Add Zvbc instruction. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvbb ISA extensionChristoph Müllner2-0/+55
Zvbb is part of the vector crypto extensions. This extension adds the following instructions: - vandn.[vv,vx] - vbrev.v - vbrev8.v - vrev8.v - vclz.v - vctz.v - vcpop.v - vrol.[vv,vx] - vror.[vv,vx,vi] - vwsll.[vv,vx,vi] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvbb. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add 'l' as new format string directive. (riscv_ip): Likewise. * testsuite/gas/riscv/zvbb.d: New test. * testsuite/gas/riscv/zvbb.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VANDN_VV): New. (MASK_VANDN_VV): New. (MATCH_VANDN_VX): New. (MASK_VANDN_VX): New. (MATCH_VBREV8_V): New. (MASK_VBREV8_V): New. (MATCH_VBREV_V): New. (MASK_VBREV_V): New. (MATCH_VCLZ_V): New. (MASK_VCLZ_V): New. (MATCH_VCPOP_V): New. (MASK_VCPOP_V): New. (MATCH_VCTZ_V): New. (MASK_VCTZ_V): New. (MATCH_VREV8_V): New. (MASK_VREV8_V): New. (MATCH_VROL_VV): New. (MASK_VROL_VV): New. (MATCH_VROL_VX): New. (MASK_VROL_VX): New. (MATCH_VROR_VI): New. (MASK_VROR_VI): New. (MATCH_VROR_VV): New. (MASK_VROR_VV): New. (MATCH_VROR_VX): New. (MASK_VROR_VX): New. (MATCH_VWSLL_VI): New. (MASK_VWSLL_VI): New. (MATCH_VWSLL_VV): New. (MASK_VWSLL_VV): New. (MATCH_VWSLL_VX): New. (MASK_VWSLL_VX): New. (DECLARE_INSN): New. * opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New. (ENCODE_RVV_VI_UIMM6): New. (enum riscv_insn_class): Add instruction class for Zvbb. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add 'l' as new format string directive. * riscv-opc.c: Add Zvbb instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-06-30RISC-V: Add support for the Zfa extensionChristoph Müllner2-0/+105
This patch adds support for the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Modular Convert-to-Integer) * fmv* to access high bits of FP registers in case XLEN < FLEN * fleq/fltq (quiet comparison instructions) Zfa defines its instructions in combination with the following extensions: * single-precision floating-point (F) * double-precision floating-point (D) * quad-precision floating-point (Q) * half-precision floating-point (Zfh) This patch is based on an earlier version from Tsukasa OI: https://sourceware.org/pipermail/binutils/2022-September/122939.html Most significant change to that commit is the switch from the rs1-field value to the actual floating-point value in the last operand of the fli* instructions. Everything that strtof() can parse is accepted and the '%a' printf specifier is used to output hex floating-point literals in the disassembly. The Zfa specification is frozen (and has passed public review). It is available as a chapter in "The RISC-V Instruction Set Manual: Volume 1": https://github.com/riscv/riscv-isa-manual/releases bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for 'Zfa' extension. (riscv_multi_subset_supports_ext): Likewise. (riscv_implicit_subsets): Add 'Zfa' -> 'F' dependency. gas/ChangeLog: * config/tc-riscv.c (flt_lookup): New helper to lookup a float value in an array. (validate_riscv_insn): Add 'Wfv' as new format string directive. (riscv_ip): Likewise. * doc/c-riscv.texi: Add floating-point chapter and describe limiations of the Zfa FP literal parsing. * testsuite/gas/riscv/zfa-32.d: New test. * testsuite/gas/riscv/zfa-32.s: New test. * testsuite/gas/riscv/zfa-64.d: New test. * testsuite/gas/riscv/zfa-64.s: New test. * testsuite/gas/riscv/zfa-fail.d: New test. * testsuite/gas/riscv/zfa-fail.l: New test. * testsuite/gas/riscv/zfa-fail.s: New test. * testsuite/gas/riscv/zfa.d: New test. * testsuite/gas/riscv/zfa.s: New test. * testsuite/gas/riscv/zfa.s: New test. * opcode/riscv-opc.h (MATCH_FLI_H): New. (MASK_FLI_H): New. (MATCH_FMINM_H): New. (MASK_FMINM_H): New. (MATCH_FMAXM_H): New. (MASK_FMAXM_H): New. (MATCH_FROUND_H): New. (MASK_FROUND_H): New. (MATCH_FROUNDNX_H): New. (MASK_FROUNDNX_H): New. (MATCH_FLTQ_H): New. (MASK_FLTQ_H): New. (MATCH_FLEQ_H): New. (MASK_FLEQ_H): New. (MATCH_FLI_S): New. (MASK_FLI_S): New. (MATCH_FMINM_S): New. (MASK_FMINM_S): New. (MATCH_FMAXM_S): New. (MASK_FMAXM_S): New. (MATCH_FROUND_S): New. (MASK_FROUND_S): New. (MATCH_FROUNDNX_S): New. (MASK_FROUNDNX_S): New. (MATCH_FLTQ_S): New. (MASK_FLTQ_S): New. (MATCH_FLEQ_S): New. (MASK_FLEQ_S): New. (MATCH_FLI_D): New. (MASK_FLI_D): New. (MATCH_FMINM_D): New. (MASK_FMINM_D): New. (MATCH_FMAXM_D): New. (MASK_FMAXM_D): New. (MATCH_FROUND_D): New. (MASK_FROUND_D): New. (MATCH_FROUNDNX_D): New. (MASK_FROUNDNX_D): New. (MATCH_FLTQ_D): New. (MASK_FLTQ_D): New. (MATCH_FLEQ_D): New. (MASK_FLEQ_D): New. (MATCH_FLI_Q): New. (MASK_FLI_Q): New. (MATCH_FMINM_Q): New. (MASK_FMINM_Q): New. (MATCH_FMAXM_Q): New. (MASK_FMAXM_Q): New. (MATCH_FROUND_Q): New. (MASK_FROUND_Q): New. (MATCH_FROUNDNX_Q): New. (MASK_FROUNDNX_Q): New. (MATCH_FLTQ_Q): New. (MASK_FLTQ_Q): New. (MATCH_FLEQ_Q): New. (MASK_FLEQ_Q): New. (MATCH_FCVTMOD_W_D): New. (MASK_FCVTMOD_W_D): New. (MATCH_FMVH_X_D): New. (MASK_FMVH_X_D): New. (MATCH_FMVH_X_Q): New. (MASK_FMVH_X_Q): New. (MATCH_FMVP_D_X): New. (MASK_FMVP_D_X): New. (MATCH_FMVP_Q_X): New. (MASK_FMVP_Q_X): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction classes for the Zfa extension. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add support for new format string directive 'Wfv'. * riscv-opc.c: Add Zfa instructions. Co-Developed-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Co-Developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-30LoongArch: gas: Add LVZ and LBT instructions supportmengqinggang1-0/+6
gas/ChangeLog: * config/tc-loongarch.c (md_parse_option): Add LARCH_opts.ase_lvz and LARCH_opts.ase_lbt. * testsuite/gas/loongarch/uleb128.d: Regenerated. * testsuite/gas/loongarch/lvz-lbt.d: New test. * testsuite/gas/loongarch/lvz-lbt.s: New test. include/ChangeLog: * opcode/loongarch.h (ase_lvz): New. (ase_lbt): New. opcodes/ChangeLog: * loongarch-dis.c (set_default_loongarch_dis_options): Add LARCH_opts.ase_lvz and LARCH_opts.ase_lbt. * loongarch-opc.c (struct loongarch_ase): Add LVZ and LBT instructions.
2023-06-30LoongArch: Deprecate $v[01], $fv[01] and $x names per specWANG Xuerui1-2/+2
As outlined in the LoongArch ELF psABI spec [1], it is actually already 2 versions after the initial LoongArch support, and the $v[01] and $fv[01] names should really get sunset by now. In addition, the "$x" name for $r21 was never included in any released version of the ABI spec, and such usages are all fixed to say just $r21 for every project I could think of that accepted a LoongArch port. Plus, the upcoming LSX/LASX support makes use of registers named "$vrNN" and "$xrNN", so having "$vN" and "$x" alongside would almost certainly create confusion for developers. Issue warnings for such usages per the deprecation procedure detailed in the spec, so we can finally remove support in the next release cycle after this. [1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html gas/ChangeLog: * config/tc-loongarch.c: Init canonical register ABI name mappings and deprecated register names. (loongarch_args_parser_can_match_arg_helper): Warn in case of deprecated register name usage. * testsuite/gas/loongarch/deprecated_reg_aliases.d: New test. * testsuite/gas/loongarch/deprecated_reg_aliases.l: Likewise. * testsuite/gas/loongarch/deprecated_reg_aliases.s: Likewise. include/ChangeLog: * opcode/loongarch.h: Rename global variables. opcodes/ChangeLog: * loongarch-opc.c: Rename the alternate/deprecated register name mappings, and move $x to the deprecated name map. Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30opcodes/loongarch: remove unused codeWANG Xuerui1-5/+0
Remove some unused declarations and code. include/ChangeLog: * opcode/loongarch.h: Remove unused declarations. opcodes/ChangeLog: * loongarch-dis.c (loongarch_parse_dis_options): Remove. (my_print_address_func): Likewise. (loongarch_disassemble_one): Likewise. Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30LoongArch: support disassembling certain pseudo-instructionsWANG Xuerui1-0/+2
Add a flag in the pinfo field for being able to mark certain specialized matchers as disassembler-only, so some degree of isolation between assembler-side and disassembler-side can be achieved. This isolation is necessary, firstly because some pseudo-instructions cannot be fully described in the opcode table, like `li.[wd]`, so the corresponding opcode entry cannot have meaningful match/mask values. Secondly, some of these pseudo-instructions can be realized in more than one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie disassembly of such aliases with the corresponding GAS support, only one canonical form among the above would be recognized as `li.w`, and it would mildly impact the readability of disassembly output. People wanting the exact disassembly can always set `-M no-aliases` to get the original behavior back. In addition, in certain cases, information is irreversibly lost after assembling, so perfect round-trip would not be possible in such cases. For example, `li.w` and `li.d` of immediates within int32_t range produce the same code; in this patch, `addi.d rd, $zero, imm` is treated as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`, due to the expressible value range well within 32 bits. gas/ChangeLog: * config/tc-loongarch.c (get_loongarch_opcode): Ignore disassembler-only aliases. * testsuite/gas/loongarch/64_pcrel.d: Update test case. * testsuite/gas/loongarch/imm_ins.d: Likewise. * testsuite/gas/loongarch/imm_ins_32.d: Likewise. * testsuite/gas/loongarch/jmp_op.d: Likewise. * testsuite/gas/loongarch/li.d: Likewise. * testsuite/gas/loongarch/macro_op.d: Likewise. * testsuite/gas/loongarch/macro_op_32.d: Likewise. * testsuite/gas/loongarch/macro_op_large_abs.d: Likewise. * testsuite/gas/loongarch/macro_op_large_pc.d: Likewise. * testsuite/gas/loongarch/nop.d: Likewise. * testsuite/gas/loongarch/relax_align.d: Likewise. * testsuite/gas/loongarch/reloc.d: Likewise. include/ChangeLog: * opcode/loongarch.h (INSN_DIS_ALIAS): Add. ld/ChangeLog: * testsuite/ld-loongarch-elf/jmp_op.d: Update test case. * testsuite/ld-loongarch-elf/macro_op.d: Likewise. * testsuite/ld-loongarch-elf/macro_op_32.d: Likewise. * testsuite/ld-loongarch-elf/relax-align.dd: Likewise. opcodes/ChangeLog: * loongarch-dis.c: Move register name map declarations to top. (get_loongarch_opcode_by_binfmt): Consider aliases when disassembling without the no-aliases option. (parse_loongarch_dis_option): Support the no-aliases option. * loongarch-opc.c: Collect pseudo instructions into a new dedicated table. Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-29sframe: bfd: gas: ld: format bump to SFrame version 2Indu Bhagat2-1/+29
SFrame version 2 encodes the size of repetitive insn block explicitly in the format. Add information in the SFrame FDE to convey the size of the block of repeating instructions. This information is used only for SFrame FDEs of type SFRAME_FDE_TYPE_PCMASK. Introduce two extra bytes for padding: this ensures that the memory accesses to the members of the SFrame Frame Descriptor Entry (FDE) are naturally aligned. gas generates SFrame section with version SFRAME_VERSION_2 by default. libsframe provides two new APIs to: - get an SFrame FDE data from the decoder context, and - add an SFrame FDE to the encoder context. The additional argument (for rep_block_size) is useful for SFrame FDEs where FDE type is SFRAME_FDE_TYPE_PCMASK. The linker will generate the output SFrame sections in the SFRAME_VERSION_2 format. If the input sections offered to the linker are not all in the SFRAME_VERSION_2 format, the linker issues an error to the user. objdump/readelf will show the following message to the user if .sframe section in SFRAME_VERSION_1 format is seen: "No further information can be displayed. SFrame version not supported." In other words, like the rest of the binutils, only the current SFrame format version, i.e., SFRAME_VERSION_2 is supported by the textual dump facilities. bfd/ * elf-sframe.c (_bfd_elf_merge_section_sframe): Generate an output SFrame section with version SFRAME_VERSION_2. Also, error out if the SFrame sections do not all have SFRAME_VERSION_2. * elfxx-x86.c (_bfd_x86_elf_create_sframe_plt): Generate SFrame section for plt entries with version SFRAME_VERSION_2. gas/ * gen-sframe.c (sframe_set_version): Update to SFRAME_VERSION_2. (output_sframe): Likewise. gas/testsuite/ * gas/cfi-sframe/cfi-sframe-aarch64-1.d: Use SFRAME_VERSION_2. * gas/cfi-sframe/cfi-sframe-aarch64-2.d: Likewise. * gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-1.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-2.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-3.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-4.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-5.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-6.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-7.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-8.d: Likewise. * gas/cfi-sframe/cfi-sframe-x86_64-1.d: Likewise. * gas/cfi-sframe/common-empty-1.d: Likewise. * gas/cfi-sframe/common-empty-2.d: Likewise. * gas/cfi-sframe/common-empty-3.d: Likewise. ld/testsuite/ * ld-aarch64/sframe-simple-1.d: Adjust for SFRAME_VERSION_2. * ld-x86-64/sframe-plt-1.d: Likewise. * ld-x86-64/sframe-simple-1.d: Likewise. libsframe/ * libsframe.ver: Add the new APIs. * sframe.c (sframe_decoder_get_funcdesc_v2): New definition. (sframe_encoder_add_funcdesc_v2): Likewise. (sframe_header_sanity_check_p): Include SFRAME_VERSION_2. (sframe_fre_check_range_p): Get rep_block_size info from SFrame FDE. * sframe-dump.c (dump_sframe_header): Add support for SFRAME_VERSION_2. (dump_sframe): Inform user if SFrame section in SFRAME_VERSION_1 format is seen. libsframe/testsuite/ * libsframe.decode/DATA-BE: Regenerated data file. * libsframe.decode/DATA1: Likewise. * libsframe.decode/DATA2: Likewise. * libsframe.find/plt-findfre-1.c: Use new API in the testcase. include/ * sframe.h: Add member to encode size of the code block of repeating instructions. Add 2 bytes of padding. * sframe-api.h (sframe_decoder_get_funcdesc_v2): New declaration. (sframe_encoder_add_funcdesc_v2): Likewise.
2023-06-29libsframe: add new APIs to get SFrame versionIndu Bhagat1-0/+8
While the SFrame preamble is guaranteed to not change between versions, providing these access APIs from the SFrame decoder and encoder APIs is for convenience only. The linker may want to use these APIs as the format evolves. include/ * sframe-api.h (sframe_decoder_get_version): New declaration. (sframe_encoder_get_version): Likewise. libsframe/ * libsframe/libsframe.ver: Add new APIs. * libsframe/sframe.c (sframe_decoder_get_version): New definition. (sframe_encoder_get_version): Likewise.
2023-06-29libsframe: fix sframe_find_fre for pltN entriesIndu Bhagat1-2/+2
For a toy application on x86_64, for example, following is the SFrame stack trace information for the 3 pltN entries of 16 bytes each: func idx [1]: pc = 0x401030, size = 48 bytes STARTPC[m] CFA FP RA 0000000000000000 sp+8 u u 000000000000000b sp+16 u u The data in first column is the start_ip_offset. Also note that the FDE is of type SFRAME_FDE_TYPE_PCMASK (denoted by the [m] on LHS). Where each pltN (note: excluding plt0 entry) entry looks like: 401030: jmp *0x2fca(%rip) 401036: push $0x0 40103b: jmp 401020<_init+0x20> 401040: jmp *0x2fc2(%rip) 401046: push $0x1 40104b: jmp 401020<_init+0x20> 401050: jmp *0x2fba(%rip) 401056: push $0x2 40105b: jmp 401020<_init+0x20> Now, to find SFrame stack trace information from an FDE of type SFRAME_FDE_TYPE_PCMASK, sframe_find_fre () was doing an operation like, (start_ip_offset & 0xf) >= (pc & 0xf) This works for pltN entry of size, say, less than 16 bytes. But if the pltN entries or similar code stubs (for which SFrame FDE of type SFRAME_FDE_TYPE_PCMASK may be used), evolve to be of size > 16 bytes, this will cease to work. To match the range covered by the SFrame FRE, one should instead perform a modulo operation. The constant for the modulo operation must be the size of the pltN entry. Further, this constant should ideally be encoded in the format, as it may be different for each ABI. In SFrame Version 2 of the format, we will move towards encoding it explicitly in the SFrame FDE. For now, fix up the logic to at least move towards modulo operation. libsframe/ * sframe.c (sframe_fre_check_range_p): New definition. (sframe_find_fre): Refactor a bit and use the new definition above. include/ * sframe.h (SFRAME_FDE_TYPE_PCMASK): Update comment. libsframe/doc/ * sframe-spec.texi: Fix the text for SFRAME_FDE_TYPE_PCMASK FDE type.
2023-06-28LoongArch: Add R_LARCH_64_PCREL relocation supportmengqinggang1-0/+2
Gas defaults to emit R_LARCH_ADD64/R_LARCH_SUB64 unless explcitly declared to emit R_LARCH_64_PCREL. The LoongArch ABI at here: https://github.com/loongson/la-abi-specs/blob/release/la-abi.adoc bfd/ChangeLog: * bfd-in2.h (not): Add R_LARCH_64_PCREL * elfnn-loongarch.c (perform_relocation): Likewise. * elfxx-loongarch.c: Likewise. * libbfd.h: Likewise. * reloc.c: Likewise. gas/ChangeLog: * config/tc-loongarch.c (loongarch_args_parser_can_match_arg_helper): (md_apply_fix): Add R_LARCH_64_PCREL. * testsuite/gas/loongarch/64_pcrel.d: New test. * testsuite/gas/loongarch/64_pcrel.s: New test. include/ChangeLog: * elf/loongarch.h (RELOC_NUMBER): Add R_LARCH_64_PCREL. ld/ChangeLog: * testsuite/ld-loongarch-elf/ld-loongarch-elf.exp: Add test. * testsuite/ld-loongarch-elf/64_pcrel.d: New test. * testsuite/ld-loongarch-elf/64_pcrel.s: New test.
2023-06-27libsframe: bfd: use uint32_t for return type of get_num_fidx APIsIndu Bhagat1-2/+2
Keep the data types usage in libsframe look consistent. bfd/ * elf-sframe.c (_bfd_elf_merge_section_sframe): Use uint32_t type alias. * libsframe/sframe.c (sframe_decoder_get_funcdesc_at_index): Likewise. (sframe_decoder_get_num_fidx): Likewise. (sframe_encoder_get_num_fidx): Likewise. include/ * sframe-api.h (sframe_decoder_get_num_fidx): Likewise. (sframe_encoder_get_num_fidx): Likewise.
2023-06-27libsframe: use appropriate data types for args of sframe_encodeIndu Bhagat1-1/+1
include/ * sframe-api.h (sframe_encode): Use of uint8_t is more appropriate. libsframe/ * sframe.c (sframe_encode): Likewise.
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