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2024-01-04Update year range in copyright notice of binutils filesAlan Modra319-319/+319
2023-12-29LoongArch: include: Add support for tls le relax.changjiachen1-0/+12
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESCH.J. Lu1-0/+6
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTPCRELXH.J. Lu1-1/+5
2023-12-28x86: Add NT_X86_SHSTK noteSchimpe, Christina1-0/+3
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-0/+4
2023-12-25LoongArch: Add support for TLS LD/GD/DESC relaxationmengqinggang1-0/+4
2023-12-25LoongArch: Add tls transition support.Lulu Cai1-0/+6
2023-12-25LoongArch: Add new relocs and macro for TLSDESC.Lulu Cai1-1/+21
2023-12-20s390: Optionally print instruction description in disassemblyJens Remus1-1/+4
2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo1-0/+2
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo1-1/+4
2023-12-18LoongArch: Add new relocation R_LARCH_CALL36mengqinggang1-0/+2
2023-12-14RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.Jin Ma1-4/+4
2023-12-10Add some new DW_IDX_* constantsTom Tromey1-0/+9
2023-12-05Add basic support for RISC-V 64-bit EFI objectsAndreas Schwab2-0/+66
2023-12-04s390: Support for jump visualization in disassemblyJens Remus1-3/+22
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu2-0/+64
2023-12-01RISC-V: Zv*: Add support for Zvkb ISA extensionChristoph Müllner2-2/+3
2023-11-28libiberty, ld: Use x86 HW optimized sha1Jakub Jelinek2-0/+12
2023-11-24RISC-V: reduce redundancy in sign/zero extension macro insn handlingJan Beulich1-2/+1
2023-11-23RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extensionJin Ma1-0/+10
2023-11-23RISC-V: Add vector mask instructions for T-Head VECTOR vendor extensionJin Ma1-0/+14
2023-11-23RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...Jin Ma1-0/+36
2023-11-23RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...Jin Ma1-0/+12
2023-11-23RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extensionJin Ma1-0/+12
2023-11-23RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extensionJin Ma2-1/+37
2023-11-23RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extensionJin Ma1-0/+169
2023-11-23RISC-V: Add load/store instructions for T-Head VECTOR vendor extensionJin Ma1-0/+33
2023-11-23RISC-V: Add CSRs for T-Head VECTOR vendor extensionJin Ma1-0/+7
2023-11-23RISC-V: Add T-Head VECTOR vendor extension.Jin Ma1-0/+1
2023-11-16aarch64: Add support for VMSA feature enhancements.Srinath Parvathaneni1-1/+20
2023-11-16aarch64: Add new AT system instructions.Srinath Parvathaneni1-1/+4
2023-11-16aarch64: Add support to new features in RAS extension.Srinath Parvathaneni1-1/+13
2023-11-16aarch64: Add features to the Statistical Profiling Extension.Srinath Parvathaneni1-1/+10
2023-11-10bfd, binutils: add gfx11 amdgpu architecturesSimon Marchi2-0/+9
2023-11-10MIPS: Change all E_MIPS_* to EF_MIPS_*Ying Huang1-38/+81
2023-11-10Add ability to change linker warning messages into errors when reporting exec...Nick Clifton2-8/+37
2023-11-10Add support for ilp32 register alias.Lulu Cai1-4/+4
2023-11-07aarch64: Add arch support for LSE128 extensionVictor Do Nascimento1-0/+3
2023-11-07aarch64: Add LSE128 instruction operand supportVictor Do Nascimento1-0/+2
2023-11-07aarch64: Add THE system register supportVictor Do Nascimento1-0/+2
2023-11-07RISC-V: Add support for XCValu extension in CV32E40PMary Bennett2-0/+72
2023-11-07RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett2-0/+44
2023-11-06RISC-V: Moved out linker internal relocations after R_RISCV_max.Nelson Chu1-0/+8
2023-11-03RISC-V: reduce redundancy in load/store macro insn handlingJan Beulich1-19/+3
2023-11-02aarch64: Add support for GCSB DSYNC instruction.Srinath Parvathaneni1-0/+2
2023-11-02aarch64: Add support for GCS extension.srinath1-1/+3
2023-11-02aarch64: Add support for Check Feature Status Extension.Srinath Parvathaneni1-2/+5
2023-11-02aarch64: Add support for Armv8.9-A and Armv9.4-A Architectures.srinath1-1/+8
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