rocket-tools/riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-12-27	RISC-V: Fix T-Head Fmv vendor extension encoding	Christoph Müllner	1	-2/+2
2022-11-25	riscv: Add AIA extension support (Smaia, Ssaia)	Christoph Müllner	1	-0/+68
2022-11-19	RISC-V: Add 'Ssstateen' extension and its CSRs	Tsukasa OI	1	-13/+13
2022-11-17	RISC-V: Add T-Head Int vendor extension	Christoph Müllner	2	-0/+9
2022-11-17	RISC-V: Add T-Head Fmv vendor extension	Christoph Müllner	2	-0/+9
2022-11-14	aarch64: Add support for Common Short Sequence Compression extension	Andre Vieira	1	-1/+5
2022-10-27	PowerPC: Add support for RFC02653 - Dense Math Facility	Peter Bergner	1	-15/+18
2022-10-14	e200 LSP support	Alan Modra	1	-0/+5
2022-10-14	RISC-V: Move certain arrays to riscv-opc.c	Tsukasa OI	1	-11/+2
2022-10-04	RISC-V: Fix buffer overflow on print_insn_riscv	Tsukasa OI	1	-0/+2
2022-10-04	RISC-V: Renamed INSN_CLASS for floating point in integer extensions.	Nelson Chu	1	-7/+7
2022-10-04	RISC-V/gas: allow generating up to 176-bit instructions with .insn	Jan Beulich	1	-0/+3
2022-09-23	RISC-V: Add Zawrs ISA extension support	Christoph Müllner	2	-0/+9
2022-09-22	RISC-V: Add T-Head MemPair vendor extension	Christoph Müllner	2	-0/+18
2022-09-22	RISC-V: Add T-Head MemIdx vendor extension	Christoph Müllner	2	-0/+135
2022-09-22	RISC-V: Add T-Head FMemIdx vendor extension	Christoph Müllner	2	-0/+27
2022-09-22	RISC-V: Add T-Head MAC vendor extension	Christoph Müllner	2	-0/+21
2022-09-22	RISC-V: Add T-Head CondMov vendor extension	Christoph Müllner	2	-0/+9
2022-09-22	RISC-V: Add T-Head Bitmanip vendor extension	Christoph Müllner	2	-0/+42
2022-09-22	RISC-V: Add support for arbitrary immediate encoding formats	Christoph Müllner	1	-0/+17
2022-09-22	RISC-V: Add T-Head SYNC vendor extension	Christoph Müllner	2	-0/+18
2022-09-22	RISC-V: Add T-Head CMO vendor extension	Christoph Müllner	2	-0/+66
2022-09-12	ppc: Document the -mfuture and -Mfuture options and make them usable	Peter Bergner	1	-0/+3
2022-08-30	RISC-V: Add 'Zmmul' extension in assembler.	Tsukasa OI	1	-0/+1
2022-08-11	ppc/svp64: introduce non-zero operand flag	Dmitry Selyutin	1	-0/+5
2022-08-11	ppc/svp64: support LibreSOC architecture	Dmitry Selyutin	1	-0/+3
2022-07-29	libopcodes/aarch64: add support for disassembler styling	Andrew Burgess	1	-1/+27
2022-07-07	RISC-V: Added Zfhmin and Zhinxmin.	Tsukasa OI	1	-3/+4
2022-06-29	opcodes/aarch64: split off creation of comment text in disassembler	Andrew Burgess	1	-1/+1
2022-06-28	RISC-V: Add 'Sstc' extension and its CSRs	Tsukasa OI	1	-0/+10
2022-06-28	RISC-V: Add 'Sscofpmf' extension with its CSRs	Tsukasa OI	1	-0/+62
2022-06-28	RISC-V: Add 'Smstateen' extension and its CSRs	Tsukasa OI	1	-0/+42
2022-06-22	RISC-V: Use single h extension to control hypervisor CSRs and instructions.	Nelson Chu	2	-25/+26
2022-05-30	RISC-V: Add zhinx extension supports.	jiawei	1	-2/+3
2022-05-27	Remove use of bfd_uint64_t and similar	Alan Modra	2	-32/+32
2022-05-25	ppc: extend opindex to 16 bits	Dmitry Selyutin	1	-1/+7
2022-05-20	RISC-V: Remove RV128-only fmv instructions	Tsukasa OI	1	-6/+0
2022-05-18	AArch64: Enable FP16 by default for Armv9-A.	Tamar Christina	1	-0/+1
2022-05-17	RISC-V: Added half-precision floating-point v1.0 instructions.	Nelson Chu	2	-0/+77
2022-04-22	RISC-V: Add missing DECLARE_INSNs for Zicbo{m,p,z}	Christoph Muellner	1	-0/+9
2022-03-20	gas:LoongArch: Fix segment error in compilation due to too long symbol name.	liuzhensong	1	-2/+2
2022-03-18	RISC-V: Cache management instructions	Tsukasa OI	2	-0/+11
2022-03-18	RISC-V: Prefetch hint instructions and operand set	Tsukasa OI	2	-0/+8
2022-03-16	Delete PowerPC macro insn support	Alan Modra	1	-26/+0
2022-03-16	PowerPC64 extended instructions in powerpc_macros	Alan Modra	1	-3/+5
2022-02-23	RISC-V: Updated CSRs to privileged spec v1.12 and debug spec v1.0.	Nelson Chu	1	-34/+49
2022-02-23	RISC-V: Add Privileged Architecture 1.12 CSRs	Tsukasa OI	1	-0/+138
2022-01-02	Update year range in copyright notice of binutils files	Alan Modra	70	-70/+70
2021-12-24	RISC-V: Hypervisor ext: support Privileged Spec 1.12	Vineet Gupta	1	-0/+100
2021-12-24	RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests	Vineet Gupta	1	-20/+0