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AgeCommit message (Expand)AuthorFilesLines
2017-06-21[ARM] Rework Tag_CPU_arch build attribute value selectionThomas Preud'homme1-0/+4
2017-06-16Rewrite __start and __stop symbol handlingAlan Modra1-0/+8
2017-06-14Don't use print_insn_XXX in GDBYao Qi1-0/+8
2017-06-06ld: Allow section groups to be resolved as part of a relocatable linkAndrew Burgess1-0/+5
2017-06-01PPC64_OPT_LOCALENTRYAlan Modra1-0/+4
2017-05-31Fix MinGW compilation warnings due to environ.hEli Zaretskii1-0/+4
2017-05-30[ARC] Add arc-cpu.def with processor definitionsAnton Kolesov1-0/+4
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi1-0/+5
2017-05-24Refactor disassembler selectionYao Qi1-0/+4
2017-05-23[ARC] Update MAX_INSN_FLGS.claziss1-0/+4
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-0/+4
2017-05-19binutils: support for the SPARC M8 processorJose E. Marchesi1-0/+26
2017-05-16Rename non_ir_ref to non_ir_ref_regularAlan Modra1-0/+5
2017-05-16non_ir_ref_dynamicAlan Modra1-0/+5
2017-05-15MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki1-0/+10
2017-05-14Fix match and mask for 64-bit bb opcode.John David Anglin1-0/+4
2017-05-10[ARC] Object attributes.Claudiu Zissulescu1-0/+16
2017-04-20Handle symbol defined in IR and referenced in DSOH.J. Lu1-0/+5
2017-04-19Implement -z dynamic-undefined-weakAlan Modra1-0/+5
2017-04-11Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500Alan Modra1-0/+2
2017-04-11Bye bye PPC_OPCODE_HTM and -mhtmAlan Modra1-0/+1
2017-04-11Bye Bye PPC_OPCODE_VSX3Alan Modra1-0/+1
2017-04-11Bye bye PPC_OPCODE_ALTIVEC2Alan Modra1-0/+4
2017-04-06Add support for disassembling WebAssembly opcodes.Pip Cet1-0/+4
2017-04-05-Wwrite-strings: Constify struct disassemble_info's disassembler_options fieldPedro Alves1-0/+6
2017-04-04Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXXH.J. Lu1-0/+7
2017-04-04RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt1-0/+4
2017-03-31RISC-V: Add physical memory protection CSRsAndrew Waterman1-0/+43
2017-03-30Add support for the WebAssembly file format and the wasm32 ELF conversion to ...Pip Cet1-0/+5
2017-03-29PowerPC -Mraw disassemblyAlan Modra1-0/+5
2017-03-27Add minimal support for WebAssembly backend to the BFD library.Pip Cet1-0/+4
2017-03-27Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig1-0/+4
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel1-0/+5
2017-03-21arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig1-0/+4
2017-03-16Add support for a GNU BUILD note type to record the enum size.Nick Clifton1-0/+5
2017-03-14Add DW_OP_GNU_variable_valueH.J. Lu1-0/+5
2017-03-13Sync libiberty sources with GCC.Nick Clifton1-0/+9
2017-03-13Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AA...Nick Clifton1-0/+8
2017-03-10Add basic recognition of new EM_ ELF machine numbers.Nick Clifton1-0/+8
2017-03-08Properly dump NT_GNU_PROPERTY_TYPE_0H.J. Lu1-0/+8
2017-03-01Add support for displaying and merging GNU_BUILD_NOTEs.Nick Clifton1-0/+42
2017-02-28GDB: Add support for the new set/show disassembler-options commands.Peter Bergner1-0/+16
2017-02-28PowerPC addpcis fixAlan Modra1-0/+5
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-0/+7
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford1-0/+5
2017-02-24Add new counter-enable CSRsAndrew Waterman1-0/+7
2017-02-15Add SFENCE.VMA instructionAndrew Waterman1-0/+6
2017-02-14PowerPC register expression checksAlan Modra1-0/+6
2017-01-25Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov1-0/+9
2017-01-25Fix include/ChangeLog entry formatPedro Alves1-1/+1
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