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2023-12-11LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">mengqinggang2-0/+15
2023-12-11RISC-V/gas: Clarify the definition of `relaxable' in md_apply_fixNelson Chu1-1/+1
2023-12-01gas: drop unused fields from struct segment_info_structJan Beulich2-12/+1
2023-12-01x86: adjust NOP generation after potential non-insnJan Beulich2-1/+13
2023-12-01x86: i386_cons_align() badly affects diagnosticsJan Beulich3-20/+3
2023-12-01gas: no md_cons_align() for .nop{,s}Jan Beulich4-9/+17
2023-12-01x86: suppress optimization after potential non-insnJan Beulich1-0/+5
2023-12-01x86: last-insn recording should be per-sectionJan Beulich6-58/+116
2023-12-01x86: allow 32-bit reg to be used with U{RD,WR}MSRJan Beulich1-4/+4
2023-12-01RISC-V: Update gas/NEWS for RISC-V vendor extension news.Nelson Chu1-1/+3
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu5-0/+147
2023-12-01RISC-V: Zv*: Add support for Zvkb ISA extensionChristoph Müllner6-58/+48
2023-11-30MIPS/GAS: Add -march=loongson2f to loongson-2f-3 testYunQiang Su1-1/+1
2023-11-30MIPS: Set r6 as default arch if vendor is imgYunQiang Su4-2/+14
2023-11-30gas: support double-slash line comments in BPF assemblyJose E. Marchesi9-2/+57
2023-11-28gas: add NEWS entry for change of comment syntax in BPF assemblerJose E. Marchesi2-0/+9
2023-11-28gas: change meaning of ; in the BPF assemblerJose E. Marchesi12-35/+57
2023-11-28testsuite: Clean up .allow_index_reg in i386 testsHaochen Jiang234-574/+350
2023-11-28testsuite: Clean up #as in dump file for i386 testsHaochen Jiang262-262/+0
2023-11-27as: Add new estimated reciprocal instructions in LoongArch v1.1Jiajie Chen4-0/+24
2023-11-27as: Add new atomic instructions in LoongArch v1.1Jiajie Chen3-2/+88
2023-11-24x86: shrink opcode sets tableJan Beulich2-130/+130
2023-11-24x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possibleJan Beulich3-13/+62
2023-11-24RISC-V: reduce redundancy in sign/zero extension macro insn handlingJan Beulich1-16/+5
2023-11-24RISC-V: disallow x0 with certain macro-insnsJan Beulich2-3/+6
2023-11-23s390: Add missing extended mnemonicsJens Remus13-7/+68
2023-11-23s390: Align optional operand definition to specsJens Remus6-10/+27
2023-11-23s390: Add brasl edge test cases from ESA to z/ArchitectureJens Remus2-0/+12
2023-11-23s390: Position independent verification of relative addressingJens Remus6-237/+237
2023-11-23MIPS/GAS: Use addiu instead of addi in test elf-rel.YunQiang Su4-30/+36
2023-11-23MIPS/GAS: Fix test failures due to jr encoding changes on r6YunQiang Su6-5/+14
2023-11-23RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extensionJin Ma2-0/+68
2023-11-23RISC-V: Add vector mask instructions for T-Head VECTOR vendor extensionJin Ma2-0/+56
2023-11-23RISC-V: Add reductions instructions for T-Head VECTOR vendor extensionJin Ma2-0/+68
2023-11-23RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...Jin Ma2-0/+358
2023-11-23RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...Jin Ma2-0/+178
2023-11-23RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extensionJin Ma2-0/+657
2023-11-23RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extensionJin Ma3-0/+161
2023-11-23RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extensionJin Ma2-0/+1708
2023-11-23RISC-V: Add load/store instructions for T-Head VECTOR vendor extensionJin Ma2-0/+268
2023-11-23RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor exten...Jin Ma2-0/+15
2023-11-23RISC-V: Add CSRs for T-Head VECTOR vendor extensionJin Ma5-0/+57
2023-11-23RISC-V: Add T-Head VECTOR vendor extension.Jin Ma5-0/+13
2023-11-22LoongArch: fix internal error when as handling unsupported modifier.Lulu Cai4-1/+13
2023-11-21bpf: Fixed register parsing disambiguating with possible symbol.Cupertino Miranda2-0/+7
2023-11-18gas: bpf: do not allow referring to register names as symbols in operandsJose E. Marchesi7-49/+102
2023-11-17bpf: avoid creating wrong symbols while parsingDavid Faust5-0/+107
2023-11-17x86: improve a few diagnosticsJan Beulich9-84/+93
2023-11-17x86: don't allow pseudo-prefixes to be overridden by legacy suffixesJan Beulich1-3/+19
2023-11-17x86: CPU-qualify {disp16} / {disp32}Jan Beulich5-19/+68