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This commit adds the AIA extensions (Smaia and Ssaia) CSRs.
bfd/ChangeLog:
* elfxx-riscv.c: Add 'smaia' and 'ssaia' to the list
of known standard extensions.
gas/ChangeLog:
* config/tc-riscv.c (enum riscv_csr_class):
(riscv_csr_address): Add CSR classes for Smaia/Ssaia.
* testsuite/gas/riscv/csr-dw-regnums.d: Add new CSRs.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/csr.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (CSR_MISELECT): New CSR macro.
(CSR_MIREG): Likewise.
(CSR_MTOPEI): Likewise.
(CSR_MTOPI): Likewise.
(CSR_MVIEN): Likewise.
(CSR_MVIP): Likewise.
(CSR_MIDELEGH): Likewise.
(CSR_MIEH): Likewise.
(CSR_MVIENH): Likewise.
(CSR_MVIPH): Likewise.
(CSR_MIPH): Likewise.
(CSR_SISELECT): Likewise.
(CSR_SIREG): Likewise.
(CSR_STOPEI): Likewise.
(CSR_STOPI): Likewise.
(CSR_SIEH): Likewise.
(CSR_SIPH): Likewise.
(CSR_HVIEN): Likewise.
(CSR_HVICTL): Likewise.
(CSR_HVIPRIO1): Likewise.
(CSR_HVIPRIO2): Likewise.
(CSR_VSISELECT): Likewise.
(CSR_VSIREG): Likewise.
(CSR_VSTOPEI): Likewise.
(CSR_VSTOPI): Likewise.
(CSR_HIDELEGH): Likewise.
(CSR_HVIENH): Likewise.
(CSR_HVIPH): Likewise.
(CSR_HVIPRIO1H): Likewise.
(CSR_HVIPRIO2H): Likewise.
(CSR_VSIEH): Likewise.
(CSR_VSIPH): Likewise.
(DECLARE_CSR): Add CSRs for Smaia and Ssaia.
Changes for v3:
- Imply ssaia for smaia
- Imply zicsr for ssaia (and transitively smaia)
- Move hypervisor CSRs to Ssaia+H
- Rebase on upstream/master
Changes for v2:
- Add hypervisor and VS CSRs
- Fix whitespace issue
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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acinclude.m4 to stop a potwntial configure time warning message.
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First of all make operand_type_register_match() apply to all sized
operands, i.e. in Intel Syntax also to respective memory ones. This
addresses gas wrongly accepting certain SIMD insns where register and
memory operand sizes should match but don't. This apparently has
affected all templates with one memory-only operand and one or more
register ones, both permitting at least two sizes, due to CheckRegSize
not taking effect.
Then also add CheckRegSize to a couple of non-SIMD templates matching
that same pattern of memory-only vs register operands. This replaces
bogus (for Intel Syntax) diagnostics referring to a wrong suffix (when
none was used at all) by "type mismatch" ones, just like already emitted
for insns where the template allows a register operand alongside a
memory one at any particular position.
This also is a prereq to limiting (ideally eliminating in the long run)
suffix "derivation" in Intel Syntax mode.
While making the code adjustment also flip order of checks to do the
cheaper one first in both cases.
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Both uniformly only ever take 16-bit memory operands while at the same
time requiring matching (in size) register operands, which then also
should disassemble that way. This in particular requires splitting each
of the templates for the assembler and separating decode of the
register and memory forms in the disassembler.
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Once again: Old enough glibc has an (unguarded) declaration of index()
in string.h, which triggers a "shadows a global declaration" warning
with our choice of wanring level and with at least some gcc versions.
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PR 29764
gas * testsuite/gas/arm/cpu-cortex-a76ae.d: Add arm prefix to the -m
option passed to objdump.
* testsuite/gas/arm/cpu-cortex-a77.d: Likewise.
* testsuite/gas/aarch64/cpu-cortex-a76ae.d: Add aarch64 prefix to
the -m option passed to objdump.
* testsuite/gas/aarch64/cpu-cortex-a77.d: Likewise.
bfd * cpu-arm.c (scan): Accept machine names prefixed with "arm:".
* cpu-aarch64.c (scan): Accept machine names prefixed with "aarch64:".
bin * doc/binutils.texi (objdump): Note that the -m option supports
the <architecture>:<machine> syntax.
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This commit adds 'Ssstateen' extension, which is a supervisor-visible view
of the 'Smstateen' extension. It means, this extension implements sstateen*
and hstateen* CSRs of the 'Smstateen' extension.
Note that 'Smstateen' extension itself is unchanged but due to
implementation simplicity, it is implemented so that 'Smstateen' implies
'Ssstateen' (just like 'M' implies 'Zmmul').
This is based on the latest version of RISC-V Profiles
(version 0.9-draft, Frozen):
<https://github.com/riscv/riscv-profiles/commit/226b7f643067b29abc6723fac60d5f6d3f9eb901>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Update implication rules.
(riscv_supported_std_s_ext) Add 'Ssstateen' extension.
gas/ChangeLog:
* config/tc-riscv.c (enum riscv_csr_class): Rename
CSR_CLASS_SMSTATEEN_AND_H{,_32} to CSR_CLASS_SSSTATEEN_...
Add CSR_CLASS_SSSTATEEN.
(riscv_csr_address): Support new/renamed CSR classes.
* testsuite/gas/riscv/csr.s: Add 'Ssstateen' extension to comment.
* testsuite/gas/riscv/csr-version-1p9p1.l: Reflect changes to
error messages.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/ssstateen-csr.s: Test for 'Ssstateen' CSRs.
* testsuite/gas/riscv/ssstateen-csr.d: Likewise.
* testsuite/gas/riscv/smstateen-csr-s.d: Test to make sure that
supervisor/hypervisor part of 'Smstateen' CSRs are accessible from
'RV32IH_Smstateen', not just from 'RV32IH_Ssstateen' that is tested
in ssstateen-csr.d.
include/ChangeLog:
* opcode/riscv-opc.h: Update DECLARE_CSR declarations with
new CSR classes.
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Fixes issue where various values of '.align' causes writing of COFF files to fail.
Specific to the aarch64-pe target.
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SFrame is supported for ELF only. Keep the definitions and declarations
guarded with OBJ_ELF consistently.
ChangeLog:
* gas/config/tc-aarch64.h: Guard SFrame related definitions
with OBJ_ELF.
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gas/
* config/tc-i386.c (i386_seg_prefixes): New. Moved from opcodes.
opcodes/
* i386-opc.c (i386_seg_prefixes): Removed.
* i386-opc.h (i386_seg_prefixes): Likewise.
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This patch adds the XTheadInt extension, which provides interrupt
stack management instructions.
The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.
The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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ChangeLog:
* gas/NEWS: Add SFrame related news.
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Earlier these tests were in the same commit as previous which adds the
support in GNU assembler to generate .sframe section from CFI
directives. Splitting this out here for ease of applying and testing.
ChangeLog:
* gas/testsuite/gas/cfi-sframe/cfi-sframe-aarch64-1.d: New file.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-aarch64-1.s: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-1.d: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-1.s: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-2.d: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-2.s: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-3.d: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-3.s: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-4.d: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-4.s: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-5.d: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-5.s: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-6.d: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-6.s: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-7.d: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-7.s: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-8.d: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-common-8.s: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-x86_64-1.d: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe-x86_64-1.s: Likewise.
* gas/testsuite/gas/cfi-sframe/cfi-sframe.exp: Likewise.
* gas/testsuite/gas/cfi-sframe/common-empty-1.d: Likewise.
* gas/testsuite/gas/cfi-sframe/common-empty-1.s: Likewise.
* gas/testsuite/gas/cfi-sframe/common-empty-2.d: Likewise.
* gas/testsuite/gas/cfi-sframe/common-empty-2.s: Likewise.
* gas/testsuite/gas/cfi-sframe/common-empty-3.d: Likewise.
* gas/testsuite/gas/cfi-sframe/common-empty-3.s: Likewise.
* gas/testsuite/gas/cfi-sframe/common-empty-4.d: Likewise.
* gas/testsuite/gas/cfi-sframe/common-empty-4.s: Likewise.
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Currently supported for x86_64 and aarch64 only.
[PS: Currently, the compiler has not been adapted to generate
".cfi_sections" with ".sframe" in it. The newly added command line
option of --gsframe provides an easy way to try out .sframe support
in the toolchain.]
gas interprets the CFI directives to generate DWARF-based .eh_frame
info. These internal DWARF structures are now consumed by
gen-sframe.[ch] sub-system to, in turn, create the SFrame unwind
information. These internal DWARF structures are read-only for the
purpose of SFrame unwind info generation.
SFrame unwind info generation does not impact .eh_frame unwind info
generation. Both .eh_frame and .sframe can co-exist in an ELF file,
if so desired by the user.
Recall that SFrame unwind information only contains the minimal
necessary information to generate backtraces and does not provide
information to recover all callee-saved registers. The reason being
that callee-saved registers other than FP are not needed for stack
unwinding, and hence are not included in the .sframe section.
Consequently, gen-sframe.[ch] only needs to interpret a subset of
DWARF opcodes in gas. More details follow.
[Set 1, Interpreted] The following opcodes are interpreted:
- DW_CFA_advance_loc
- DW_CFA_def_cfa
- DW_CFA_def_cfa_register
- DW_CFA_def_cfa_offset
- DW_CFA_offset
- DW_CFA_remember_state
- DW_CFA_restore_state
- DW_CFA_restore
[Set 2, Bypassed] The following opcodes are acknowledged but are not
necessary for generating SFrame unwind info:
- DW_CFA_undefined
- DW_CFA_same_value
Anything else apart from the two above-mentioned sets is skipped
altogether. This means that any function containing a CFI directive not
in Set 1 or Set 2 above, will not have any SFrame unwind information
generated for them. Holes in instructions covered by FREs of a single
FDE are not representable in the SFrame unwind format.
As few examples, following opcodes are not processed for .sframe
generation, and are skipped:
- .cfi_personality*
- .cfi_*lsda
- .cfi_escape
- .cfi_negate_ra_state
- ...
Not processing .cfi_escape, .cfi_negate_ra_state will cause SFrame
unwind information to be absent for SFrame FDEs that contain these CFI
directives, hence affecting the asynchronicity.
x86-64 and aarch64 backends need to have a few new definitions and
functions for .sframe generation. These provide gas with architecture
specific information like the SP/FP/RA register numbers and an
SFrame-specific ABI marker.
Lastly, the patch also implements an optimization for size, where
specific fragments containing SFrame FRE start address and SFrame FDE
function are fixed up. This is similar to other similar optimizations
in gas, where fragments are sized and fixed up when the associated
symbols can be resolved. This optimization is controlled by a #define
SFRAME_FRE_TYPE_SELECTION_OPT and should be easy to turn off if needed.
The optimization is on by default for both x86_64 and aarch64.
ChangeLog:
* gas/Makefile.am: Include gen-sframe.c and sframe-opt.c.
* gas/Makefile.in: Regenerated.
* gas/as.h (enum _relax_state): Add new state rs_sframe.
(sframe_estimate_size_before_relax): New function.
(sframe_relax_frag): Likewise.
(sframe_convert_frag): Likewise.
* gas/config/tc-aarch64.c (aarch64_support_sframe_p): New
definition.
(aarch64_sframe_ra_tracking_p): Likewise.
(aarch64_sframe_cfa_ra_offset): Likewise.
(aarch64_sframe_get_abi_arch): Likewise.
(md_begin): Set values of sp/fp/ra registers.
* gas/config/tc-aarch64.h (aarch64_support_sframe_p): New
declaration.
(support_sframe_p): Likewise.
(SFRAME_CFA_SP_REG): Likewise.
(SFRAME_CFA_FP_REG): Likewise.
(SFRAME_CFA_RA_REG): Likewise.
(aarch64_sframe_ra_tracking_p): Likewise.
(sframe_ra_tracking_p): Likewise.
(aarch64_sframe_cfa_ra_offset): Likewise.
(sframe_cfa_ra_offset): Likewise.
(aarch64_sframe_get_abi_arch): Likewise.
(sframe_get_abi_arch): Likewise.
* gas/config/tc-i386.c (x86_support_sframe_p): New definition.
(x86_sframe_ra_tracking_p): Likewise.
(x86_sframe_cfa_ra_offset): Likewise.
(x86_sframe_get_abi_arch): Likewise.
* gas/config/tc-i386.h (x86_support_sframe_p): New declaration.
(support_sframe_p): Likewise.
(SFRAME_CFA_SP_REG): Likewise.
(SFRAME_CFA_FP_REG): Likewise.
(x86_sframe_ra_tracking_p): Likewise.
(sframe_ra_tracking_p): Likewise.
(x86_sframe_cfa_ra_offset): Likewise.
(sframe_cfa_ra_offset): Likewise.
(x86_sframe_get_abi_arch): Likewise.
(sframe_get_abi_arch): Likewise.
* gas/config/tc-xtensa.c (unrelaxed_frag_max_size): Add case for
rs_sframe.
* gas/doc/as.texi: Add .sframe to the documentation for
.cfi_sections.
* gas/dw2gencfi.c (cfi_finish): Create a .sframe section.
* gas/dw2gencfi.h (CFI_EMIT_sframe): New definition.
* gas/write.c (cvt_frag_to_fill): Handle rs_sframe.
(relax_segment): Likewise.
* gas/gen-sframe.c: New file.
* gas/gen-sframe.h: New file.
* gas/sframe-opt.c: New file.
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When --gsframe is specified, the assembler will generate a .sframe
section from the CFI directives in the assembly.
ChangeLog:
* gas/as.c (parse_args): Parse args and set flag_gen_sframe.
* gas/as.h: Introduce skeleton for --gsframe.
* gas/doc/as.texi: document --gsframe.
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* testsuite/gas/arm/ehabi-pacbti-m.d: Limit test to ELF.
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Without commit b66e671854, this:
.p2align 4
nop
.p2align 3
nop
results in an error when coff_frob_section attempts to pad out the
section to a 16-byte boundary. Due to miscalculating the pad pattern
repeat count, write.c:write_contents attempts to shove 16 bytes of
padding into the remaining 4 bytes of the .text section.
* config/obj-coff.c (coff_frob_section): Correct fill count.
Don't pad after errors.
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2022-09-28 Tejas Joshi <TejasSanjay.Joshi@amd.com>
gas/
* config/tc-i386.c (cpu_arch): Add znver4 ARCH and rmpquery SUBARCH.
(md_assemble): Expand comment before swap_operands() with rmpquery.
* doc/c-i386.texi: Add znver4.
* testsuite/gas/i386/arch-14-1.d: New.
* testsuite/gas/i386/arch-14-1.s: New.
* testsuite/gas/i386/arch-14-znver4.d: New.
* testsuite/gas/i386/i386.exp: Add new znver4 test cases.
* testsuite/gas/i386/rmpquery.d: New.
* testsuite/gas/i386/rmpquery.s: New.
* testsuite/gas/i386/x86-64-arch-4-1.d: New.
* testsuite/gas/i386/x86-64-arch-4-1.s: New.
* testsuite/gas/i386/x86-64-arch-4-znver4.d: New.
opcodes/
* i386-dis.c (x86_64_table): Add rmpquery.
* i386-gen.c (cpu_flag_init): Add CPU_ZNVER4_FLAGS and
CPU_RMPQUERY_FLAGS.
(cpu_flags): Add CpuRMPQUERY.
* i386-opc.h (enum): Add CpuRMPQUERY.
(i386_cpu_flags): Add cpurmpquery.
* i386-opc.tbl: Add rmpquery insn.
* i386-init.h: Re-generated.
* i386-tbl.h: Re-generated.
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Fixed wrong paste in cssc.d.
gas/ChangeLog:
* testsuite/gas/aarch64/cssc.d: Removed duplicate head.
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This patch adds support for the CSSC extension and its corresponding
instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN.
gas/ChangeLog:
* config/tc-aarch64.c (parse_operands): Handle new operand types.
* doc/c-aarch64.texi: Document new extension.
* testsuite/gas/aarch64/cssc.d: New test.
* testsuite/gas/aarch64/cssc.s: New test.
include/ChangeLog:
* opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro.
(enum aarch64_opnd): New operand types.
(enum aarch64_insn_class): New instruction class.
opcodes/ChangeLog:
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (operand_general_constraint_met_p): Update for new
operand types.
(aarch64_print_operand): Likewise.
* aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field.
* aarch64-tbl.h (aarch64_feature_cssc): Define new feature set.
(CSSC): Define new feature set Macro.
(CSSC_INSN): Define new instruction type.
(aarch64_opcode_table): Add new instructions.
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Attributes which aren't used together in any single insn template can be
converted from individual booleans to a single enum, as was done for a few
other attributes before. This is more space efficient. Collect together
all attributes which express special operand constraints (and which fit
the criteria for folding).
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This patch adds the assembler support for the new unwinder
directive ".pacspval" and encodes this directives with opcode
"0xb5". This opcode indicates the unwinder to use effective
vsp as modifier for PAC validation.
gas/ChangeLog:
2022-11-07 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* doc/c-arm.texi: Document directive.
* config/tc-arm.c (s_arm_unwind_pacspval): Define function.
(md_pseudo_table): Add entry for pacspval directive.
* testsuite/gas/arm/ehabi-pacbti-m.d: New test.
* testsuite/gas/arm/ehabi-pacbti-m.s: Likewise.
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This patch adds support for Cortex-X1C CPU in Arm.
bfd/ChangeLog:
2022-11-09 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* cpu-arm.c (processors): Add Cortex-X1C CPU entry.
gas/ChangeLog:
2022-11-09 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* NEWS: Update docs.
* config/tc-arm.c (arm_cpus): Add cortex-x1c to -mcpu.
* doc/c-arm.texi: Update docs.
* testsuite/gas/arm/cpu-cortex-x1c.d: New test.
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This tidies SEC_RELOC handling in bfd, in the process fixing a bug
with objcopy when renaming sections.
bfd/
* reloc.c (_bfd_generic_set_reloc): Set/clear SEC_RELOC depending
on reloc count.
* elf64-sparc.c (elf64_sparc_set_reloc): Likewise.
binutils/
* objcopy.c (copy_relocations_in_section): Remove now unnecessary
clearing of SEC_RELOC.
* testsuite/binutils-all/rename-section-01.d: New test.
* testsuite/binutils-all/objcopy.exp: Run it.
gas/
* write.c (size_seg): Remove unneccesary twiddle of SEC_RELOC.
(write_relocs): Likewise. Always call bfd_set_reloc.
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On a testcase like
pla 8,foo@pcrel
disassembled with -Mpower10 results in
0: 00 00 10 06 pla r8,0 # 0
4: 00 00 00 39
0: R_PPC64_PCREL34 foo
but with -Mpower10 -Mraw
0: 00 00 10 06 .long 0x6100000
0: R_PPC64_PCREL34 foo
4: 00 00 00 39 addi r8,0,0
The instruction is unrecognised due to the hack we have in
extract_pcrel0 in order to disassemble paddi with RA0=0 and R=1 as
pla. I could have just added "&& !(dialect & PPC_OPCODE_RAW)" to the
condition in extract_pcrel0 under which *invalid is set, but went for
this larger patch that reorders the extended insn pla to the more
usual place before its underlying machine insn. (la is after addi
because we never disassemble to la.)
gas/
* testsuite/gas/ppc/raw.d,
* testsuite/gas/ppc/raw.s: Add pla.
opcodes/
* ppc-opc.c (extract_pcrel1): Rename from extract_pcrel0 and
invert *invalid logic.
(PCREL1): Rename from PCREL0.
(prefix_opcodes): Sort pla before paddi, adjusting R operand
for pla, paddi and psubi.
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While .linefile is generally intended for gas internal use only, its use
in a source file would better not result in an internal error. Give use
of it outside of any macro(-like) construct the meaning of restoring the
original (physical) input file name.
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The need for IsString on the PadLock insns went away with the
introduction of RepPrefixOk. Drop these leftovers.
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Of the two instances the first is correct in using ANY_SSE4A as 3rd
argument to SUBARCH(), so drop the wrong/redundant/dead 2nd one.
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(%dx) isn't a valid memory address in any modes. It is used as a special
memory operand for input/output port address in AT&T syntax and should
only be used with input/output instructions. Update i386_att_operand to
set i.input_output_operand to true for (%dx) and issue an error if (%dx)
is used with non-input/output instructions.
PR gas/29751
* config/tc-i386.c (_i386_insn): Add input_output_operand.
(md_assemble): Issue an error if input/output memory operand is
used with non-input/output instructions.
(i386_att_operand): Set i.input_output_operand to true for
(%dx).
* testsuite/gas/i386/inval.l: Updated.
* testsuite/gas/i386/x86-64-inval.l: Likewise.
* testsuite/gas/i386/inval.s: Add tests for invalid (%dx) usage.
* testsuite/gas/i386/x86-64-inval.s: Likewise.
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Operand swapping was mistakenly suppressed when the first two operands
were immediate ones, not taking into account overall operand count. This
way EXTRQ / INSERTQ would have been accepted also with kind-of-AT&T
operand order.
For the testcase being extended, in order to not move around "GAS
LISTING" expectations, suppress pagination.
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Although the encoding for scalar and fp registers is identical,
we should follow common pratice and use fp register names
when referencing fp registers.
The xtheadmemidx extension consists of indirect load/store instructions
which all load to or store from fp registers.
Let's use fp register names in this case and adjust the test cases
accordingly.
gas/
* testsuite/gas/riscv/x-thead-fmemidx-fail.l: Updated since rd need to
be float register.
* testsuite/gas/riscv/x-thead-fmemidx-fail.s: Likewise.
* testsuite/gas/riscv/x-thead-fmemidx.d: Likewise.
* testsuite/gas/riscv/x-thead-fmemidx.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Updated since rd need to be float register.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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gas/ChangeLog:
* NEWS: Support Intel RAO-INT.
* config/tc-i386.c: Add raoint.
* doc/c-i386.texi: Document .raoint.
* testsuite/gas/i386/i386.exp: Run RAO_INT tests.
* testsuite/gas/i386/raoint-intel.d: New test.
* testsuite/gas/i386/raoint.d: Ditto.
* testsuite/gas/i386/raoint.s: Ditto.
* testsuite/gas/i386/x86-64-raoint-intel.d: Ditto.
* testsuite/gas/i386/x86-64-raoint.d: Ditto.
* testsuite/gas/i386/x86-64-raoint.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_0F38FC): New.
(prefix_table): Add PREFIX_0F38FC.
* i386-gen.c: (cpu_flag_init): Add CPU_RAO_INT_FLAGS and
CPU_ANY_RAO_INT_FLAGS.
* i386-init.h: Regenerated.
* i386-opc.h: (CpuRAO_INT): New.
(i386_cpu_flags): Add cpuraoint.
* i386-opc.tbl: Add RAO_INT instructions.
* i386-tbl.h: Regenerated.
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gas uses ZSTD_compressStream2 which is only available with libzstd >=
1.4.0, leading to build errors when an older version is installed.
This patch updates the check libzstd presence to check its version is
>= 1.4.0. However, since gas seems to be the only component requiring
such a recent version this may imply that we disable ZSTD support for
all components although some would still benefit from an older
version.
I ran 'autoreconf -f' in all directories containing a configure.ac
file, using vanilla autoconf-2.69 and automake-1.15.1. I noticed
several errors from autoheader in readline, as well as warnings in
intl, but they are unrelated to this patch.
This should fix some of the buildbots.
OK for trunk?
Thanks,
Christophe
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Despite that the RISC-V ISA Manual version 2.2 prohibited "RV32EF", later
versions beginning with the version 20190608-Base-Ratified removed this
restriction. Because the 'E' extension is still a draft, the author chose
to *just* remove the conflict (not checking the ISA version).
Note that, because RV32E is only used with a soft-float calling convention,
there's no valid official ABI for RV32EF. It means, even if we can assemble
a program with -march=rv32ef -mabi=ilp32e, floating-point registers are kept
in an unmanaged state (outside ABI management).
The purpose of this commit is to suppress unnecessary errors while parsing
an ISA string and/or disassembling, not to allow hard-float with RVE.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Accept RV32EF
because only older specifications disallowed it.
gas/ChangeLog:
* testsuite/gas/riscv/march-fail-rv32ef.d: Remove as not directly
prohibited.
* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
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The issue addressed by 2c02c72c62d2 ("re: Support Intel AMX-FP16") has
been introduced once again in a number of new tests.
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gas/ChangeLog:
* NEWS: Support Intel AVX-NE-CONVERT.
* config/tc-i386.c: Add avx_ne_convert.
* doc/c-i386.texi: Document .avx_ne_convert.
* testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests.
* testsuite/gas/i386/avx-ne-convert-intel.d: New test.
* testsuite/gas/i386/avx-ne-convert.d: Ditto.
* testsuite/gas/i386/avx-ne-convert.s: Ditto.
* testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto.
* testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (Mw): New.
(PREFIX_VEX_0F3872): Ditto.
(PREFIX_VEX_0F38B0_W_0): Ditto.
(PREFIX_VEX_0F38B1_W_0): Ditto.
(VEX_W_0F3872_P_1): Ditto.
(VEX_W_0F38B0): Ditto.
(VEX_W_0F38B1): Ditto.
(prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0_W_0,
PREFIX_VEX_0F38B1_W_0.
(vex_w_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0, VEX_W_0F38B1.
* i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and
CPU_ANY_AVX_NE_CONVERT_FLAGS.
(cpu_flags): Add CpuAVX_NE_CONVERT.
* i386-init.h: Regenerated.
* i386-opc.h (CpuAVX_NE CONVERT): New.
(i386_cpu_flags): Add cpuavx_ne_convert.
* i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions.
* i386-tbl.h: Regenerated.
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This patch is based on MULTIPLE_FRAME_SECTIONS and EH_FRAME_LINKONCE,
it allows backend to enable this feature and use '--gc-sections' simply.
* gas/dw2gencfi.h (TARGET_MULTIPLE_EH_FRAME_SECTIONS): New.
(MULTIPLE_FRAME_SECTIONS): Add TARGET_MULTIPLE_EH_FRAME_SECTIONS.
* gas/dw2gencfi.c (EH_FRAME_LINKONCE): Add TARGET_MULTIPLE_EH_FRAME_SECTIONS.
(is_now_linkonce_segment): Likewise.
(get_cfi_seg): Create relocation info between .eh_frame.* and .text.* section.
* bfd/elf-bfd.h (elf_backend_can_make_multiple_eh_frame): New.
* bfd/elfxx-target.h (elf_backend_can_make_multiple_eh_frame): Likewise.
* bfd/elflink.c (_bfd_elf_default_action_discarded): Add checking for
elf_backend_can_make_multiple_eh_frame.
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* gas/doc/internals.texi (md_emit_single_noop_insn):
fix '@var missing closing brace'
* gas/doc/internals.texi (Hash tables):
fix '@menu reference to nonexistent node `Hash tables''
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Comparing the sum of the relevant .imm<N> fields against a constant imo
makes more obvious what is actually meant. It allows dropping of two
static variables, with a 3rd drop requiring two more minor adjustments
elsewhere, utilizing that "i" is zeroed first thing in md_assemble().
This also increases the chances of the compiler doing the calculations
all in registers.
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Consider the case,
.option arch, rv32i
.option norelax
.option arch, +c
.byte 1
.align 2
addi a0, zero, 1
Assembler adds $d for the odd .byte, and then adds $x+arch for the
alignment. Since norelax, riscv_add_odd_padding_symbol will add the
$d and $x for the odd alignment, but accidently remove the $x+arch because
it has the same address as $d. Therefore, we will get the unexpected result
before applying this patch,
.byte 1 # $d
.align 2 # odd alignment, $xrv32ic replaced by $d + $x
After this patch, the expected result should be,
.byte 1 # $d
.align 2 # odd alignment, $xrv32ic replaced by $d + $xrv32ic
gas/
* config/tc-riscv.c (make_mapping_symbol): If we are adding mapping symbol
for odd alignment, then we probably will remove the $x+arch by accidently
when it has the same address of $d. Try to add the removed $x+arch back
after the $d rather than just $x.
(riscv_mapping_state): Updated since parameters of make_mapping_symbol are
changed.
(riscv_add_odd_padding_symbol): Likewise.
(riscv_remove_mapping_symbol): Removed and moved the code into the
riscv_check_mapping_symbols.
(riscv_check_mapping_symbols): Updated.
* testsuite/gas/riscv/mapping-dis.d: Updated and added new testcase.
* testsuite/gas/riscv/mapping-symbols.d: Likewise.
* testsuite/gas/riscv/mapping.s: Likewise.
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gas/ChangeLog:
* NEWS: Support Intel MSRLIST.
* config/tc-i386.c: Add msrlist.
* doc/c-i386.texi: Document .msrlist.
* testsuite/gas/i386/i386.exp: Add MSRLIST tests.
* testsuite/gas/i386/msrlist-inval.l: New test.
* testsuite/gas/i386/msrlist-inval.s: Ditto.
* testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto.
* testsuite/gas/i386/x86-64-msrlist.d: Ditto.
* testsuite/gas/i386/x86-64-msrlist.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New.
(X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto.
(prefix_table): New entry for msrlist.
(x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1
and X86_64_0F01_REG_0_MOD_3_RM_6_P_3.
* i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS
and CPU_ANY_MSRLIST_FLAGS.
* i386-init.h: Regenerated.
* i386-opc.h (CpuMSRLIST): New.
(i386_cpu_flags): Add cpumsrlist.
* i386-opc.tbl: Add MSRLIST instructions.
* i386-tbl.h: Regenerated.
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gas/ChangeLog:
* NEWS: Support Intel WRMSRNS.
* config/tc-i386.c: Add wrmsrns.
* doc/c-i386.texi: Document .wrmsrns.
* testsuite/gas/i386/i386.exp: Add WRMSRNS tests.
* testsuite/gas/i386/wrmsrns-intel.d: New test.
* testsuite/gas/i386/wrmsrns.d: Ditto.
* testsuite/gas/i386/wrmsrns.s: Ditto.
* testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto.
* testsuite/gas/i386/x86-64-wrmsrns.d: Ditto.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New.
(prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6.
(rm_table): New entry for wrmsrns.
* i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS
and CPU_ANY_WRMSRNS_FLAGS.
(cpu_flags): Add CpuWRMSRNS.
* i386-init.h: Regenerated.
* i386-opc.h (CpuWRMSRNS): New.
(i386_cpu_flags): Add cpuwrmsrns.
* i386-opc.tbl: Add WRMSRNS instructions.
* i386-tbl.h: Regenerated.
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gas/ChangeLog:
* config/tc-i386.c (cpu_flags_all_zero): Add new ARRAY_SIZE handle.
(cpu_flags_equal): Ditto.
(cpu_flags_and): Ditto.
(cpu_flags_or): Ditto.
(cpu_flags_and_not): Ditto.
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gas/ChangeLog:
* NEWS: Support Intel CMPccXADD.
* config/tc-i386.c: Add cmpccxadd.
(build_modrm_byte): Add operations for Vex.VVVV reg
on operand 0 while have memory operand.
* doc/c-i386.texi: Document .cmpccxadd.
* testsuite/gas/i386/i386.exp: Run CMPccXADD tests.
* testsuite/gas/i386/cmpccxadd-inval.s: New test.
* testsuite/gas/i386/cmpccxadd-inval.l: Ditto.
* testsuite/gas/i386/x86-64-cmpccxadd-intel.d: Ditto.
* testsuite/gas/i386/x86-64-cmpccxadd.s: Ditto.
* testsuite/gas/i386/x86-64-cmpccxadd.d: Ditto.
opcodes/ChangeLog:
* i386-dis.c (Mdq): New.
(X86_64_VEX_0F38E0): Ditto.
(X86_64_VEX_0F38E1): Ditto.
(X86_64_VEX_0F38E2): Ditto.
(X86_64_VEX_0F38E3): Ditto.
(X86_64_VEX_0F38E4): Ditto.
(X86_64_VEX_0F38E5): Ditto.
(X86_64_VEX_0F38E6): Ditto.
(X86_64_VEX_0F38E7): Ditto.
(X86_64_VEX_0F38E8): Ditto.
(X86_64_VEX_0F38E9): Ditto.
(X86_64_VEX_0F38EA): Ditto.
(X86_64_VEX_0F38EB): Ditto.
(X86_64_VEX_0F38EC): Ditto.
(X86_64_VEX_0F38ED): Ditto.
(X86_64_VEX_0F38EE): Ditto.
(X86_64_VEX_0F38EF): Ditto.
(x86_64_table): Add X86_64_VEX_0F38E0, X86_64_VEX_0F38E1,
X86_64_VEX_0F38E2, X86_64_VEX_0F38E3, X86_64_VEX_0F38E4,
X86_64_VEX_0F38E5, X86_64_VEX_0F38E6, X86_64_VEX_0F38E7,
X86_64_VEX_0F38E8, X86_64_VEX_0F38E9, X86_64_VEX_0F38EA,
X86_64_VEX_0F38EB, X86_64_VEX_0F38EC, X86_64_VEX_0F38ED,
X86_64_VEX_0F38EE, X86_64_VEX_0F38EF.
* i386-gen.c (cpu_flag_init): Add CPU_CMPCCXADD_FLAGS and
CPU_ANY_CMPCCXADD_FLAGS.
(cpu_flags): Add CpuCMPCCXADD.
* i386-init.h: Regenerated.
* i386-opc.h (CpuCMPCCXADD): New.
(i386_cpu_flags): Add cpucmpccxadd. Comment unused for it is actually 0.
* i386-opc.tbl: Add Intel CMPccXADD instructions.
* i386-tbl.h: Regenerated.
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gas/
* NEWS: Support Intel AVX-VNNI-INT8.
* config/tc-i386.c: Add avx_vnni_int8.
* doc/c-i386.texi: Document avx_vnni_int8.
* testsuite/gas/i386/avx-vnni-int8-intel.d: New file.
* testsuite/gas/i386/avx-vnni-int8.d: Likewise.
* testsuite/gas/i386/avx-vnni-int8.s: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni-int8.d: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni-int8.s: Likewise.
* testsuite/gas/i386/i386.exp: Run AVX VNNI INT8 tests.
opcodes/
* i386-dis.c: (PREFIX_VEX_0F3850) New.
(PREFIX_VEX_0F3851): Likewise.
(VEX_W_0F3850_P_0): Likewise.
(VEX_W_0F3850_P_1): Likewise.
(VEX_W_0F3850_P_2): Likewise.
(VEX_W_0F3850_P_3): Likewise.
(VEX_W_0F3851_P_0): Likewise.
(VEX_W_0F3851_P_1): Likewise.
(VEX_W_0F3851_P_2): Likewise.
(VEX_W_0F3851_P_3): Likewise.
(VEX_W_0F3850): Delete.
(VEX_W_0F3851): Likewise.
(prefix_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851.
(vex_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851,
delete VEX_W_0F3850 and VEX_W_0F3851.
(vex_w_table): Add VEX_W_0F3850_P_0, VEX_W_0F3850_P_1, VEX_W_0F3850_P_2
VEX_W_0F3850_P_3, VEX_W_0F3851_P_0, VEX_W_0F3851_P_1, VEX_W_0F3851_P_2
and VEX_W_0F3851_P_3, delete VEX_W_0F3850 and VEX_W_0F3851.
* i386-gen.c: (cpu_flag_init): Add CPU_AVX_VNNI_INT8_FLAGS
and CPU_ANY_AVX_VNNI_INT8_FLAGS.
(cpu_flags): Add CpuAVX_VNNI_INT8.
* i386-opc.h (CpuAVX_VNNI_INT8): New.
* i386-opc.tbl: Add Intel AVX_VNNI_INT8 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
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