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2016-11-03[ARC] Fix ldbit test on 32-bit systemsGraham Markall3-7/+13
The long immediate operand chosen for one of the ldbit tests is equivalent to a small negative value that would fit inside an s9 operand, leading to the assembler to choose an unexpected (but legitimate) encoding of the instruction on 32-bit systems, and therefore causing the test to fail. This commit fixes the test by changing the offending limm value so that it can no longer be interpreted as an s9 operand. gas/ChangeLog: * testsuite/gas/arc/nps400-6.s: Change ldbit tests so that limm operands are out of the range of an s9, in order to fix the test. * testsuite/gas/arc/nps400-6.d: Updated to match new expected output.
2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall3-0/+100
gas/ChangeLog: * testsuite/gas/arc/nps-400-9.d: Added. * testsuite/gas/arc/nps-400-9.s: Added. include/ChangeLog: * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t. opcodes/ChangeLog: * arc-dis.c (arc_insn_length): Return length 8 for instructions with major opcode 0xa. * arc-nps-400-tbl.h: Add dcmac instruction. * arc-opc.c (arc_operands): Added operands for dcmac instruction. (insert_nps_rbdouble_64): Added. (extract_nps_rbdouble_64): Added. (insert_nps_proto_size): Added. (extract_nps_proto_size): Added.
2016-11-03arc: Change max instruction length to 64-bitsAndrew Burgess2-125/+44
The current handling for arc instructions longer than 32-bits is all handled as a special case in both the assembler and disassembler. The problem with this approach is that it leads to code duplication, selecting a long instruction is exactly the same process as selecting a short instruction, except over more bits, in both cases we select based on bit comparison, and initial operand insertion and extraction. This commit unifies both the long and short instruction worlds, converting the core opcodes library from being largely 32-bit focused, to being largely 64-bit focused. The changes are, on the whole, not too much. There's obviously a lot of type changes but otherwise the bulk of the code just works. Most of the actual functional changes are to code that previously handled the longer 48 or 64 bit instructions. The insert/extract handlers for these have now been brought into line with the short instruction insert/extract handlers. All of the special case handling code that was previously added has now been removed again. Overall, this commit reduces the amount of code in the arc assembler and disassembler. gas/ChangeLog: * config/tc-arc.c (struct arc_insn): Change type of insn field. (md_number_to_chars_midend): Support 6- and 8-byte values. (emit_insn0): Update debug output. (find_opcode_match): Likewise. (build_fake_opcode_hash_entry): Delete. (find_special_case_long_opcode): Delete. (find_special_case): Remove long format special case handling. (insert_operand): Change instruction type and update debug print format. (assemble_insn): Change instruction type, update debug print formats, and remove unneeded assert. include/ChangeLog: * opcode/arc.h (struct arc_opcode): Change type of opcode and mask fields. (struct arc_long_opcode): Delete. (struct arc_operand): Change types for insert and extract handlers. opcodes/ChangeLog: * arc-dis.c (struct arc_operand_iterator): Remove all fields relating to long instruction processing, add new limm field. (OPCODE): Rename to... (OPCODE_32BIT_INSN): ...this. (OPCODE_AC): Delete. (skip_this_opcode): Handle different instruction lengths, update macro name. (special_flag_p): Update parameter type. (find_format_from_table): Update for more instruction lengths. (find_format_long_instructions): Delete. (find_format): Update for more instruction lengths. (arc_insn_length): Likewise. (extract_operand_value): Update for more instruction lengths. (operand_iterator_next): Remove code relating to long instructions. (arc_opcode_to_insn_type): New function. (print_insn_arc):Update for more instructions lengths. * arc-ext.c (extInstruction_t): Change argument type. * arc-ext.h (extInstruction_t): Change argument type. * arc-fxi.h: Change type unsigned to unsigned long long extensively throughout. * arc-nps400-tbl.h: Add long instructions taken from arc_long_opcodes table in arc-opc.c. * arc-opc.c: Update parameter types on insert/extract handlers. (arc_long_opcodes): Delete. (arc_num_long_opcodes): Delete. (arc_opcode_len): Update for more instruction lengths.
2016-11-03arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall2-2/+9
In preparation for moving to a world where arc instructions can be 2, 4, 6, or 8 bytes in length, replace the ARC_SHORT macro (which is either true of false) with an arc_opcode_len function that returns a length in bytes. There should be no functional change after this commit. gas/ChangeLog: * config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with arc_opcode_len. include/ChangeLog: * opcode/arc.h (arc_opcode_len): Declare. (ARC_SHORT): Delete. opcodes/ChangeLog: * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT with arc_opcode_len. (find_format_long_instructions): Likewise. * arc-opc.c (arc_opcode_len): New function.
2016-11-03gas/arc: Replace short_insn flag with insn length fieldGraham Markall2-45/+27
When assembling an instruction replace the short_insn boolean flag with an integer field for holding the instruction length. This is in preparation for moving to a world where instructions can be 2, 4, 6, or 8 bytes in length. gas/ChangeLog: * config/tc-arc.c (struct arc_insn): Replace short_insn flag with len field. (apply_fixups): Update to use len field. (emit_insn0): Simplify code, making use of len field. (md_convert_frag): Update to use len field. (assemble_insn): Update to use len field.
2016-11-04New option falkor for Qualcomm server partSiddhesh Poyarekar5-0/+15
This adds an option for the Qualcomm falkor core, the corresponding gcc patch is here: https://gcc.gnu.org/ml/gcc-patches/2016-11/msg00262.html This was tested with aarch64 and armhf builds and make check and also by building and running SPEC2006. * config/tc-aarch64.c (aarch64_cpus): Add falkor. * config/tc-arm.c (arm_cpus): Likewise. * doc/c-aarch64.texi: Likewise. * doc/c-arm.texi: Likewise.
2016-11-03X86: Decode opcode 0x82 as opcode 0x80 in 32-bit modeH.J. Lu4-0/+32
Update x86 disassembler to treat opcode 0x82 as an aliase of opcode 0x80 in 32-bit mode. gas/ PR binutils/20754 * testsuite/gas/i386/opcode.s: Add tests for opcode 0x82. * testsuite/gas/i386/opcode-intel.d: Updated. * testsuite/gas/i386/opcode.d: Likewise. opcodes/ PR binutils/20754 * i386-dis.c (REG_82): New. (X86_64_82_REG_0): Likewise. (X86_64_82_REG_1): Likewise. (X86_64_82_REG_2): Likewise. (X86_64_82_REG_3): Likewise. (X86_64_82_REG_4): Likewise. (X86_64_82_REG_5): Likewise. (X86_64_82_REG_6): Likewise. (X86_64_82_REG_7): Likewise. (dis386): Use REG_82. (reg_table): Add REG_82. (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
2016-11-03[ARM] Allow MOV/MOV.W to accept all possible immediatesJiong Wang10-17/+108
gas/ * config/tc-arm.c (SBIT_SHIFT): New. (T2_SBIT_SHIFT): Likewise. (t32_insn_ok): Return TRUE for MOV in ARMv8-M Baseline. (md_apply_fix): Try UINT16 encoding when ARM/Thumb modified immediate encoding failed. * testsuite/gas/arm/archv6t2-bad.s: New error case. * testsuite/gas/arm/archv6t2-bad.l: New error match. * testsuite/gas/arm/archv6t2.s: New testcase. * testsuite/gas/arm/archv6t2.d: New expected result. * testsuite/gas/arm/archv8m.s: New testcase. * testsuite/gas/arm/archv8m-base.d: New expected result. * testsuite/gas/arm/archv8m-main.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist16-2/+762
gas/ * config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw. (cpu_noarch): Add noavx512_4vnniw. * doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw. * testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests. * testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test. * testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto. * testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS, CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_4VNNIW. * i386-opc.h (enum): (AVX512_4VNNIW): New. (i386_cpu_flags): Add cpuavx512_4vnniw. * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist24-3/+1124
gas/ * config/tc-i386.c (cpu_arch): Add .avx512_4fmaps. (cpu_noarch): Add noavx512_4fmaps. (process_operands): Handle implicit quad group. * doc/c-i386.texi: Document avx512_4fmaps, noavx512_4fmaps. * testsuite/gas/i386/i386.exp: Add AVX512_4FMAPS tests. * testsuite/gas/i386/avx512_4fmaps_vl-intel.d: New test. * testsuite/gas/i386/avx512_4fmaps_vl.d: Ditto. * testsuite/gas/i386/avx512_4fmaps_vl.s: Ditto. * testsuite/gas/i386/avx512_4fmaps-intel.d: Ditto. * testsuite/gas/i386/avx512_4fmaps.d: Ditto. * testsuite/gas/i386/avx512_4fmaps.s: Ditto. * testsuite/gas/i386/avx512_4fmaps-warn.l: Ditto. * testsuite/gas/i386/avx512_4fmaps-warn.s: Ditto. * testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Ditto. * testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps-warn.l: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps-warn.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Ditto. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Ditto. opcodes/ * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS, CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_4FMAPS. (opcode_modifiers): Add ImplicitQuadGroup modifier. * i386-opc.h (AVX512_4FMAP): New. (i386_cpu_flags): Add cpuavx512_4fmaps. (ImplicitQuadGroup): New. (i386_opcode_modifier): Add implicitquadgroup. * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2016-11-01Add support for RISC-V architecture.Nick Clifton16-7/+2667
bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.
2016-10-27gas/arc: Don't rely on bfd list of cpu type for cpu selectionAndrew Burgess3-91/+131
In the ARC assembler, when a cpu type is specified using the .cpu directive, we rely on the bfd list of arc machine types in order to validate the cpu name passed in. This validation is only used in order to check that the cpu type passed to the .cpu directive matches any machine type selected earlier on the command line. Once that initial check has passed a full check is performed using the assemblers internal list of know cpu types. The problem is that the assembler knows about more cpu types than bfd, some cpu types known by the assembler are actually aliases for a base cpu type plus a specific set of assembler extensions. One such example is NPS400, though more could be added later. This commit removes the need for the assembler to use the bfd list of machine types for validation. Instead the error checking, to ensure that any value passed to a '.cpu' directive matches any earlier command line selection, is moved into the function arc_select_cpu. I have taken the opportunity to bundle the 4 separate static globals that describe the currently selected machine type into a single structure (called selected_cpu). gas/ChangeLog: * config/tc-arc.c (arc_target): Delete. (arc_target_name): Delete. (arc_features): Delete. (arc_mach_type): Delete. (mach_type_specified_p): Delete. (enum mach_selection_type): New enum. (mach_selection_mode): New static global. (selected_cpu): New static global. (arc_eflag): Rename to ... (arc_initial_eflag): ...this, and make const. (arc_select_cpu): Update comment, new parameter, check how previous machine type selection was made, and record this selection. Use selected_cpu instead of old globals. (arc_option): Remove use of arc_get_mach, instead use arc_select_cpu to validate machine type selection. Use selected_cpu over old globals. (allocate_tok): Use selected_cpu over old globals. (find_opcode_match): Likewise. (assemble_tokens): Likewise. (arc_cons_fix_new): Likewise. (arc_extinsn): Likewise. (arc_extcorereg): Likewise. (md_begin): Update default machine type selection, use selected_cpu over old globals. (md_parse_option): Update machine type selection option handling, use selected_cpu over old globals. * testsuite/gas/arc/nps400-0.s: Add .cpu directive. bfd/ChangeLog: * cpu-arc.c (arc_get_mach): Delete.
2016-10-26Revert "bison warning fixes"Alan Modra3-2/+8
This reverts commit 95e61695c199a07c832153cea25ae9c331d16a3c. People still want to use older versions of bison, apparently. Revert 2016-10-06 Alan Modra <amodra@gmail.com> * config/rl78-parse.y: Do use old %name-prefix syntax. * config/rx-parse.y: Likewise.
2016-10-21X86: Remove pcommit instructionH.J. Lu10-84/+13
Remove x86 pcommit instruction support, which has been deprecated: https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction gas/ * config/tc-i386.c (cpu_arch): Remove .pcommit. * doc/c-i386.texi: Likewise. * testsuite/gas/i386/i386.exp: Remove pcommit tests. * testsuite/gas/i386/pcommit-intel.d: Removed. * testsuite/gas/i386/pcommit.d: Likewise. * testsuite/gas/i386/pcommit.s: Likewise. * testsuite/gas/i386/x86-64-pcommit-intel.d: Likewise. * testsuite/gas/i386/x86-64-pcommit.d: Likewise. * testsuite/gas/i386/x86-64-pcommit.s: Likewise. opcodes/ * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed. (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry. (rm_table): Update the RM_0FAE_REG_7 entry. * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS. (cpu_flags): Remove CpuPCOMMIT. * i386-opc.h (CpuPCOMMIT): Removed. (i386_cpu_flags): Remove cpupcommit. * i386-opc.tbl: Remove pcommit. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2016-10-20Check invalid mask registersH.J. Lu4-0/+30
In 32-bit, the REX_B bit in the 3-byte VEX prefix is ignored and the the highest bit in VEX.vvvv is either 1 or ignored. In 64-bit, we need to check invalid mask registers. gas/ PR binutis/20705 * testsuite/gas/i386/i386.exp: Run x86-64-opcode-bad. * testsuite/gas/i386/x86-64-opcode-bad.d: New file. * testsuite/gas/i386/x86-64-opcode-bad.s: Likewise. opcodes/ PR binutis/20705 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and the highest bit in VEX.vvvv for the 3-byte VEX prefix in 32-bit mode. Don't check vex.register_specifier in 32-bit mode. (OP_E_register): Check invalid mask registers. (OP_G): Likewise. (OP_VEX): Likewise.
2016-10-19[GAS][ARM]Generate unpredictable warning for pc used in data processing ↵Renlin Li5-0/+103
instructions with register-shifted register operand. gas/ 2016-10-19 Renlin Li <renlin.li@arm.com> * config/tc-arm.c (encode_arm_shift): Generate unpredictable warning for register-shifted register instructions. * testsuite/gas/arm/shift-bad-pc.d: New. * testsuite/gas/arm/shift-bad-pc.l: New. * testsuite/gas/arm/shift-bad-pc.s: New.
2016-10-17Fixed matching in newly added test.Cupertino Miranda2-1/+5
gas/ChangeLog: 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com> * testsuite/arc/dis-inv.d: Fixed target match.
2016-10-17Removed pseudo invalid instructions opcodes.Cupertino Miranda3-0/+21
The disassember was generating invXXX instructions for cases when in reality we had llockd or scondd instrutions. opcodes/ChangeLog: Cupertino Miranda <cmiranda@synopsys.com> arc-tbl.h: Removed any "inv.+" instructions from the table. gas/ChangeLog: Cupertino Miranda <cmiranda@synopsys.com> testsuite/arc/dis-inv.s: Test to validate patch. testsuite/arc/dis-inv.d: Likewise.
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu5-0/+47
The ARC (short) instructions are using a special register number to indicate is the instruction uses a long immediate (LIMM). In the case of short instruction, this LIMM indicator depends on the ISA version used. Thus, for ARCv1 processors, the LIMM indicator is 0x3E, the same value used in "long" instructions. However, for the ARCv2 processors, this LIMM indicator is 0x1E. This patch fixes the LIMM detection for ARCv1 ISA and adds two tests. gas/ 2016-10-13 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/shortlimm_a7.d: New file. * testsuite/gas/arc/shortlimm_a7.s: Likewise. * testsuite/gas/arc/shortlimm_hs.d: Likewise. * testsuite/gas/arc/shortlimm_hs.s: Likewise. include/ 2016-10-13 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (ARC_OPCODE_ARCV2): New define. opcodes/ 2016-10-13 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (find_format_from_table): Discriminate LIMM indicator usage on ISA basis.
2016-10-11Enhance objdump so that it will use .got, .plt and .plt.got section symbols ↵Nick Clifton2-2/+6
when disassembling, and it will use dynamic relocs to interpret entries in the PLT and GOT. binutils * objdump.c (is_significant_symbol_name): New function. (remove_useless_symbols): Do not remove significanr symbols. (find_symbol_for_address): If an exact match for the specified address has not been found, try scanning the dynamic relocs to see if one of these matches the address. If so, use the symbol associated with the reloc. (objdump_print_addr_with_symbol): Do not print offsets to symbols with no value. (disassemble_section): Only use dynamic relocs if the user requested this. (disassemble_data): Always load dynamic relocs if they are available. ld * ld-aarch64/emit-relocs-515-be.d: Adjust output to match change in objdump. * ld-aarch64/emit-relocs-515.d: Likewise. * ld-aarch64/emit-relocs-516-be.d: Likewise. * ld-aarch64/emit-relocs-516.d: Likewise. * ld-aarch64/farcall-b-plt.d: Likewise. * ld-aarch64/farcall-bl-plt.d: Likewise. * ld-aarch64/gc-plt-relocs.d: Likewise. * ld-aarch64/tls-desc-ie.d: Likewise. * ld-aarch64/tls-tiny-desc.d: Likewise. * ld-aarch64/tls-tiny-gd.d: Likewise. * ld-aarch64/tls-tiny-ie.d: Likewise. * ld-arm/arm-app-abs32.d: Likewise. * ld-arm/arm-app.d: Likewise. * ld-arm/arm-lib-plt32.d: Likewise. * ld-arm/arm-lib.d: Likewise. * ld-arm/armthumb-lib.d: Likewise. * ld-arm/cortex-a8-fix-b-plt.d: Likewise. * ld-arm/cortex-a8-fix-bcc-plt.d: Likewise. * ld-arm/cortex-a8-fix-bl-plt.d: Likewise. * ld-arm/cortex-a8-fix-bl-rel-plt.d: Likewise. * ld-arm/cortex-a8-fix-blx-plt.d: Likewise. * ld-arm/farcall-mixed-app-v5.d: Likewise. * ld-arm/farcall-mixed-app.d: Likewise. * ld-arm/farcall-mixed-app2.d: Likewise. * ld-arm/farcall-mixed-lib-v4t.d: Likewise. * ld-arm/farcall-mixed-lib.d: Likewise. * ld-arm/ifunc-10.dd: Likewise. * ld-arm/ifunc-14.dd: Likewise. * ld-arm/ifunc-15.dd: Likewise. * ld-arm/ifunc-3.dd: Likewise. * ld-arm/ifunc-4.dd: Likewise. * ld-arm/ifunc-9.dd: Likewise. * ld-arm/long-plt-format.d: Likewise. * ld-arm/mixed-app-v5.d: Likewise. * ld-arm/mixed-app.d: Likewise. * ld-arm/mixed-lib.d: Likewise. * ld-arm/tls-lib-loc.d: Likewise. * ld-cris/dso-pltdis1.d: Likewise. * ld-cris/dso-pltdis2.d: Likewise. * ld-cris/dso12-pltdis.d: Likewise. * ld-elf/symbolic-func.r: Likewise. * ld-frv/fdpic-pie-1.d: Likewise. * ld-frv/fdpic-pie-2.d: Likewise. * ld-frv/fdpic-pie-6.d: Likewise. * ld-frv/fdpic-pie-7.d: Likewise. * ld-frv/fdpic-pie-8.d: Likewise. * ld-frv/fdpic-shared-1.d: Likewise. * ld-frv/fdpic-shared-2.d: Likewise. * ld-frv/fdpic-shared-3.d: Likewise. * ld-frv/fdpic-shared-4.d: Likewise. * ld-frv/fdpic-shared-5.d: Likewise. * ld-frv/fdpic-shared-6.d: Likewise. * ld-frv/fdpic-shared-7.d: Likewise. * ld-frv/fdpic-shared-8.d: Likewise. * ld-frv/fdpic-shared-local-2.d: Likewise. * ld-frv/fdpic-shared-local-8.d: Likewise. * ld-frv/fdpic-static-1.d: Likewise. * ld-frv/fdpic-static-2.d: Likewise. * ld-frv/fdpic-static-6.d: Likewise. * ld-frv/fdpic-static-7.d: Likewise. * ld-frv/fdpic-static-8.d: Likewise. * ld-frv/tls-dynamic-2.d: Likewise. * ld-frv/tls-initial-shared-2.d: Likewise. * ld-frv/tls-relax-shared-2.d: Likewise. * ld-frv/tls-shared-2.d: Likewise. * ld-i386/plt-nacl.pd: Likewise. * ld-i386/plt-pic-nacl.pd: Likewise. * ld-i386/plt-pic.pd: Likewise. * ld-i386/plt.pd: Likewise. * ld-i386/pr19636-1d-nacl.d: Likewise. * ld-i386/pr19636-1d.d: Likewise. * ld-i386/pr19636-2c-nacl.d: Likewise. * ld-i386/pr19636-2c.d: Likewise. * ld-ifunc/ifunc-21-x86-64.d: Likewise. * ld-ifunc/ifunc-22-x86-64.d: Likewise. * ld-ifunc/pr17154-i386.d: Likewise. * ld-ifunc/pr17154-x86-64.d: Likewise. * ld-m68k/plt1-68020.d: Likewise. * ld-m68k/plt1-cpu32.d: Likewise. * ld-m68k/plt1-isab.d: Likewise. * ld-m68k/plt1-isac.d: Likewise. * ld-metag/shared.d: Likewise. * ld-metag/stub_pic_app.d: Likewise. * ld-metag/stub_pic_shared.d: Likewise. * ld-metag/stub_shared.d: Likewise. * ld-s390/tlsbin_64.dd: Likewise. * ld-s390/tlspic_64.dd: Likewise. * ld-tic6x/shlib-1.dd: Likewise. * ld-tic6x/shlib-1b.dd: Likewise. * ld-tic6x/shlib-1rb.dd: Likewise. * ld-tic6x/shlib-app-1.dd: Likewise. * ld-tic6x/shlib-app-1b.dd: Likewise. * ld-tic6x/shlib-app-1r.dd: Likewise. * ld-tic6x/shlib-app-1rb.dd: Likewise. * ld-tic6x/shlib-noindex.dd: Likewise. * ld-vax-elf/export-class-data.dd: Likewise. * ld-vax-elf/plt-local-lib.dd: Likewise. * ld-vax-elf/plt-local.dd: Likewise. * ld-x86-64/bnd-ifunc-2.d: Likewise. * ld-x86-64/bnd-plt-1.d: Likewise. * ld-x86-64/gotpcrel1.dd: Likewise. * ld-x86-64/libno-plt-1b.dd: Likewise. * ld-x86-64/load1c-nacl.d: Likewise. * ld-x86-64/load1c.d: Likewise. * ld-x86-64/load1d-nacl.d: Likewise. * ld-x86-64/load1d.d: Likewise. * ld-x86-64/mov1a.d: Likewise. * ld-x86-64/mov1b.d: Likewise. * ld-x86-64/mov1c.d: Likewise. * ld-x86-64/mov1d.d: Likewise. * ld-x86-64/mov2a.d: Likewise. * ld-x86-64/mov2b.d: Likewise. * ld-x86-64/mov2c.d: Likewise. * ld-x86-64/mov2d.d: Likewise. * ld-x86-64/mpx3.dd: Likewise. * ld-x86-64/mpx4.dd: Likewise. * ld-x86-64/no-plt-1a.dd: Likewise. * ld-x86-64/no-plt-1b.dd: Likewise. * ld-x86-64/no-plt-1c.dd: Likewise. * ld-x86-64/no-plt-1e.dd: Likewise. * ld-x86-64/no-plt-1f.dd: Likewise. * ld-x86-64/no-plt-1g.dd: Likewise. * ld-x86-64/plt-main-bnd.dd: Likewise. * ld-x86-64/plt-nacl.pd: Likewise. * ld-x86-64/plt.pd: Likewise. * ld-x86-64/pr18591.d: Likewise. * ld-x86-64/pr19609-1c.d: Likewise. * ld-x86-64/pr19609-1e.d: Likewise. * ld-x86-64/pr19609-1j.d: Likewise. * ld-x86-64/pr19609-1l.d: Likewise. * ld-x86-64/pr19609-1m.d: Likewise. * ld-x86-64/pr19609-5b.d: Likewise. * ld-x86-64/pr19609-5c.d: Likewise. * ld-x86-64/pr19609-5e.d: Likewise. * ld-x86-64/pr19609-6b.d: Likewise. * ld-x86-64/pr19609-7b.d: Likewise. * ld-x86-64/pr19609-7d.d: Likewise. * ld-x86-64/pr19636-2d.d: Likewise. * ld-x86-64/pr20093-1.d: Likewise. * ld-x86-64/pr20093-2.d: Likewise. * ld-x86-64/pr20253-1b.d: Likewise. * ld-x86-64/pr20253-1d.d: Likewise. * ld-x86-64/pr20253-1f.d: Likewise. * ld-x86-64/pr20253-1h.d: Likewise. * ld-x86-64/pr20253-1j.d: Likewise. * ld-x86-64/pr20253-1l.d: Likewise. * ld-x86-64/protected3.d: Likewise. * ld-x86-64/tlsbin.dd: Likewise. * ld-x86-64/tlsbin2.dd: Likewise. * ld-x86-64/tlsbindesc.dd: Likewise. * ld-x86-64/tlsdesc-nacl.pd: Likewise. * ld-x86-64/tlsdesc.dd: Likewise. * ld-x86-64/tlsdesc.pd: Likewise. * ld-x86-64/tlsgd10.dd: Likewise. * ld-x86-64/tlsgd5.dd: Likewise. * ld-x86-64/tlsgd6.dd: Likewise. * ld-x86-64/tlsgd8.dd: Likewise. * ld-x86-64/tlsgdesc.dd: Likewise. * ld-x86-64/tlspic.dd: Likewise. * ld-x86-64/tlspic2.dd: Likewise. 2016-10-11 Nick Clifton <nickc@redhat.com> PR ld/20535 * emultempl/elf32.em (_search_needed): Add support for pseudo environment variables supported by ld.so. Namely $ORIGIN, $LIB and $PLATFORM. * configure.ac: Add getauxval to list AC_CHECK_FUNCS list. * config.in: Regenerate. * configure: Regenerate. 2016-10-11 Alan Modra <amodra@gmail.com> * ldlang.c (lang_do_assignments_1): Descend into output section statements that do not yet have bfd sections. Set symbol section temporarily for symbols defined in such statements to the undefined section. Don't error on data or reloc statements until final phase. * ldexp.c (exp_fold_tree_1 <etree_assign>): Handle bfd_und_section in expld.section. * testsuite/ld-mmix/bpo-10.d: Adjust. * testsuite/ld-mmix/bpo-11.d: Adjust. 2016-10-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * emulparams/elf64_s390.sh: Move binary start to 16M. * testsuite/ld-s390/tlsbin_64.dd: Adjust testcases accordingly. * testsuite/ld-s390/tlsbin_64.rd: Likewise. 2016-10-07 Alan Modra <amodra@gmail.com> * ldexp.c (MAX): Define. (exp_unop, exp_binop, exp_trinop): Alloc at least enough for etree_type.value. 2016-10-07 Alan Modra <amodra@gmail.com> * testsuite/lib/ld-lib.exp (is_generic_elf): New, extracted from.. * testsuite/ld-elf/elf.exp: ..here. 2016-10-06 Ludovic Court?s <ludo@gnu.org> * emulparams/elf32bmipn32-defs.sh: Shift quote of "x$EMULATION_NAME" to the left to work around <http://ftp.gnu.org/gnu/bash/bash-4.2-patches/bash42-007>. 2016-10-06 Alan Modra <amodra@gmail.com> * lexsup.c: Spell fall through comments consistently and add missing fall through comments. 2016-10-06 Alan Modra <amodra@gmail.com> * plugin.c (asymbol_from_plugin_symbol): Avoid compiler warning by adding return. 2016-10-04 Alan Modra <amodra@gmail.com> * ld.texinfo (Expression Section): Update result of arithmetic expressions. * ldexp.c (arith_result_section): New function. (fold_binary): Use it. 2016-10-04 Alan Modra <amodra@gmail.com> * ldexp.c (exp_value_fold): New function. (exp_unop, exp_binop, exp_trinop): Use it. 2016-09-30 Alan Modra <amodra@gmail.com> * scripttempl/v850.sc: Don't reference __ctbp, __ep, __gp when not relocating. * scripttempl/v850_rh850.sc: Likewise. 2016-09-30 Alan Modra <amodra@gmail.com> PR ld/20528 * testsuite/ld-elf/pr20528a.d: xfail generic elf targets. Allow multiple .text sections for hppa-linux. * testsuite/ld-elf/pr20528b.d: Likewise. 2016-09-30 Alan Modra <amodra@gmail.com> * ldmain.c (default_bfd_error_handler): New function pointer. (ld_bfd_error_handler): New function. (main): Arrange to call it on bfd errors/warnings. (ld_bfd_assert_handler): Enable tail call. 2016-09-30 Alan Modra <amodra@gmail.com> * ldlang.c (ignore_bfd_errors): Update params. 2016-09-29 H.J. Lu <hongjiu.lu@intel.com> PR ld/20528 * emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Don't merge 2 sections with different SHF_EXCLUDE. * testsuite/ld-elf/pr20528a.d: New file. * testsuite/ld-elf/pr20528a.s: Likewise. * testsuite/ld-elf/pr20528b.d: Likewise. * testsuite/ld-elf/pr20528b.s: Likewise. 2016-09-28 Christophe Lyon <christophe.lyon@linaro.org> PR ld/20608 * testsuite/ld-arm/arm-elf.exp: Handle new testcase. * testsuite/ld-arm/farcall-mixed-app2.d: New file. * testsuite/ld-arm/farcall-mixed-app2.r: Likewise. * testsuite/ld-arm/farcall-mixed-app2.s: Likewise. * testsuite/ld-arm/farcall-mixed-app2.sym: Likewise. 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com> * Makefile.in: Regenerate. * configure: Likewise. 2016-09-26 Alan Modra <amodra@gmail.com> * testsuite/ld-powerpc/attr-gnu-4-4.s: Delete. * testsuite/ld-powerpc/attr-gnu-4-14.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-24.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-34.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-41.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-32.d: Adjust expected warning. * testsuite/ld-powerpc/attr-gnu-8-23.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-01.d: Adjust expected output. * testsuite/ld-powerpc/attr-gnu-4-02.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-03.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-10.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-11.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-20.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-22.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-33.d: Likewise. * testsuite/ld-powerpc/attr-gnu-8-11.d: Likewise. * testsuite/ld-powerpc/powerpc.exp: Don't run deleted tests. 2016-09-23 Akihiko Odaki <akihiko.odaki.4i@stu.hosei.ac.jp> PR ld/20595 * testsuite/ld-arm/unwind-4.d: Add -q option to linker command line and -r option to objdump command line. Match emitted relocs to make sure that superflous relocs are not generated. 2016-09-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * emulparams/elf64_s390.sh: Change TEXT_START_ADDR to 256MB. * testsuite/ld-s390/tlsbin_64.dd: Adjust testcase accordingly. * testsuite/ld-s390/tlsbin_64.rd: Likewise. 2016-09-22 Nick Clifton <nickc@redhat.com> * emultempl/elf32.em (_try_needed): In verbose mode, report failed attempts to find a needed library. 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> * testsuite/ld-aarch64/emit-relocs-28.d: Expect spaces after "," in addresses. * testsuite/ld-aarch64/emit-relocs-301-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-301.d: Likewise. * testsuite/ld-aarch64/emit-relocs-302-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-302.d: Likewise. * testsuite/ld-aarch64/emit-relocs-310-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-310.d: Likewise. * testsuite/ld-aarch64/emit-relocs-313.d: Likewise. * testsuite/ld-aarch64/emit-relocs-515-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-515.d: Likewise. * testsuite/ld-aarch64/emit-relocs-516-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-516.d: Likewise. * testsuite/ld-aarch64/emit-relocs-531.d: Likewise. * testsuite/ld-aarch64/emit-relocs-532.d: Likewise. * testsuite/ld-aarch64/emit-relocs-533.d: Likewise. * testsuite/ld-aarch64/emit-relocs-534.d: Likewise. * testsuite/ld-aarch64/emit-relocs-535.d: Likewise. * testsuite/ld-aarch64/emit-relocs-536.d: Likewise. * testsuite/ld-aarch64/emit-relocs-537.d: Likewise. * testsuite/ld-aarch64/emit-relocs-538.d: Likewise. * testsuite/ld-aarch64/erratum835769.d: Likewise. * testsuite/ld-aarch64/erratum843419.d: Likewise. * testsuite/ld-aarch64/farcall-b-plt.d: Likewise. * testsuite/ld-aarch64/farcall-bl-plt.d: Likewise. * testsuite/ld-aarch64/gc-plt-relocs.d: Likewise. * testsuite/ld-aarch64/ifunc-21.d: Likewise. * testsuite/ld-aarch64/ifunc-7c.d: Likewise. * testsuite/ld-aarch64/tls-desc-ie.d: Likewise. * testsuite/ld-aarch64/tls-large-desc-be.d: Likewise. * testsuite/ld-aarch64/tls-large-desc.d: Likewise. * testsuite/ld-aarch64/tls-large-ie-be.d: Likewise. * testsuite/ld-aarch64/tls-large-ie.d: Likewise. * testsuite/ld-aarch64/tls-relax-all.d: Likewise. * testsuite/ld-aarch64/tls-relax-gd-ie.d: Likewise. * testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d: Likewise. * testsuite/ld-aarch64/tls-relax-gdesc-ie.d: Likewise. * testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d: Likewise. * testsuite/ld-aarch64/tls-relax-large-desc-ie.d: Likewise. * testsuite/ld-aarch64/tls-tiny-desc.d: Likewise. * testsuite/ld-aarch64/tls-tiny-gd.d: Likewise. gas * gas/arm/tls.d: Adjust output to match change in objdump.
2016-10-11[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudoJiong Wang2-17/+22
opcode/ PR target/20666 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index. gas/ * testsuite/gas/aarch64/alias-2.d: Update expected results.
2016-10-10MIPS64: Adjust cfi* testcases.Andreas Krebbel10-17/+29
The CFI* testcases fail on MIPS64 because the augmentation string does not match the regexp. This is because MIPS64 doesn't use the default of 4 for DWARF2_FDE_RELOC_SIZE which ends up as "b" in the augmentation string. MIPS64 uses the address size which is 8 resulting in "c". Adding c to the regexp fixes a couple of them. Others also need adjustments in the FDE header lines due to different sizes/offsets. gas/ChangeLog: 2016-10-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * testsuite/gas/cfi/cfi-common-1.d: Adjust regexps for mips64. * testsuite/gas/cfi/cfi-common-2.d: Likewise. * testsuite/gas/cfi/cfi-common-3.d: Likewise. * testsuite/gas/cfi/cfi-common-4.d: Likewise. * testsuite/gas/cfi/cfi-common-5.d: Likewise. * testsuite/gas/cfi/cfi-common-7.d: Likewise. * testsuite/gas/cfi/cfi-common-8.d: Likewise. * testsuite/gas/cfi/cfi-common-9.d: Likewise. * testsuite/gas/cfi/cfi-mips-1.d: Likewise.
2016-10-08Auto-generated dependencies for rx-parse.o and rl78-parse.oAlan Modra3-27/+22
I noticed a while ago that the rx-elf gas gprel test regressed for no apparent reason. It turns out that the problem was rx-parse.y using BFD_RELOC_RX_* values, which may change when other targets add new relocs. If rx-parse.o doesn't depend on bfd.h, it won't be recompiled. * Makefile.am (EXTRA_as_new_SOURCES): Add config/rl78-parse.y and config/rx-parse.y. Move config/bfin-parse.y. (bfin-parse.@OBJEXT@, rl78-parse.@OBJEXT@, rx-parse.@OBJEXT@): Delete. ($(srcdir)/config/rl78-defs.h): New rule. * Makefile.in: Regenerate.
2016-10-07[AArch64] PR target/20667, fix disassembler for the "special" optional ↵Jiong Wang3-0/+162
SYS_Rt operand for "ic"/"tlbi" gas/ PR target/20667 * testsuite/gas/aarch64/sys-rt-reg.s: Test source for instructions using SYS_Rt reg. * testsuite/gas/aarch64/sys-rt-reg.d: New testcase. opcodes/ PR target/20667 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's available.
2016-10-06[ARC] Fix parsing leave_s and enter_s mnemonics.Claudiu Zissulescu6-2/+68
gas/ 2016-10-06 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/leave_enter.d: New file. * testsuite/gas/arc/leave_enter.s: Likewise. * testsuite/gas/arc/regnames.d: Likewise. * testsuite/gas/arc/regnames.s: Likewise. * config/tc-arc.c (arc_parse_name): Don't match reg names against confirmed symbol names.
2016-10-06-Wimplicit-fallthrough dodgy fixesAlan Modra3-4/+9
The comment logically belongs inside the preprocessor conditional, but gcc's -Wimplicit-fallthrough loses track of it. Revert when/if https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77817 is fixed. * app.c (do_scrub_chars): Move fall through comment. * expr.c (operand): Likewise.
2016-10-06Refine .cfi_sections check to only consider compact eh_frameMatthew Fortune5-1/+42
The .cfi_sections directive can be safely used multiple times with different sections named at any time unless the compact form of exception handling is requested after CFI information has been emitted. Only the compact form of CFI information changes the way in which CFI is generated and therefore cannot be retrospectively requested after generating CFI information. gas/ PR gas/20648 * dw2gencfi.c (dot_cfi_sections): Refine the check for inconsistent .cfi_sections to only consider compact vs non compact forms. * testsuite/gas/cfi/cfi-common-9.d: New file. * testsuite/gas/cfi/cfi-common-9.s: New file. * testsuite/gas/cfi/cfi.exp: Run new test.
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra37-18/+193
Comment changes. bfd/ * coff-h8300.c: Spell fall through comments consistently. * coffgen.c: Likewise. * elf32-hppa.c: Likewise. * elf32-ppc.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elf64-ppc.c: Likewise. * elfxx-aarch64.c: Likewise. * elfxx-mips.c: Likewise. * cpu-ns32k.c: Add missing fall through comments. * elf-m10300.c: Likewise. * elf32-arm.c: Likewise. * elf32-avr.c: Likewise. * elf32-bfin.c: Likewise. * elf32-frv.c: Likewise. * elf32-i386.c: Likewise. * elf32-microblaze.c: Likewise. * elf32-nds32.c: Likewise. * elf32-ppc.c: Likewise. * elf32-rl78.c: Likewise. * elf32-rx.c: Likewise. * elf32-s390.c: Likewise. * elf32-sh.c: Likewise. * elf32-tic6x.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-ppc.c: Likewise. * elf64-s390.c: Likewise. * elf64-x86-64.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * ieee.c: Likewise. * oasys.c: Likewise. * pdp11.c: Likewise. * srec.c: Likewise. * versados.c: Likewise. opcodes/ * aarch64-opc.c: Spell fall through comments consistently. * i386-dis.c: Likewise. * aarch64-dis.c: Add missing fall through comments. * aarch64-opc.c: Likewise. * arc-dis.c: Likewise. * arm-dis.c: Likewise. * i386-dis.c: Likewise. * m68k-dis.c: Likewise. * mep-asm.c: Likewise. * ns32k-dis.c: Likewise. * sh-dis.c: Likewise. * tic4x-dis.c: Likewise. * tic6x-dis.c: Likewise. * vax-dis.c: Likewise. binutils/ * dlltool.c: Spell fall through comments consistently. * objcopy.c: Likewise. * readelf.c: Likewise. * dwarf.c: Add missing fall through comments. * elfcomm.c: Likewise. * sysinfo.y: Likewise. * readelf.c: Likewise. Also remove extraneous comments. gas/ * app.c: Add missing fall through comments. * dw2gencfi.c: Likewise. * expr.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-h8300.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/obj-elf.c: Likewise. * config/tc-i386.c: Likewise. * depend.c: Spell fall through comments consistently. * config/tc-arm.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/tc-z8k.c: Likewise. gprof/ * gprof.c: Add missing fall through comments. ld/ * lexsup.c: Spell fall through comments consistently and add missing fall through comments.
2016-10-06-Wimplicit-fallthrough noreturn fixesAlan Modra2-1/+5
binutils/ * cxxfilt.c (usage): Add ATTRIBUTE_NORETURN. * elfedit.c (usage): Likewise. * nm.c (usage): Likewise. * objcopy.c (copy_usage, strip_usage): Likewise. * srconv.c (show_usage): Likewise. * strings.c (usage): Likewise. * sysdump.c (show_usage): Likewise. * srconv.c: Remove unneeded forward function declarations. * strings.c: Likewise. * sysdump.c: Likewise. gas/ * as.h (as_assert): Add ATTRIBUTE_NORETURN.
2016-10-06-Wimplicit-fallthrough error fixesAlan Modra9-10/+28
Well, not all are errors, but a little more substantive than just fiddling with comments. bfd/ * coffcode.h (coff_slurp_symbol_table): Revert accidental commit made 2015-01-08. * elf32-nds32.c (nds32_elf_grok_psinfo): Add missing break. * reloc.c (bfd_default_reloc_type_lookup): Add missing breaks. opcodes/ * arc-ext.c (create_map): Add missing break. * msp430-decode.opc (encode_as): Likewise. * msp430-decode.c: Regenerate. binutils/ * coffdump.c (dump_coff_where): Add missing break. * stabs.c (stab_xcoff_builtin_type): Likewise. gas/ * config/tc-arc.c (find_opcode_match): Add missing break. * config/tc-i960.c (get_cdisp): Likewise. * config/tc-metag.c (parse_swap, md_apply_fix): Likewise. * config/tc-mt.c (md_parse_option): Likewise. * config/tc-nds32.c (nds32_apply_fix): Likewise. * config/tc-hppa.c (pa_ip): Assert rather than testing last condition of multiple if statements. * config/tc-s390.c (s390_exp_compare): Return 0 on error. * config/tc-tic4x.c (tic4x_operand_parse): Add as_bad and break out of case rather than falling into next case. Formatting. ld/ * plugin.c (asymbol_from_plugin_symbol): Avoid compiler warning by adding return.
2016-10-06bison warning fixesAlan Modra3-2/+7
* config/rl78-parse.y: Don't use deprecated %name-prefix. * config/rx-parse.y: Likewise.
2016-09-30[AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang3-0/+22
opcode/ PR target/20553 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field. gas/ * testsuite/gas/aarch64/advsimd-fp16.s (indexed_elem): New high index testcases for H and S variants. New low index testcases for D variant. * testsuite/gas/aarch64/advsimd-fp16.d: Update expected results.
2016-09-29Add .cfi_val_offset GAS command.Andreas Krebbel6-0/+76
This patch adds support for .cfi_val_offset GAS pseudo command which maps to DW_CFA_val_offset and DW_CFA_val_offset_sf. gas/ChangeLog: 2016-09-29 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * doc/as.texinfo: Add docu for .cfi_val_offset. * dw2gencfi.c (cfi_add_CFA_val_offset): New function. (dot_cfi): Add case for DW_CFA_val_offset. (output_cfi_insn): Likewise. (cfi_pseudo_table): Add entry for cfi_val_offset. * dw2gencfi.h: Add prototype for cfi_add_CFA_val_offset. * testsuite/gas/cfi/cfi-common-8.d: New test. * testsuite/gas/cfi/cfi-common-8.s: New test. * testsuite/gas/cfi/cfi.exp: Run cfi-common-8 testcase. binutils/ChangeLog: 2016-09-29 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * dwarf.c (display_debug_frames): Adjust output line.
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra4-4/+12
cmp[l][o] get an optional L field only when generating 32-bit code. dcbf, tlbie and tlbiel keep their optional L field, ditto for R field of tbegin. cmprb, tsr., wlcr[all] and mtsle all change to a compulsory L field. L field of dcbf and wclr is 2 bits. PR 20641 include/ * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define. opcodes/ * ppc-opc.c (L): Make compulsory. (LOPT): New, optional form of L. (HTM_R): Define as LOPT. (L0, L1): Delete. (L32OPT): New, optional for 32-bit L. (L2OPT): New, 2-bit L for dcbf. (SVC_LEC): Update. (L2): Define. (insert_l0, extract_l0, insert_l1, extract_l2): Delete. (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT. <dcbf>: Use L2OPT. <tlbiel, tlbie>: Use LOPT. <wclr, wclrall>: Use L2. gas/ * config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32. * testsuite/gas/ppc/power8.s: Provide tbegin. operand. * testsuite/gas/ppc/power9.d: Update cmprb disassembly.
2016-09-26tc-xtensa.c: fixup xg_reverse_shift_count typoTrevor Saunders2-1/+6
gas/ChangeLog: 2016-09-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-xtensa.c (xg_reverse_shift_count): Pass cnt_arg instead of cnt_argp to concat.
2016-09-26When building target binaries, ensure that the warning flags selected for ↵Vlad Zakharov4-6/+58
the command line match the target compiler. bfd * warning.m4 (AC_EGREP_CPP_FOR_BUILD): Introduce macro to verify CC_FOR_BUILD compiler. (AM_BINUTILS_WARNINGS): Introduce ac_cpp_for_build variable and add CC_FOR_BUILD compiler checks. * Makefile.in: Regenerate. * configure: Likewise. * doc/Makefile.in: Likewise. binutils * Makefile.am: Replace AM_CLFAGS with AM_CFLAGS_FOR_BUILD when building with CC_FOR_BUILD compiler. * Makefile.in: Regenerate. * configure: Likewise. * doc/Makefile.in: Likewise. gas * Makefile.in: Regenerate. * configure: Likewise. * doc/Makefile.in: Likewise. gold * Makefile.in: Regenerate. * configure: Likewise. * testsuite/Makefile.in: Likewise. gprof * Makefile.in: Regenerate. * configure: Likewise. ld * Makefile.in: Regenerate. * configure: Likewise. opcodes * Makefile.in: Regenerate. * configure: Likewise.
2016-09-26PowerPC .gnu.attributesAlan Modra2-0/+29
This patch extends Tag_GNU_Power_ABI_FP to cover long double ABIs, makes the assembler warn about undefined tag values, and removes similar warnings from the linker. I think it is better to not warn in the linker about undefined tag values as future extensions to the tags then won't result in likely bogus warnings. This is consistent with the fact that an older linker won't warn on an entirely new tag. include/ * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment. bfd/ * elf-bfd.h (_bfd_elf_ppc_merge_fp_attributes): Declare. * elf32-ppc.c (_bfd_elf_ppc_merge_fp_attributes): New function. (ppc_elf_merge_obj_attributes): Use it. Don't copy first file attributes, merge them. Don't warn about undefined tag bits, or copy unknown values to output. * elf64-ppc.c (ppc64_elf_merge_private_bfd_data): Call _bfd_elf_ppc_merge_fp_attributes. binutils/ * readelf.c (display_power_gnu_attribute): Catch truncated section for all powerpc attributes. Display long double ABI. Don't capitalize words, except for names. Show known bits of tag values when some unknown bits are present. Whitespace fixes. gas/ * config/tc-ppc.c (ppc_elf_gnu_attribute): New function. (md_pseudo_table <ELF>): Handle "gnu_attribute". ld/ * testsuite/ld-powerpc/attr-gnu-4-4.s: Delete. * testsuite/ld-powerpc/attr-gnu-4-14.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-24.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-34.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-41.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-32.d: Adjust expected warning. * testsuite/ld-powerpc/attr-gnu-8-23.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-01.d: Adjust expected output. * testsuite/ld-powerpc/attr-gnu-4-02.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-03.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-10.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-11.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-20.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-22.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-33.d: Likewise. * testsuite/ld-powerpc/attr-gnu-8-11.d: Likewise. * testsuite/ld-powerpc/powerpc.exp: Don't run deleted tests.
2016-09-22Remove legacy basepri_mask MRS/MSR special regThomas Preud'homme2-1/+5
2016-09-22 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (v7m_psrs): Remove BASEPRI_MASK MRS/MSR special register and redundant basepri_max.
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford16-9612/+9633
I got an off-list request to make the AArch64 disassembler print spaces after commas in addresses. This patch does that. The same code is used to print operands in "did you mean" errors, so to keep things consistent, the patch also prints spaces between operands in those messages. opcodes/ * aarch64-opc.c (print_immediate_offset_address): Print spaces after commas in addresses. (aarch64_print_operand): Likewise. gas/ * config/tc-aarch64.c (print_operands): Print spaces between operands. * testsuite/gas/aarch64/ilp32-basic.d: Expect spaces after "," in addresses. * testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise. * testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise. * testsuite/gas/aarch64/ldst-reg-pair.d: Likewise. * testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise. * testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise. * testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise. * testsuite/gas/aarch64/reloc-insn.d: Likewise. * testsuite/gas/aarch64/sve.d: Likewise. * testsuite/gas/aarch64/symbol.d: Likewise. * testsuite/gas/aarch64/system.d: Likewise. * testsuite/gas/aarch64/tls-desc.d: Likewise. * testsuite/gas/aarch64/sve-invalid.l: Expect spaces after "," in suggested alternatives. * testsuite/gas/aarch64/verbose-error.l: Likewise. ld/ * testsuite/ld-aarch64/emit-relocs-28.d: Expect spaces after "," in addresses. * testsuite/ld-aarch64/emit-relocs-301-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-301.d: Likewise. * testsuite/ld-aarch64/emit-relocs-302-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-302.d: Likewise. * testsuite/ld-aarch64/emit-relocs-310-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-310.d: Likewise. * testsuite/ld-aarch64/emit-relocs-313.d: Likewise. * testsuite/ld-aarch64/emit-relocs-515-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-515.d: Likewise. * testsuite/ld-aarch64/emit-relocs-516-be.d: Likewise. * testsuite/ld-aarch64/emit-relocs-516.d: Likewise. * testsuite/ld-aarch64/emit-relocs-531.d: Likewise. * testsuite/ld-aarch64/emit-relocs-532.d: Likewise. * testsuite/ld-aarch64/emit-relocs-533.d: Likewise. * testsuite/ld-aarch64/emit-relocs-534.d: Likewise. * testsuite/ld-aarch64/emit-relocs-535.d: Likewise. * testsuite/ld-aarch64/emit-relocs-536.d: Likewise. * testsuite/ld-aarch64/emit-relocs-537.d: Likewise. * testsuite/ld-aarch64/emit-relocs-538.d: Likewise. * testsuite/ld-aarch64/erratum835769.d: Likewise. * testsuite/ld-aarch64/erratum843419.d: Likewise. * testsuite/ld-aarch64/farcall-b-plt.d: Likewise. * testsuite/ld-aarch64/farcall-bl-plt.d: Likewise. * testsuite/ld-aarch64/gc-plt-relocs.d: Likewise. * testsuite/ld-aarch64/ifunc-21.d: Likewise. * testsuite/ld-aarch64/ifunc-7c.d: Likewise. * testsuite/ld-aarch64/tls-desc-ie.d: Likewise. * testsuite/ld-aarch64/tls-large-desc-be.d: Likewise. * testsuite/ld-aarch64/tls-large-desc.d: Likewise. * testsuite/ld-aarch64/tls-large-ie-be.d: Likewise. * testsuite/ld-aarch64/tls-large-ie.d: Likewise. * testsuite/ld-aarch64/tls-relax-all.d: Likewise. * testsuite/ld-aarch64/tls-relax-gd-ie.d: Likewise. * testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d: Likewise. * testsuite/ld-aarch64/tls-relax-gdesc-ie.d: Likewise. * testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d: Likewise. * testsuite/ld-aarch64/tls-relax-large-desc-ie.d: Likewise. * testsuite/ld-aarch64/tls-tiny-desc.d: Likewise. * testsuite/ld-aarch64/tls-tiny-gd.d: Likewise.
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford6-80/+90
One of the review comments from the SVE series was that it would be better to use "must" rather than "should" in error messages. I think this patch fixes all cases in the AArch64 code. It also uses "must be" instead of "expected to be". opcodes/ * aarch64-opc.c (operand_general_constraint_met_p): Use "must be" rather than "should be" or "expected to be" in error messages. gas/ * config/tc-aarch64.c (output_operand_error_record): Use "must be" rather than "should be" or "expected to be" in error messages. (parse_operands): Likewise. * testsuite/gas/aarch64/diagnostic.l: Likewise. * testsuite/gas/aarch64/legacy_reg_names.l: Likewise. * testsuite/gas/aarch64/sve-invalid.l: Likewise. * testsuite/gas/aarch64/sve-reg-diagnostic.l: Likewise.
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford11-69/+228
SVE defines new names for existing NZCV conditions, to reflect the result of instructions like PTEST. This patch adds support for these names. The patch also adds comments to the disassembly output to show the alternative names of a condition code. For example: cinv x0, x1, cc becomes: cinv x0, x1, cc // cc = lo, ul, last and: b.cc f0 <...> becomes: b.cc f0 <...> // b.lo, b.ul, b.last Doing this for the SVE names follows the practice recommended by the SVE specification and is definitely useful when reading SVE code. If the feeling is that it's too distracting elsewhere, we could add an option to turn it off. include/ * opcode/aarch64.h (aarch64_cond): Bump array size to 4. opcodes/ * aarch64-dis.c (remove_dot_suffix): New function, split out from... (print_mnemonic_name): ...here. (print_comment): New function. (print_aarch64_insn): Call it. * aarch64-opc.c (aarch64_conds): Add SVE names. (aarch64_print_operand): Print alternative condition names in a comment. gas/ * config/tc-aarch64.c (opcode_lookup): Search for the end of a condition name, rather than assuming that it will have exactly 2 characters. (parse_operands): Likewise. * testsuite/gas/aarch64/alias.d: Add new condition-code comments to the expected output. * testsuite/gas/aarch64/beq_1.d: Likewise. * testsuite/gas/aarch64/float-fp16.d: Likewise. * testsuite/gas/aarch64/int-insns.d: Likewise. * testsuite/gas/aarch64/no-aliases.d: Likewise. * testsuite/gas/aarch64/programmer-friendly.d: Likewise. * testsuite/gas/aarch64/reloc-insn.d: Likewise. * testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s: New test. ld/ * testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments. * testsuite/ld-aarch64/weak-undefined.d: Likewise.
2016-09-21Fix misplaced ChangeLogRichard Sandiford2-11/+15
2016-09-21[AArch64][SVE 32/32] Add SVE testsRichard Sandiford15-0/+79428
This patch adds new tests for SVE. It also extends diagnostic.[sl] with checks for some inappropriate uses of MUL and MUL VL in base AArch64 instructions. gas/testsuite/ * gas/aarch64/diagnostic.s, gas/aarch64/diagnostic.l: Add tests for invalid uses of MUL VL and MUL in base AArch64 instructions. * gas/aarch64/sve-add.s, gas/aarch64/sve-add.d, gas/aarch64/sve-dup.s, gas/aarch64/sve-dup.d, gas/aarch64/sve-invalid.s, gas/aarch64/sve-invalid.d, gas/aarch64/sve-invalid.l, gas/aarch64/sve-reg-diagnostic.s, gas/aarch64/sve-reg-diagnostic.d, gas/aarch64/sve-reg-diagnostic.l, gas/aarch64/sve.s, gas/aarch64/sve.d: New tests.
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford3-1/+27
This patch adds the SVE instruction definitions and associated OP_* enum values. include/ * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro. (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi) (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P) (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops. opcodes/ * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB) (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ) (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD) (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU) (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB) (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR) (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS) (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB) (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD) (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD) (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD) (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD) (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD) (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD) (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS) (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD) (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD) (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD) (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD) (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD) (OP_SVE_XWU, OP_SVE_XXU): New macros. (aarch64_feature_sve): New variable. (SVE): New macro. (_SVE_INSN): Likewise. (aarch64_opcode_table): Add SVE instructions. * aarch64-opc.h (extract_fields): Declare. * aarch64-opc-2.c: Regenerate. * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops. * aarch64-asm-2.c: Regenerate. * aarch64-dis.c (extract_fields): Make global. (do_misc_decoding): Handle the new SVE aarch64_ops. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document the "sve" feature. * config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type. (get_reg_expected_msg): Handle it. (parse_operands): When parsing operands of an SVE instruction, disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP. (aarch64_features): Add an entry for SVE.
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford2-0/+11
SVE uses some new fields to store W, X and scalar FP registers. This patch adds corresponding operands. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd. (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd) (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core and FP register operands. * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm) (FLD_SVE_Vn): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. (aarch64_print_operand): Handle the new SVE core and FP register operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm-2.c: Likewise. * aarch64-dis-2.c: Likewise. gas/ * config/tc-aarch64.c (parse_operands): Handle the new SVE core and FP register operands.
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford2-3/+44
This patch adds support for the new SVE floating-point immediate operands. One operand uses the same 8-bit encoding as base AArch64, but in a different position. The others use a single bit to select between two values. One of the single-bit operands is a choice between 0 and 1, where 0 is not a valid 8-bit encoding. I think the cleanest way of handling these single-bit immediates is therefore to use the IEEE float encoding itself as the immediate value and select between the two possible values when encoding and decoding. As described in the covering note for the patch that added F_STRICT, we get better error messages by accepting unsuffixed vector registers and leaving the qualifier matching code to report an error. This means that we carry on parsing the other operands, and so can try to parse FP immediates for invalid instructions like: fcpy z0, #2.5 In this case there is no suffix to tell us whether the immediate should be treated as single or double precision. Again, we get better error messages by picking one (arbitrary) immediate size and reporting an error for the missing suffix later. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd. (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO) (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP immediate operands. * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind. * aarch64-opc.c (fields): Add corresponding entry. (operand_general_constraint_met_p): Handle the new SVE FP immediate operands. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two) (ins_sve_float_zero_one): New inserters. * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function. (aarch64_ins_sve_float_half_two): Likewise. (aarch64_ins_sve_float_zero_one): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two) (ext_sve_float_zero_one): New extractors. * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function. (aarch64_ext_sve_float_half_two): Likewise. (aarch64_ext_sve_float_zero_one): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (double_precision_operand_p): New function. (parse_operands): Use it to calculate the dp_p input to parse_aarch64_imm_float. Handle the new SVE FP immediate operands.
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford2-0/+32
This patch adds the new SVE integer immediate operands. There are three kinds: - simple signed and unsigned ranges, but with new widths and positions. - 13-bit logical immediates. These have the same form as in base AArch64, but at a different bit position. In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical immediate <limm> is not allowed to be a valid DUP immediate, since DUP is preferred over DUPM for constants that both instructions can handle. - a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}". In some contexts the operand is signed and in others it's unsigned. As an extension, we allow shifted immediates to be written as a single integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the shiftless form as the preferred disassembly, except for the special case of "#0, LSL #8" (a redundant encoding of 0). include/ * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd. (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM) (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM) (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED) (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED) (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5) (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6) (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3) (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8) (AARCH64_OPND_SVE_UIMM8_53): Likewise. (aarch64_sve_dupm_mov_immediate_p): Declare. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE integer immediate operands. * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5) (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9) (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. (operand_general_constraint_met_p): Handle the new SVE integer immediate operands. (aarch64_print_operand): Likewise. (aarch64_sve_dupm_mov_immediate_p): New function. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm) (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters. * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from... (aarch64_ins_limm): ...here. (aarch64_ins_inv_limm): New function. (aarch64_ins_sve_aimm): Likewise. (aarch64_ins_sve_asimm): Likewise. (aarch64_ins_sve_limm_mov): Likewise. (aarch64_ins_sve_shlimm): Likewise. (aarch64_ins_sve_shrimm): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm) (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors. * aarch64-dis.c (decode_limm): New function, split out from... (aarch64_ext_limm): ...here. (aarch64_ext_inv_limm): New function. (decode_sve_aimm): Likewise. (aarch64_ext_sve_aimm): Likewise. (aarch64_ext_sve_asimm): Likewise. (aarch64_ext_sve_limm_mov): Likewise. (aarch64_top_bit): Likewise. (aarch64_ext_sve_shlimm): Likewise. (aarch64_ext_sve_shrimm): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (parse_operands): Handle the new SVE integer immediate operands.
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford2-15/+68
This patch adds support for addresses of the form: [<base>, #<offset>, MUL VL] This involves adding a new AARCH64_MOD_MUL_VL modifier, which is why I split it out from the other addressing modes. For LD2, LD3 and LD4, the offset must be a multiple of the structure size, so for LD3 the possible values are 0, 3, 6, .... The patch therefore extends value_aligned_p to handle non-power-of-2 alignments. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd. (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL) (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL) (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise. (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL operands. * aarch64-opc.c (aarch64_operand_modifiers): Initialize the AARCH64_MOD_MUL_VL entry. (value_aligned_p): Cope with non-power-of-two alignments. (operand_general_constraint_met_p): Handle the new MUL VL addresses. (print_immediate_offset_address): Likewise. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl) (ins_sve_addr_ri_s9xvl): New inserters. * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function. (aarch64_ins_sve_addr_ri_s6xvl): Likewise. (aarch64_ins_sve_addr_ri_s9xvl): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl) (ext_sve_addr_ri_s9xvl): New extractors. * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function. (aarch64_ext_sve_addr_ri_s4xvl): Likewise. (aarch64_ext_sve_addr_ri_s6xvl): Likewise. (aarch64_ext_sve_addr_ri_s9xvl): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New parse_shift_modes. (parse_shift): Handle SHIFTED_MUL_VL. (parse_address_main): Add an imm_shift_mode parameter. (parse_address, parse_sve_address): Update accordingly. (parse_operands): Handle MUL VL addressing modes.
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford2-23/+237
This patch adds most of the new SVE addressing modes and associated operands. A follow-on patch adds MUL VL, since handling it separately makes the changes easier to read. The patch also introduces a new "operand-dependent data" field to the operand flags, based closely on the existing one for opcode flags. For SVE this new field needs only 2 bits, but it could be widened in future if necessary. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd. (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4) (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR) (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2) (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX) (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2) (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ) (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2) (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5) (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4) (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL) (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE address operands. * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14) (FLD_SVE_xs_22): New aarch64_field_kinds. (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags. (get_operand_specific_data): New function. * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14 and FLD_SVE_xs_22. (operand_general_constraint_met_p): Handle the new SVE address operands. (sve_reg): New array. (get_addr_sve_reg_name): New function. (aarch64_print_operand): Handle the new SVE address operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl) (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl) (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters. * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function. (aarch64_ins_sve_addr_rr_lsl): Likewise. (aarch64_ins_sve_addr_rz_xtw): Likewise. (aarch64_ins_sve_addr_zi_u5): Likewise. (aarch64_ins_sve_addr_zz): Likewise. (aarch64_ins_sve_addr_zz_lsl): Likewise. (aarch64_ins_sve_addr_zz_sxtw): Likewise. (aarch64_ins_sve_addr_zz_uxtw): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl) (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl) (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors. * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function. (aarch64_ext_sve_addr_ri_u6): Likewise. (aarch64_ext_sve_addr_rr_lsl): Likewise. (aarch64_ext_sve_addr_rz_xtw): Likewise. (aarch64_ext_sve_addr_zi_u5): Likewise. (aarch64_ext_sve_addr_zz): Likewise. (aarch64_ext_sve_addr_zz_lsl): Likewise. (aarch64_ext_sve_addr_zz_sxtw): Likewise. (aarch64_ext_sve_addr_zz_uxtw): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New register types. (get_reg_expected_msg): Handle them. (aarch64_addr_reg_parse): New function, split out from aarch64_reg_parse_32_64. Handle Z registers too. (aarch64_reg_parse_32_64): Call it. (parse_address_main): Add base_qualifier, offset_qualifier, base_type and offset_type parameters. Handle SVE base and offset registers. (parse_address): Update call to parse_address_main. (parse_sve_address): New function. (parse_operands): Parse the new SVE address operands.
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford2-1/+49
Some SVE instructions count the number of elements in a given vector pattern and allow a scale factor of [1, 16] to be applied to the result. This scale factor is written ", MUL #n", where "MUL" is a new operator. E.g.: UQINCD X0, POW2, MUL #2 This patch adds support for this kind of operand. All existing operators were shifts of some kind, so there was a natural range of [0, 63] regardless of context. This was then narrowered further by later checks (e.g. to [0, 31] when used for 32-bit values). In contrast, MUL doesn't really have a natural context-independent range. Rather than pick one arbitrarily, it seemed better to make the "shift" amount a full 64-bit value and leave the range test to the usual operand-checking code. I've rearranged the fields of aarch64_opnd_info so that this doesn't increase the size of the structure (although I don't think its size is critical anyway). include/ * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New aarch64_opnd. (AARCH64_MOD_MUL): New aarch64_modifier_kind. (aarch64_opnd_info): Make shifter.amount an int64_t and rearrange the fields. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind. * aarch64-opc.c (fields): Add a corresponding entry. (set_multiplier_out_of_range_error): New function. (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL. (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (print_register_offset_address): Use PRIi64 to print the shift amount. (aarch64_print_operand): Likewise. Handle AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_scale): New inserter. * aarch64-asm.c (aarch64_ins_sve_scale): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_scale): New inserter. * aarch64-dis.c (aarch64_ext_sve_scale): New function. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode. (parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other shift modes. Skip range tests for AARCH64_MOD_MUL. (process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (parse_operands): Likewise.
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