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2024-06-12aarch64: add Branch Record Buffer extension instructionsClaudio Bantaloukas11-0/+64
The FEAT_BRBE extension provides two aliases of sys: - brb iall (Invalidates all Branch records in the Branch Record Buffer) - brb inj (Injects the Branch Record held in BRBINFINJ_EL1, BRBSRCINJ_EL1, and BRBTGTINJ_EL1 into the Branch Record Buffer) This patch adds: - the feature option "brbe" that must be added for the aliases to be available - a new operand flag AARCH64_OPND_Rt_IN_SYS_ALIASES that warns in a comment when Rt is set to the non default value 0b11111 (it is constrained unpredictable whether the instruction is undefined or behaves as if the Rt field is set to 0b11111). - a new operand flag AARCH64_OPND_BRBOP that encodes and decodes Op2 values from bit 5 - support for the two brb aliases above See: - https://developer.arm.com/documentation/ddi0602/2024-03/Base-Instructions/BRB--Branch-Record-Buffer--an-alias-of-SYS-?lang=en - https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-INJ--Branch-Record-Injection-into-the-Branch-Record-Buffer?lang=en - https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-IALL--Invalidate-the-Branch-Record-Buffer?lang=en
2024-06-12RISC-V: Support S[sm]csrind extension csrs.Jiawei10-36/+549
This patch supports RISC-V Smcsrind/Sscsrind privilege extension csrs. Reuse csr 'smselect/siselect', 'mireg/sireg' and 'vsiselect,vsireg' csrs in Smaia/Ssaia extension. bfd/ChangeLog: * elfxx-riscv.c: New extensions. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (enum riscv_csr_class): New extensions. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extensions. include/ChangeLog: * opcode/riscv-opc.h (CSR_MIREG2): New csr. (CSR_MIREG3): Ditto. (CSR_MIREG4): Ditto. (CSR_MIREG5): Ditto. (CSR_MIREG6): Ditto. (CSR_SIREG2): Ditto. (CSR_SIREG3): Ditto. (CSR_SIREG4): Ditto. (CSR_SIREG5): Ditto. (CSR_SIREG6): Ditto. (CSR_VSIREG2): Ditto. (CSR_VSIREG3): Ditto. (CSR_VSIREG4): Ditto. (CSR_VSIREG5): Ditto. (CSR_VSIREG6): Ditto. (DECLARE_CSR): Ditto.
2024-06-11MIPS/opcodes: Add MIPS Allegrex DBREAK instructionDavid Guillen Fandos2-1/+3
This complements the debug instruction set and uses the same encoding as the VR5400/VR5500 devices.
2024-06-11MIPS/opcodes: Exclude trap instructions for MIPS AllegrexDavid Guillen Fandos4-0/+30
These instructions are not supported by the target even though they are part of the MIPS II specification.
2024-06-10aarch64: warn on unpredictable results for new rcpc3 instructionsMatthieu Longo6-26/+306
The previous patch for the feature rcpc3 introduced 4 new operations (ldiapp, stilp, ldapr, stlr). The specification mentions some cases of inputs causing unpredictable results. gas currently fails to diagnose them, and does not emit warnings. Even if the instruction encoding is valid, the developer probably wants to know for those cases that the instruction won't have the expected effect. - ldiapp & stilp: * unpredictable load pair transfer with register overlap * unpredictable transfer with writeback - ldapr & stlr: * unpredictable transfer with writeback This patch also completes the existing relevant tests.
2024-06-10Revert "MIPS/Allegrex: Exclude trap instructions"Maciej W. Rozycki3-27/+0
This reverts commit a2e71b281a9365872451a157767e03a2e89ddaad.
2024-06-10Revert "MIPS/Allegrex: Enable dbreak instruction"Maciej W. Rozycki2-3/+1
This reverts commit c41020942b94ea7c5a58de4fed644826e8f0b509.
2024-06-10MIPS/Allegrex: Enable dbreak instructionDavid Guillen Fandos2-1/+3
2024-06-10MIPS/Allegrex: Exclude trap instructionsDavid Guillen Fandos3-0/+27
These instructions are not supported by the target even though they are part of the MIPS II specification.
2024-06-10x86/APX: convert ZU to operand constraintJan Beulich1-1/+5
Extremely rarely used attributes are inefficient when represented by a separate attribute. Convert it to an operand constraint, as already suggested during review. The collision with RegKludge is pretty simple to resolve.
2024-06-10x86: disassembler macro for condition codeJan Beulich6-276/+276
Both CMPccXADD and APX'es {,CF}CMOVcc have almost identical entries replicated 16 times each. Fold those to just one each by introducing a %CC macro. (Note that the recording of ->condition_code in print_insn() is merely for completeness for now; it's not used as long as only VEX/EVEX encodings would consume it.) This then also renders condition codes printed consistent across all respective insns; CMPxxXADD had a number of outliers so far.
2024-06-10x86/APX: support extended SETcc formJan Beulich3-0/+9
As indicated during review, spelling/readability-wise setz %eax is easier than setzuz %al _and_ properly specifies the full register that's being modified. Permit that form to be used, even if the spec writers are unwilling to formally mention it. While there also correct the non-ZU EVEX form: That ought to also permit memory operands.
2024-06-10gas: extend \+ support to .reptJan Beulich6-7/+93
PR gas/31752 While not quite as macro-like as .irp / .irpc, this perhaps benefits from supporting \+ even more than those: It allows, where desired, to get away without maintaining an explicit count variable in source code. Keep .rep (and custom per-arch uses of s_rept() / do_repeat()) behavior unaltered.
2024-06-10autoupdate: regen after replacing obsolete macrosMatthieu Longo1-4/+2
2024-06-10autoupdate: add square brackets around arguments of AC_INITMatthieu Longo1-1/+1
https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.72/autoconf.html#index-AC_005fINIT-2
2024-06-10autoupdate: replace obsolete macros AC_AIX, AC_MINIX, and AC_GNU_SOURCEMatthieu Longo1-1/+0
- AC_AIX, AC_MINIX, and AC_GNU_SOURCE by AC_USE_SYSTEM_EXTENSIONS https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.72/autoconf.html#index-AC_005fAIX https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.72/autoconf.html#index-AC_005fMINIX-1 https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.72/autoconf.html#index-AC_005fGNU_005fSOURCE-1
2024-06-06arm: fix testsuite fallout on arm-elf and arm-nto from FPA removalRichard Earnshaw5-3/+7
Removing FPA means that in some cases we default to 'no-fpu' in the assembler when previously we would have picked FPA-format floating numbers. This patch fixes the testsuite fallout on a couple of targets that are affected by this change. Where possible we do this by adding an option to set the floating-point format, but for bad-bss we just skip the test.
2024-06-06RISC-V: Add support for Zvfbfwma extensionXiao Zeng4-0/+22
This implements the Zvfbfwma extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfwma---vector-bf16-widening-mul-add> 1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension." 1.1 In Embedded Processor: Zvfbfwma -> Zvfbfmin -> Zve32f 1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V 1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin 2 Depending on different usage scenarios, the Zvfbfwma extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. This is consistent with the processing strategy in Zvfbfmin. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=38dd4e26e07c6be7cf4d169141ee4f3a03f3a09d> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfwma. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zvfbfwma.d: New test. * testsuite/gas/riscv/zvfbfwma.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF): Define. (MASK_VFWMACCBF16_VF): Ditto. (MATCH_VFWMACCBF16_VV): Ditto. (MASK_VFWMACCBF16_VV): Ditto. (DECLARE_INSN): New declarations for Zvfbfwma. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZVFBFWMA opcodes/ChangeLog: * riscv-opc.c: Add Zvfbfwma instructions.
2024-06-06RISC-V: Add support for Zvfbfmin extensionXiao Zeng4-0/+22
This implements the Zvfbfmin extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts> Depending on different usage scenarios, the Zvfbfmin extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zvfbfmin.d: New test. * testsuite/gas/riscv/zvfbfmin.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define. (MASK_VFNCVTBF16_F_F_W): Ditto. (MATCH_VFWCVTBF16_F_F_V): Ditto. (MASK_VFWCVTBF16_F_F_V): Ditto. (DECLARE_INSN): New declarations for Zvfbfmin. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZVFBFMIN opcodes/ChangeLog: * riscv-opc.c: Add Zvfbfmin instructions.
2024-06-06RISC-V: Add support for Zfbfmin extensionXiao Zeng4-0/+20
This implements the Zfbfmin extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfbfmin---scalar-bf16-converts> 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and FMV.H.X instructions as defined in the Zfh extension. 2 The Zfhmin extension includes the following instructions from the Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zfh.adoc> 3 Zfhmin extension depend on 'F'. 4 Simply put, just make Zfbfmin dependent on Zfhmin. Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and FMV.H.X instructions an independent extension to achieve precise dependency relationships for the Zfbfmin. 5 For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zfbfmin.d: New test. * testsuite/gas/riscv/zfbfmin.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define. (MASK_FCVT_BF16_S): Ditto. (MATCH_FCVT_S_BF16): Ditto. (MASK_FCVT_S_BF16): Ditto. (DECLARE_INSN): New declarations for Zfbfmin. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN. opcodes/ChangeLog: * riscv-opc.c: Add Zfbfmin instructions.
2024-06-05arm: minor documentation cleanup given removal of FPARichard Earnshaw1-3/+0
The use in the documentation of .save for an FPA instruction is no-longer relevant, so remove it.
2024-06-05arm: remove disassembly support for the FPA co-processorRichard Earnshaw2-6/+6
Remove the FPA support from the disassembler. This entails a couple of testsuite fixes where we were (probably incorrectly) disassembling a generic co-processor instruction using the legacy FPA opcodes.
2024-06-05arm: remove FPA instructions from assemblerRichard Earnshaw1-699/+0
These can no-longer be generated as the options to reach them have now gone. So remove the parsing support for FPA instructions.
2024-06-05arm: remove options to select the FPARichard Earnshaw2-23/+2
Remove the command-line options to choose the FPA (or FPE - an emulated FPA). From this point on it should be impossible to assemble the old FPA instructions.
2024-06-05arm: change default FPUs from FPA to noneRichard Earnshaw1-62/+63
Change the cases where the default FPU was FPA to none. This should ensure that any code that used settings to pick the floating-point order will not silently produce a different output. The options that explicitly set the FPA remain for the moment.
2024-06-05arm: redirect fp constant data directives through a wrapperRichard Earnshaw12-10/+55
Assembler directives such as .float, or .double are handled by generic code, but on Arm, their output can vary depeding on the type of FPU begin targetted. When we remove FPA support we don't want to silently generate different code for processors that previously defaulted to the FPA, so redirect these directives through a wrapper function that checks the FPU is enabled; we use the legacy -mno-fpu in the test to catch this. Also fix a few tests so that they won't start to fail on targets (eg arm-wince-pe) where there is no default format for the FPU and we pick this from the default processor type.
2024-06-05arm: adjust FPU selection logicRichard Earnshaw1-9/+2
The logic here seems to be overly complex, so simplify it a bit. One particular problem was that using the legacy -mno-fpu option was not working properly, as this has all the feature bits set to zero causing the code to then pick a different FPU as the default. Fix this by only selecting an FPU as a fallback if the code has not otherwise selected one: there was only one route by which this could happen. This patch is really a pre-cursor to the following one where we want to make no-fpu internally a fall-back position for some legacy processors where previously we would have dropped back to the FPA.
2024-06-05arm: default to softvfp on armv6 or later coresRichard Earnshaw1-17/+17
From armv6 onwards a lot of cores started to come with a physical VFP implementation; but many still did not and in some cases there are both variants. For the cores that lacked a physical VFP we would fall back to FPU_NONE if the platform/ABI did not mandate something else. To make matters worse, FPU_NONE is internal state used to imply soft-fpa (ie a mixed-endian double format), so any use of .double in hand-written assembly is almost certainly generating incorrect output. That's undesirable, all these cores should really default to a softvfp model.
2024-06-05arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFPRichard Earnshaw5-58/+96
FPU_ARCH_VFP has always meant VFP floating-point format (natural FP word order) but without any VFP instructions. But the name FPU_ARCH_VFP is potentially confusing. This patch just changes the name to make the meaning clearer.
2024-06-05arm: remove FPA related testsRichard Earnshaw27-1858/+119
Remove various tests of the FPA instruction set and relocation support.
2024-06-05RISC-V: Tidy vendor core-v extension gas testcasesNelson Chu146-1629/+1393
1. Combined testcases into one if they use same extention name. 2. Likewise for the fail testcases. 3. Renamed with x-cv prefix, just like what other vendors did. gas/ * testsuite/gas/riscv/cv-alu-*: Combined and renamed to x-cv-alu. Likewise for fail testcases, to x-cv-alu-fail*. * testsuite/gas/riscv/cv-bi-*: Likewise, but renamed to x-cv-bi and x-cv-bi-fail. * testsuite/gas/riscv/cv-elw-*: Likewise, but renamed to x-cv-elw and x-cv-elw-fail. * testsuite/gas/riscv/cv-mac-*: Likewise, but renamed to x-cv-mac and x-cv-mac-fail. * testsuite/gas/riscv/cv-mem-*: Likewise, but renamed to x-cv-mem and x-cv-mem-fail.
2024-06-05RISC-V: Add support for XCVmem extension in CV32E40PMary Bennett68-0/+730
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvmem` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Note XCVmem as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-mem-fail-march.d: New test. * testsuite/gas/riscv/cv-mem-fail-march.l: New test. * testsuite/gas/riscv/cv-mem-fail-march.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-mem-lbpost.d: New test. * testsuite/gas/riscv/cv-mem-lbpost.s: New test. * testsuite/gas/riscv/cv-mem-lbrr.d: New test. * testsuite/gas/riscv/cv-mem-lbrr.s: New test. * testsuite/gas/riscv/cv-mem-lbrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lbrrpost.s: New test. * testsuite/gas/riscv/cv-mem-lbupost.d: New test. * testsuite/gas/riscv/cv-mem-lbupost.s: New test. * testsuite/gas/riscv/cv-mem-lburr.d: New test. * testsuite/gas/riscv/cv-mem-lburr.s: New test. * testsuite/gas/riscv/cv-mem-lburrpost.d: New test. * testsuite/gas/riscv/cv-mem-lburrpost.s: New test. * testsuite/gas/riscv/cv-mem-lhpost.d: New test. * testsuite/gas/riscv/cv-mem-lhpost.s: New test. * testsuite/gas/riscv/cv-mem-lhrr.d: New test. * testsuite/gas/riscv/cv-mem-lhrr.s: New test. * testsuite/gas/riscv/cv-mem-lhrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lhrrpost.s: New test. * testsuite/gas/riscv/cv-mem-lhupost.d: New test. * testsuite/gas/riscv/cv-mem-lhupost.s: New test. * testsuite/gas/riscv/cv-mem-lhurr.d: New test. * testsuite/gas/riscv/cv-mem-lhurr.s: New test. * testsuite/gas/riscv/cv-mem-lhurrpost.d: New test. * testsuite/gas/riscv/cv-mem-lhurrpost.s: New test. * testsuite/gas/riscv/cv-mem-lwpost.d: New test. * testsuite/gas/riscv/cv-mem-lwpost.s: New test. * testsuite/gas/riscv/cv-mem-lwrr.d: New test. * testsuite/gas/riscv/cv-mem-lwrr.s: New test. * testsuite/gas/riscv/cv-mem-lwrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lwrrpost.s: New test. * testsuite/gas/riscv/cv-mem-sbpost.d: New test. * testsuite/gas/riscv/cv-mem-sbpost.s: New test. * testsuite/gas/riscv/cv-mem-sbrr.d: New test. * testsuite/gas/riscv/cv-mem-sbrr.s: New test. * testsuite/gas/riscv/cv-mem-sbrrpost.d: New test. * testsuite/gas/riscv/cv-mem-sbrrpost.s: New test. * testsuite/gas/riscv/cv-mem-shpost.d: New test. * testsuite/gas/riscv/cv-mem-shpost.s: New test. * testsuite/gas/riscv/cv-mem-shrr.d: New test. * testsuite/gas/riscv/cv-mem-shrr.s: New test. * testsuite/gas/riscv/cv-mem-shrrpost.d: New test. * testsuite/gas/riscv/cv-mem-shrrpost.s: New test. * testsuite/gas/riscv/cv-mem-swpost.d: New test. * testsuite/gas/riscv/cv-mem-swpost.s: New test. * testsuite/gas/riscv/cv-mem-swrr.d: New test. * testsuite/gas/riscv/cv-mem-swrr.s: New test. * testsuite/gas/riscv/cv-mem-swrrpost.d: New test. * testsuite/gas/riscv/cv-mem-swrrpost.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvmem string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVmem. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVmem. (enum riscv_insn_class): Add the XCVmem instruction class. opcodes/ChangeLog: * riscv-opc.c: Add XCVmem instructions.
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett19-1/+102
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> Nazareno Bruschi <nazareno.bruschi@embecosm.com> Lin Sinan include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbi as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-bi-beqimm.d: New test. * testsuite/gas/riscv/cv-bi-beqimm.s: New test. * testsuite/gas/riscv/cv-bi-bneimm.d: New test. * testsuite/gas/riscv/cv-bi-bneimm.s: New test. * testsuite/gas/riscv/cv-bi-fail-march.d: New test. * testsuite/gas/riscv/cv-bi-fail-march.l: New test. * testsuite/gas/riscv/cv-bi-fail-march.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvbi string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add disassembly for new operand. * riscv-opc.c: Add XCVbi instructions.
2024-06-05RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett10-0/+191
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Note XCVelw as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-elw-fail.d: New test. * testsuite/gas/riscv/cv-elw-fail.l: New test. * testsuite/gas/riscv/cv-elw-fail.s: New test. * testsuite/gas/riscv/cv-elw-fail-march.d: New test. * testsuite/gas/riscv/cv-elw-fail-march.l: New test. * testsuite/gas/riscv/cv-elw-fail-march.s: New test. * testsuite/gas/riscv/cv-elw-pass.d: New test. * testsuite/gas/riscv/cv-elw-pass.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvelw string. opcodes/ChangeLog: * riscv-opc.c: (riscv_opcode) Add event load instructions. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK instruction opcode macros. * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.
2024-06-04LoongArch: Make align symbol be in same section with alignment directivemengqinggang5-4/+103
R_LARCH_ALIGN (psABI v2.30) requires a symbol index. The symbol is only created at the first time to handle alignment directive. This means that all other sections may use this symbol. If the section of this symbol is discarded, there may be problems. Search it in its own section. Remove elf_backend_data.is_rela_normal() function added at commit daeda14191c. Co-authored-by: Jinyang He <hejinyang@loongson.cn> Reported-by: WANG Xuerui <git@xen0n.name> Link: https://lore.kernel.org/loongarch/2abbb633-a10e-71cc-a5e1-4d9e39074066@loongson.cn/T/#t
2024-06-04arm: testsuite: fix msdos line endings in testsRichard Earnshaw2-18/+18
A couple of the tests in the testsuite were at some point in the past committed with DOS-style CRLF line endings. This potentially causes email problems if the tests are touched in the middle of a large patch series so convert them to standard Un*x line endings.
2024-05-31aarch64, testsuite: avoid regexes in opcode fieldClaudio Bantaloukas2-493/+493
Some dejagnu files use regexes rather than specific encodings. This change replaces them with the explicit encodings we expect. Tested against aarch64-unknown-linux-gnu and aarch64-none-elf.
2024-05-31gas, aarch64: Fixes in texi and tests following faminmax and lut changessaurabh.jha@arm.com4-162/+162
Making two cleanups that came out of the comments from my previous patches: 1. Fixing `c-aarch64.texi` file so that the AArch64 architecture extensions are ordered alphabetically. 2. Fixing faminmax test cases so that they follow the existing test conventions.
2024-05-31x86: reduce check_{byte,word,long,qword}_reg() overheadJan Beulich1-4/+15
These run after template matching. Therefore it is quite pointless for them to check all operands, when operand sizes matching across operands is already known. Exit the loops early in such cases. In check_byte_reg() also drop a long-stale part of a comment.
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich33-157/+117
Except for very few insns mnemonic suffixes aren't permitted in Intel syntax. Warn about such for now, indicating that they will be outright refused down the road. While fiddling with testcases to address fallout, drop a few things which should never have been tested as valid Intel syntax. Also add a previously missing line to simd-suffix.d.
2024-05-29x86/Intel: SHLD/SHRD have dual meaningJan Beulich4-2/+79
Since we uniformly permit D suffixes in Intel mode whenever in AT&T mode an L suffix may be used, we need to be consistent with this. Take the easy route, despite that still leading to an anomaly which is also visible from the new testcase: shld eax, ecx, 1 shld eax, ecx, cl can mean two things with APX: SHL with a D suffix in NDD EVEX encoding, or the traditional SHLD in legacy encoding.
2024-05-29PR31796, Internal error in write_function_pdata at obj-coff-sehAlan Modra1-2/+22
PR31796 is the result of lack of aarch64 support in obj-coff-seh.c. Nick fixed this with commit 73c8603c3f. Make the seh support consistently warn in future if some archictecture is missing, rather than giving internal errors. PR 31796 * config/obj-coff-seh.c (verify_target): New function. (obj_coff_seh_handler, obj_coff_seh_endproc, obj_coff_seh_proc), (obj_coff_seh_endprologue): Use it.
2024-05-28gas, aarch64: Add SVE2 lut extensionsaurabh.jha@arm.com9-1/+464
Introduces instructions for the SVE2 lut extension for AArch64. They are documented in the following links: * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en These instructions use new SVE2 vector operands. They are called SVE_Zm1_23_INDEX, SVE_Zm2_22_INDEX, and Zm3_12_INDEX and they have 1 bit, 2 bit, and 3 bit indices respectively. The lsb and width of these new operands are the same as many existing operands but the convention is to give different names to fields that serve different purpose so we introduced new fields in aarch64-opc.c and aarch64-opc.h. We made a design choice for the second operand of the halfword variant of luti4 with two register tables. We could have either defined a new operand, like SVE_Znx2, or we could have use the existing operand SVE_ZnxN. With the new operand, we would need to implement constraints on register lists based on either operand or opcode flag. With existing operand, we could just existing constraint checks using opcode flag. We chose the second approach and went with SVE_ZnxN and added opcode flag to enforce lengths of vector register list operands. This way, we can reuse the existing constraint check logic.
2024-05-28gas, aarch64: Add AdvSIMD lut extensionsaurabh.jha@arm.com10-0/+499
Introduces instructions for the Advanced SIMD lut extension for AArch64. They are documented in the following links: * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en These instructions needed definition of some new operands. We will first discuss operands for the third operand of the instructions and then discuss a vector register list operand needed for the second operand. The third operands are vectors with bit indices and without type qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12 and they have 1 bit, 2 bit, and 3 bit indices respectively. For these new operands, we defined new parsing case branch. The lsb and width of these operands are the same as many existing but the convention is to give different names to fields that serve different purpose so we introduced new fields in aarch64-opc.c and aarch64-opc.h for these new operands. For the second operand of these instructions, we introduced a new operand called LVn_LUT. This represents a vector register list with stride 1. We defined new inserter and extractor for this new operand and it is encoded in FLD_Rn. We are enforcing the number of registers in the reglist using opcode flag rather than operand flag as this is what other SIMD vector register list operands are doing. The disassembly also uses opcode flag to print the correct number of registers.
2024-05-28Fix typo in assembler documentationNick Clifton1-1/+1
2024-05-28Fix: internal error in write_function_pdata at obj-coff-sehNick Clifton1-0/+5
PR 31796
2024-05-28RISC-V: Fix U insn; replace opcode6 with opcode7 in gas/doc/c-riscv.texiJavier Mora1-22/+22
The type U RISC-V instruction format in gas/doc/c-riscv.texi shows the bit arrangement of the simm20 immediate that belongs to the J type; It should be just `simm20[19:0]`. The current behavior of `gas` matches the proposed documentation change. Additionally, the opcode is called `opcode6` despite of having 7 bits. Rename it to `opcode7`. gas/ * doc/c-riscv.texi: Fix U type, and replace opcode6 with opcode7.
2024-05-24Re: LoongArch: gas: Adjust DWARF CIE alignment factorsAlan Modra1-22/+22
Adjust the gas testsuite to suit commit de203ed568f6. * testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d: Expect data alignment of -8. Tidy.
2024-05-24gas: extend \+ support to .irp / .irpcJan Beulich6-23/+24
PR gas/31752 These are effectively macro-like, without any separate macro definition. They already support \@, so they would better also support \+. This allows, where desired, to get away without maintaining an explicit count variable in source code. With this the recently introduced testcase doesn't need any xfails anymore.
2024-05-24gas: adjust handling of quotes for .irpcJan Beulich5-21/+40
The present handling of inner double quotes can lead to very strange diagnostics. Follow one of the two possible interpretations of the doc: @dots{} referring to possibly multiple white space separated @var{values}, each of which may be quoted. The original implementation, prior to 465e5617233f ("PR gas/3856"), hints at the other possible interpretation: When quoted there's only a single @var{values}, with inner quotes taken as ordinary characters. That, however, seems overall less useful to me. While touching the documentation, mirror the (inverse) spelling correction (@section line inconsistent with actual description) to .irp as well.
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