aboutsummaryrefslogtreecommitdiff
path: root/gas
AgeCommit message (Collapse)AuthorFilesLines
2018-11-13[ARM] Improve indentation of ARM architecture declarationsThomas Preud'homme2-51/+55
This commit cleans up indentation of ARM architecture declaration, namely entries of arm_archs and definition of macros ARM_EXT_*, ARM_AEXT_*, ARM_AEXT2_*, FPU_EXT_*, FPU_ARCH_* and ARM_ARCH_*. It also gets rid of unused ARM_ARCH_V6M-ONLY and merge AEM_AEXT_V6M_ONLY in ARM_AEXT_V6M now sole user. gas/ 2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (arm_archs): Reindent. include/ 2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * opcode/arm.h (ARM_AEXT_V6M_ONLY): Merge into its use in ARM_AEXT_V6M. (ARM_ARCH_V6M_ONLY): Remove. (ARM_EXT_V1, ARM_EXT_V2, ARM_EXT_V2S, ARM_EXT_V3, ARM_EXT_V3M, ARM_EXT_V4, ARM_EXT_V4T, ARM_EXT_V5, ARM_EXT_V5T, ARM_EXT_V5ExP, ARM_EXT_V5E, ARM_EXT_V5J, ARM_EXT_V6, ARM_EXT_V6K, ARM_EXT_V8, ARM_EXT_V6T2, ARM_EXT_DIV, ARM_EXT_V5E_NOTM, ARM_EXT_V6_NOTM, ARM_EXT_V7, ARM_EXT_V7A, ARM_EXT_V7R, ARM_EXT_V7M, ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR, ARM_EXT_V6_DSP, ARM_EXT_MP, ARM_EXT_SEC, ARM_EXT_OS, ARM_EXT_ADIV, ARM_EXT_VIRT, ARM_EXT2_PAN, ARM_EXT2_V8_2A, ARM_EXT2_V8M, ARM_EXT2_ATOMICS, ARM_EXT2_V6T2_V8M, ARM_EXT2_FP16_INST, ARM_EXT2_V8M_MAIN, ARM_EXT2_RAS, ARM_EXT2_V8_3A, ARM_EXT2_V8A, ARM_EXT2_V8_4A, ARM_EXT2_FP16_FML, ARM_EXT2_V8_5A, ARM_EXT2_SB, ARM_EXT2_PREDRES, ARM_CEXT_XSCALE, ARM_CEXT_MAVERICK, ARM_CEXT_IWMMXT, ARM_CEXT_IWMMXT2, FPU_ENDIAN_PURE, FPU_ENDIAN_BIG, FPU_FPA_EXT_V1, FPU_FPA_EXT_V2, FPU_MAVERICK, FPU_VFP_EXT_V1xD, FPU_VFP_EXT_V1, FPU_VFP_EXT_V2, FPU_VFP_EXT_V3xD, FPU_VFP_EXT_V3, FPU_NEON_EXT_V1, FPU_VFP_EXT_D32, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, FPU_VFP_EXT_FMA, FPU_VFP_EXT_ARMV8, FPU_NEON_EXT_ARMV8, FPU_CRYPTO_EXT_ARMV8, CRC_EXT_ARMV8, FPU_VFP_EXT_ARMV8xD, FPU_NEON_EXT_RDMA, FPU_NEON_EXT_DOTPROD, ARM_AEXT_V1, ARM_AEXT_V2, ARM_AEXT_V2S, ARM_AEXT_V3, ARM_AEXT_V3M, ARM_AEXT_V4xM, ARM_AEXT_V4, ARM_AEXT_V4TxM, ARM_AEXT_V4T, ARM_AEXT_V5xM, ARM_AEXT_V5, ARM_AEXT_V5TxM, ARM_AEXT_V5T, ARM_AEXT_V5TExP, ARM_AEXT_V5TE, ARM_AEXT_V5TEJ, ARM_AEXT_V6, ARM_AEXT_V6K, ARM_AEXT_V6Z, ARM_AEXT_V6KZ, ARM_AEXT_V6T2, ARM_AEXT_V6KT2, ARM_AEXT_V6ZT2, ARM_AEXT_V6KZT2, ARM_AEXT_V7_ARM, ARM_AEXT_V7A, ARM_AEXT_V7VE, ARM_AEXT_V7R, ARM_AEXT_NOTM, ARM_AEXT_V6M_ONLY, ARM_AEXT_V6M, ARM_AEXT_V6SM, ARM_AEXT_V7M, ARM_AEXT_V7, ARM_AEXT_V7EM, ARM_AEXT_V8A, ARM_AEXT2_V8A, ARM_AEXT2_V8_1A, ARM_AEXT2_V8_2A, ARM_AEXT2_V8_3A, ARM_AEXT2_V8_4A, ARM_AEXT2_V8_5A, ARM_AEXT_V8M_BASE, ARM_AEXT_V8M_MAIN, ARM_AEXT_V8M_MAIN_DSP, ARM_AEXT2_V8M, ARM_AEXT2_V8M_BASE, ARM_AEXT2_V8M_MAIN, ARM_AEXT2_V8M_MAIN_DSP, ARM_AEXT_V8R, ARM_AEXT2_V8R, FPU_VFP_V1xD, FPU_VFP_V1, FPU_VFP_V2, FPU_VFP_V3D16, FPU_VFP_V3, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4, FPU_VFP_V4_SP_D16, FPU_VFP_V5D16, FPU_VFP_ARMV8, FPU_NEON_ARMV8, FPU_CRYPTO_ARMV8, FPU_VFP_HARD, FPU_FPA, FPU_ARCH_VFP, FPU_ARCH_FPE, FPU_ARCH_FPA, FPU_ARCH_VFP_V1xD, FPU_ARCH_VFP_V1, FPU_ARCH_VFP_V2, FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_NEON_V1, FPU_ARCH_VFP_V3_PLUS_NEON_V1, FPU_ARCH_NEON_FP16, FPU_ARCH_VFP_HARD, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16, FPU_ARCH_VFP_V4_SP_D16, FPU_ARCH_VFP_V5D16, FPU_ARCH_VFP_V5_SP_D16, FPU_ARCH_NEON_VFP_V4, FPU_ARCH_VFP_ARMV8, FPU_ARCH_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD, ARCH_CRC_ARMV8, FPU_ARCH_NEON_VFP_ARMV8_1, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1, FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, ARM_ARCH_V1, ARM_ARCH_V2, ARM_ARCH_V2S, ARM_ARCH_V3, ARM_ARCH_V3M, ARM_ARCH_V4xM, ARM_ARCH_V4, ARM_ARCH_V4TxM, ARM_ARCH_V4T, ARM_ARCH_V5xM, ARM_ARCH_V5, ARM_ARCH_V5TxM, ARM_ARCH_V5T, ARM_ARCH_V5TExP, ARM_ARCH_V5TE, ARM_ARCH_V5TEJ, ARM_ARCH_V6, ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6KZ, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, ARM_ARCH_V6KZT2, ARM_ARCH_V6M, ARM_ARCH_V6SM, ARM_ARCH_V7, ARM_ARCH_V7A, ARM_ARCH_V7VE, ARM_ARCH_V7R, ARM_ARCH_V7M, ARM_ARCH_V7EM, ARM_ARCH_V8A, ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8M_BASE, ARM_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN_DSP, ARM_ARCH_V8R): Reindent.
2018-11-12[BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging ↵Sudakshina Das4-0/+68
Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch adds all the data cache instructions that are part of this extension: - DC IGVAC, Xt - DC IGSW, Xt - DC CGSW, Xt - DC CIGSW, Xt - DC CGVAC, Xt - DC CGVAP, Xt - DC CGVADP, Xt - DC CIGVAC, Xt - DC GVA, Xt - DC IGDVAC, Xt - DC IGDSW, Xt - DC CGDSW, Xt - DC CIGDSW, Xt - DC CGDVAC, Xt - DC CGDVAP, Xt - DC CGDVADP, Xt - DC CIGDVAC, Xt - DC GZVA, Xt *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): New entries for IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA, IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP, CIGDVAC and GZVA. (aarch64_sys_ins_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA, IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP, CIGDVAC and GZVA with DC. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging ExtensionSudakshina Das4-1/+75
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch adds all the system registers that are part of this extension and are accessible via the MRS/MSR instructions: - TCO - TFSRE0_SL1 - TFSR_EL1 - TFSR_EL2 - TFSR_EL3 - TFSR_EL12 - RGSR_EL1 - GCR_EL1 TCO is also accessible with the MSR(immediate) instruction. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs): New entries for TCO, TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and GCR_EL1. (aarch64_sys_reg_supported_p): New check for above. (aarch64_pstatefields): New entry for TCO. (aarch64_pstatefield_supported_p): New check for above. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and GCR_EL1 MSR and MRS. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das6-3/+70
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Bulk Allocation Tag instructions from MTE. These are the following instructions added in this patch: - LDGV <Xt>, [<Xn|SP>]! - STGV <Xt>, [<Xn|SP>]! This needed a new kind of operand for the new addressing [<Xn|SP>]! since this has no offset and only takes a pre-indexed version. Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced. (AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does not allow writeback). We also needed new encoding and decoding functions to be able to do the same. where <Xt> : Is the 64-bit destination GPR. <Xn|SP> : Is the 64-bit first source GPR or Stack pointer. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2. (aarch64_insn_class): Add ldstgv_indexed. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-asm.c (aarch64_ins_addr_simple_2): New. * aarch64-asm.h (ins_addr_simple_2): Declare the above. * aarch64-dis.c (aarch64_ext_addr_simple_2): New. * aarch64-dis.h (ext_addr_simple_2): Declare the above. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed. (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv. (AARCH64_OPERANDS): Define ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it. (warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das5-1/+33
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag Getting instruction from Memory Tagging Extension. - LDG <Xt>, [<Xn|SP>, #<simm>] where <Xt> : Is the 64-bit destination GPR. <Xn|SP> : Is the 64-bit first source GPR or Stack pointer. <simm> : Is the optional signed immediate offset, a multiple of 16 in the range of -4096 and 4080, defaulting to 0. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (QL_LDG): New. (aarch64_opcode_table): Add ldg. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldg. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging ↵Sudakshina Das6-0/+140
Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag setting instructions from MTE which consists of the following instructions: - STG [<Xn|SP>, #<simm>] - STG [<Xn|SP>, #<simm>]! - STG [<Xn|SP>], #<simm> - STZG [<Xn|SP>, #<simm>] - STZG [<Xn|SP>, #<simm>]! - STZG [<Xn|SP>], #<simm> - ST2G [<Xn|SP>, #<simm>] - ST2G [<Xn|SP>, #<simm>]! - ST2G [<Xn|SP>], #<simm> - STZ2G [<Xn|SP>, #<simm>] - STZ2G [<Xn|SP>, #<simm>]! - STZ2G [<Xn|SP>], #<simm> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>] - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]! - STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm> where <Xn|SP> : Is the 64-bit GPR or Stack pointer. <simm> : Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data for AARCH64_OPND_QLF_imm_tag. (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New. (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp for both offset and pre/post indexed versions. (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (fix_insn): Likewise. (warn_unpredictable_ldst): Exempt STGP. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g, stzg, stz2g and stgp. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory ↵Sudakshina Das5-0/+66
Tagging Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Pointer Arithmetic instructions from MTE. These are the following instructions added in this patch: - SUBP <Xd>, <Xn|SP>, <Xm|SP> - SUBPS <Xd>, <Xn|SP>, <Xm|SP> - CMPP <Xn|SP>, <Xm|SP> where CMPP is an alias to SUBPS XZR, <Xn|SP>, <Xm|SP> where <Xd> : Is the 64-bit destination GPR. <Xn|SP> : Is the 64-bit first source GPR or Stack pointer. <Xm|SP> : Is the 64-bit second source GPR or Stack pointer. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for subp, subps and cmpp. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging ↵Sudakshina Das7-0/+120
Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag generation instructions from MTE. These are the following instructions added in this patch: - IRG <Xd|SP>, <Xn|SP>{, Xm} - ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2> - SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2> - GMI <Xd>, <Xn|SP>, <Xm> where <Xd|SP> : Is the 64-bit destination GPR or Stack pointer. <Xn|SP> : Is the 64-bit source GPR or Stack pointer. <uimm6> : Is the unsigned immediate, a multiple of 16 in the range 0 to 1008. <uimm4> : Is the unsigned immediate, in the range 0 to 15. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3. (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New. * aarch64-opc.c (fields): Add entry for imm4_3. (operand_general_constraint_met_p): Add cases for AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_ADDG): New. (aarch64_opcode_table): Add addg, subg, irg and gmi. (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10. * aarch64-asm.c (aarch64_ins_imm): Add case for operand_need_shift_by_four. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10. * testsuite/gas/aarch64/armv8_5-a-memtag.s: New. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.d: Likewise.
2018-11-12[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-ASudakshina Das3-0/+10
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions. Memory Tagging Extension is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch adds the new command line option and the new feature macros. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_feature_memtag): New. (MEMTAG, MEMTAG_INSN): New. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): Add "memtag" as a new option. * doc/c-aarch64.texi: Document the same.
2018-11-09S/390: Fix optional operand handling after memory addressesAndreas Krebbel4-24/+42
Instructions having an optional argument following a memory address operand were not handled correctly if the optional argument was not specified. gas/ChangeLog: 2018-11-09 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (skip_optargs_p): New function. (md_gather_operands): Use skip_optargs_p. * testsuite/gas/s390/s390.exp: Run the new test. * testsuite/gas/s390/zarch-optargs.d: New test. * testsuite/gas/s390/zarch-optargs.s: New test.
2018-11-09PowerPC, don't use bfd reloc howto in md_assembleAlan Modra2-11/+255
We support source like the following .data .quad x-. .space 8 x: where at the time the .quad line is assembled, x is unknown so a fixup is emitted for later evaluation. This is supported for data even when the target may not have relocations for the expression, for example, 32-bit powerpc targets lack a 64-bit reloc. As long as the fixup resolves at assembly time, gas is happy. The idea of this patch is to support fixups that resolve at assembly time for instructions too, even when the target might lack the necessary relocations (and thus no howto). * config/tc-ppc.c (fixup_size): New function. (md_assemble): Use it to derive size and pcrel directly from fixup reloc type.
2018-11-07Add updated French and Portuguese translations.Nick Clifton2-2994/+3076
gas * po/fr.po: Updated French translation. bfd * po/fr.po: Updated French translation. * po/pt.po: Updated Portuguese translation. binutils* po/pt.po: Updated Portuguese translation.
2018-11-07rx: Add target rx-*-linux.Yoshinori Sato5-2/+13
2018-11-06[arm] fix testsuite breakage on pe-coffMatthew Malcomson2-2/+8
The PE target can insert NOP's for padding to 4 byte alignment. This was causing a testcase failure, this commit fixes the testcase. This commit also escapes some full-stops in the testcase regexp. 2018-11-06 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/arm/neon-cond-bad_t2.d: Fix testcase for PE target.
2018-11-06[arm] Check for neon and condition in vcvt.f16.f32Matthew Malcomson7-14/+40
VCVT between f16 and f32 is an Advanced SIMD instruction. Not all the VCVT alternatives need neon, hence the check for neon is in the encode function. The check on neon for VCVT.f16.f32 (and vice versa) is missing. vshcmd: > echo 'vcvt.f16.f32 d1, q1' | gas/as-new -mfpu=vfpxd -march=armv8.5-a - testdir [15:59:10] $ Also, the handling of the condition code behaves differently to other SIMD instructions -- no error message is produced when assembling an instruction with a condition code suffix despite the arm encoding not allowing a condition code. (n.b. the actual binary produced is independent of the suffix). The instruction should be treated similarly to VSUBL that has the same caveat of "must be unconditional" describing the {<c>} symbol. vcvt half-precision to single precision found in F6.1.58 in the ARM Architecture Reference Manual issue C.a, vsubl found in F6.1.240 in the ARM Architecture Reference Manual issue C.a 2018-11-06 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (do_neon_cvt_1): Add check for neon and condition codes to half-precision conversion. * testsuite/gas/arm/neon-cond-bad-inc.s: Check vcvteq disallowed. * testsuite/gas/arm/neon-cond-bad.l: Likewise. * testsuite/gas/arm/neon-cond-bad_t2.d: Check vcvteq allowed in IT block. * testsuite/gas/arm/vfp-bad.l: Ensure vcvt doesn't work without neon. * testsuite/gas/arm/vfp-bad.s: Likewise.
2018-11-06PowerPC instruction mask checksAlan Modra2-14/+29
The instruction mask bits should never overlap any of the operands, nor should operand bits overlap, but some operands weren't checked. This patch arranges to check the omitted operands, using a mask returned by the operand->insert function. Some tweaking of various insert functions is needed to support this: The error case must set field bits. Since I was looking at the insert functions, I tidied some dead code and simplified some of the powerpc_operands entries. gas/ * config/tc-ppc.c (insn_validate): Don't ignore mask in PPC_OPSHIFT_INV case. Call the insert function to calculate a mask. opcodes/ * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls), (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0), (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16), (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd): Don't return zero on error, insert mask bits instead. (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete. (insert_sh6, extract_sh6): Delete dead code. (insert_sprbat, insert_sprg): Use unsigned comparisions. (powerpc_operands <OIMM>): Set shift count rather than using PPC_OPSHIFT_INV. <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
2018-11-06PowerPC instruction operand flag validationAlan Modra2-0/+14
This adds another check that might have saved me a little time recently if it had been present. * config/tc-ppc.c (insn_validate): Check that optional operands are not followed by non-optional operands.
2018-11-06x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit modeJan Beulich4-0/+10
For the flavor having a GPR operand EVEX.W is ignored outside of 64-bit mode. The mnemonic should therefore not be VPBROADCASTQ.
2018-11-06x86: correctly handle VMOVD with EVEX.W set outside of 64-bit modeJan Beulich4-0/+20
For the flavors having a GPR operand EVEX.W is ignored outside of 64-bit mode. The mnemonic should therefore not be KMOVQ, the GPR operand should not name a non-existing 64-bit register, just like is already the case for the AVX counterparts, and the Disp8 scaling factor should be 4 rather than 8.
2018-11-06x86: correctly handle KMOVD with VEX.W set outside of 64-bit modeJan Beulich3-0/+9
For the flavors having a GPR operand VEX.W is ignored outside of 64-bit mode. The mnemonic should therefore not be KMOVQ.
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich8-0/+60
PEXTR{B,W} and PINSR{B,W}, just like for AVX512BW, are WIG, no matter that the SDM uses a nonstandard description of that fact. PEXTRD, even with EVEX.W set, ignores that bit outside of 64-bit mode, just like its AVX counterpart.
2018-11-06x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich13-31/+241
Many VEX-/EVEX-encoded instructions accessing GPRs become WIG outside of 64-bit mode. The respective templates should specify neither VexWIG nor VexW0, but instead the setting of the bit should be determined from - REX.W in 64-bit mode, - the setting established through -mvexwig= / -mevexwig= otherwise. This implies that the evex-wig2 testcase needs to go away, as being wrong altogether. A few test additions desirable here will only happen in later patches, as the disassembler needs adjustments first. Once again SSE2AVX templates are left alone, for it being unclear what the behavior there should be.
2018-11-06x86: fix various non-LIG templatesJan Beulich10-0/+433
Quite a few templates were marked LIG while really the insns aren't. Introduce descriptive shorthands once again, instead of continuing to use the less legible original forms.
2018-11-06x86: allow {store} to select alternative {,}PEXTRW encodingJan Beulich5-2/+51
The 0F C5 encoding is indeed a load type one (just that memory operands are not permitted), while the 0F 3A 15 encoding is obviously a store. Allow the pseudo prefixes to be used to select between them. Also move (without any change) the secondary AVX512BW templates next to the primary one.
2018-11-06x86: add more VexWIGJan Beulich9-18/+70
Commits 6865c0435a ("x86: Support VEX/EVEX WIG encoding") and 6fa52824c3 ("x86: Replace VexW=3 with VexWIG") omitted quite a few templates, oddly enough in some cases despite testcases getting added (which then were recorded with wrong expected output). Also adjust VPMAXUB's attributes in the AVX512BW case to match ordering of that of neighboring templates. For the moment SSE2AVX templates are left alone, as it isn't clear whether they were intentionally left untouched by the original commits (the descriptions don't say either way). In this context I question the decision in commit 0375113302 ("x86: Add -mvexwig=[0|1] option to assembler") to move the logic to determine the value of the W bit ahead of the decision whether to use 2-byte VEX: While I can see this as one possible interpretation of -mvexwig=, the other alternative (setting the value of the bit only if it actually exists in the encoding) looks as reasonable to me, and perhaps even more in line with us generally trying to pick the shortest encoding.
2018-11-05Correct ChangeLog entries for PR gas/23854 commitH.J. Lu1-1/+1
commit e60f4d3bdac25f02875afe36b7436bc2dfbbb978 Author: H.J. Lu <hjl.tools@gmail.com> Date: Mon Nov 5 09:01:26 2018 -0800 x86: Disable GOT relaxation with data prefix Since linker GOT relaxation isn't valid for 16-bit GOT access, we should disable GOT relaxation with data prefix.
2018-11-05x86: Disable GOT relaxation with data prefixH.J. Lu3-7/+15
Since linker GOT relaxation isn't valid for 16-bit GOT access, we should disable GOT relaxation with data prefix. gas/ PR gas/r23854 * config/tc-i386.c (output_disp): Disable GOT relaxation with data prefix. * testsuite/gas/i386/mixed-mode-reloc32.d: Updated. ld/ PR gas/r23854 * testsuite/ld-i386/i386.exp: Run pr23854. * testsuite/ld-x86-64/x86-64.exp: Likewwise. * testsuite/ld-i386/pr23854.d: New file. * testsuite/ld-i386/pr23854.s: Likewwise. * testsuite/ld-i386/pr23854.d: Likewwise. * testsuite/ld-x86-64/pr23854.d: Likewwise. * testsuite/ld-x86-64/pr23854.s: Likewwise.
2018-11-01Fix ld action in run_dump_testThomas Preud'homme2-0/+13
run_dump_test proposes an ld action but when trying to make use of it in a gas test it gave me some Tcl error. It turns out that it references the check_shared_lib_support procedure and ld_elf_shared_opt variable both only available in ld-lib.exp. I've thus moved the procedure in binutils-common.exp and defined the variable needed in the various default.exp of testsuite that seem to be using run_dump_test. Since check_shared_lib_support itself references the ld variable not defined in binutils-common I've defined it from LD in run_dump_test and fixed LD and LDFLAGS to be defined as expected by run_dump_test in the various default.exp of testsuite using run_dump_test. 2018-11-01 Thomas Preud'homme <thomas.preudhomme@linaro.org> binutils/ * testsuite/config/default.exp: Define LD, LDFLAGS and ld_elf_shared_opt. * testsuite/lib/binutils-common.exp (check_shared_lib_support): Moved from ld-lib.exp. (run_dump_test): Set ld to $LD. gas/ * testsuite/config/default.exp: Define LD, LDFLAGS and ld_elf_shared_opt. ld/ * testsuite/lib/ld-lib.exp (check_shared_lib_support): Moved to binutils-common.exp.
2018-10-31[GAS][ARM] Fix ARMv8.1 AdvSIMD testismAndre Vieira2-1/+4
This test never used to test the output of objdump as the old 'error-output' check would exit after verifying the output in stdout and stderr from the assembler. Given the use of warning_output now, the objdump runs and expects its output to be verified. Assuming the correct disassembly of these instructions is tested elsewhere given we never tested them here, this patch removes the objdump run. gas/ChangeLog 2018-10-31 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/gas/arm/armv8-a+rdma-warning.d: Remove objdump execution.
2018-10-31[GAS][ARM] Fix UDF testismAndre Vieira2-23/+23
The old test never checked the objdump output since the 'error-output' directive would exit and thus never run objdump. When this test was changed to adhere to use the new warning_output we started to run objdump. The expected objdump output was old and had bitrotten, this fixes the layout, as the "disassembly" itself did not change. gas/ChangeLog 2018-10-31 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/gas/arm/udf.d: Update expected output.
2018-10-31[GAS][ARM] Fix failing Armv1 testAndre Vieira2-18/+23
This test has been failing for a while and it could be argued that since we started testing 'arm7t' here (and not Armv1) the test itself was wrong. So I changed the assembly to Armv1. Given the changes to objdump when "disassembling all" it seemed like a good idea to force the disassembly to 'armv2' instead and actually accept the disassembly of the 26-bit Architecture variants of tst, teq, cmn and cmp. gas/ChangeLog 2018-10-31 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/gas/arm/armv1.d: Assemble for Armv1 and disassemble for Armv2.
2018-10-29Move struc-symbol.h to symbols.cAlan Modra31-326/+353
This file was never supposed to be widely used. The fact that it has found its way into many gas files led to bugs, typically when code expecting a symbolS* to point at a struct symbol is presented with a struct local_symbol. Also, commit 158184ac9e changed these structs in 2012 but didn't catch all places where symbol bsym was being used to test for a local_symbol. * Makefile.am (HFILES): Delete struc-symbol.h. * doc/internals.texi: Delete struc-symbol.h reference and out of date local symbol description. * struc-symbol.h: Delete. Move contents to.. * symbols.c: ..here. (symbol_on_chain, symbol_symbolS): New functions. * symbols.h (symbol_on_chain, symbol_symbolS): Declare. * cgen.c: Don't #include struc-symbol.h. (gas_cgen_parse_operand): Don't test for local_symbol using bsym, instead call symbol_symbolS. Use symbol_get_bfdsym. (weak_operand_overflow_check, make_right_shifted_expr): Use symbol accessors. * config/obj-coff.c: Don't #include struc-symbol.h. (GET_FILENAME_STRING): Delete. * config/obj-elf.c: Don't #include struc-symbol.h. (elf_file_symbol): Use symbol accessors. (elf_adjust_symtab): Call symbol_on_chain. * config/obj-evax.c: Don't #include struc-symbol.h. * config/tc-nds32.c: Likewise. * config/tc-rl78.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-alpha.c: Likewise. (add_to_link_pool, s_alpha_comm): Use symbol accessors. * config/tc-arc.c: Don't #include struc-symbol.h. (arc_check_relocs): Use symbol accessors, testing gas symbol section rather than bfd symbol section. * config/tc-avr.c: Don't #include struc-symbol.h. (avr_patch_gccisr_frag): Use symbol accessors. * config/tc-bfin.c: Don't #include struc-symbol.h. (bfin_loop_beginend): Use symbol accessors. * config/tc-csky.c: Don't #include struc-symbol.h. (v2_work_movih, v2_work_ori): Use symbol accessors. Check for absolute symbol as well as O_constant. * config/tc-riscv.c: Don't #include struc-symbol.h. (riscv_pre_output_hook): Use symbol accessors. * config/tc-s390.c: Don't #include struc-symbol.h. (s390_literals): Use symbol accessors. * config/tc-score.c (s3_build_la_pic, s3_build_lwst_pic): Use symbol accessors. (s3_relax_branch_inst16, s3_relax_cmpbranch_inst32): Don't test symbol bsym. * config/tc-score7.c: Don't #include struc-symbol.h. (s7_build_la_pic, s7_build_lwst_pic): Use symbol accessors. (s7_b32_relax_to_b16): Don't test symbol bsym. * config/tc-sh.c: Don't #include struc-symbol.h. (insert_loop_bounds): Use symbol accessors. (sh_frob_section): Remove bogus symbol canonicalization. * config/tc-tic54x.c: Don't #include struc-symbol.h. (tic54x_bss): Use symbol accessors. * config/tc-tilegx.c: Don't #include struc-symbol.h. (emit_tilegx_instruction, tilegx_parse_name): Use symbol accessors. * config/tc-tilepro.c: Don't #include struc-symbol.h. (emit_tilepro_instruction, tilepro_parse_name): Use accessors. * config/tc-xtensa.c: Don't #include struc-symbol.h. (xg_assemble_vliw_tokens): Use symbol accessors. (xg_order_trampoline_chain): Likewise. * ehopt.c: Don't #include struc-symbol.h. (check_eh_frame): Correct local symbol test. Use symbol accessors. * write.c: Don't #include struc-symbol.h. (create_note_reloc, maybe_generate_build_notes): Use symbol accessors. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.
2018-10-28Correct ChangeLogAlan Modra1-1/+1
2018-10-28PR23837, Segmentation fault in resolve_symbol_valueAlan Modra2-2/+8
Local symbols don't have a sy_frag field. PR 23837 * config/tc-hppa.c: Don't include struc-symbol.h. (pa_build_unwind_subspace): Call get_symbol_frag rather than referencing sy_frag.
2018-10-23S/390: Support vector alignment hintsAndreas Krebbel3-0/+31
This patch adds the vector alignment hints to the vector load and store instructions as documented in the IBM z14 Principles of Operations manual: http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr011.pdf opcodes/ChangeLog: 2018-10-23 Andreas Krebbel <krebbel@linux.ibm.com> * s390-opc.txt: Add vector load/store instructions with additional alignment parameter. gas/ChangeLog: 2018-10-23 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (md_gather_operands): Fix for optional operands following memory addresses. * testsuite/gas/s390/zarch-arch12.d: Add regexp checks for new instruction variants. * testsuite/gas/s390/zarch-arch12.s: Emit new instruction variants.
2018-10-23S12Z: Handle 16 bit fixups which are constant.John Darrington2-0/+8
Commit 1f38083f425e03faf55595414daf291306738222 added a test to check that the assembler handled fixups with resolved to constant values. We were not handling this in the case of 16 bit values. This change fixes that. * gas/config/tc-s12z.c (md_apply_fix): Handle BFD_RELOC_16
2018-10-22gas simple-forward testAlan Modra5-2/+36
Tests that target md_apply_fix can handle fixups that have resolved down to a constant and thus do not need relocations. Also a fix for eqv-dot xfails. * testsuite/gas/all/simple-forward.d, * testsuite/gas/all/simple-forward.s: New test. * testsuite/gas/all/gas.exp: Run it. * testsuite/gas/all/eqv-dot.d: xfail tic30 and tic54x.
2018-10-22Apply alpha BFD_RELOC_8 fixupsAlan Modra4-4/+15
* config/tc-alpha.c (md_apply_fix): Handle BFD_RELOC_8 for fixups without a symbol. * testsuite/gas/all/gas.exp: Don't xfail forward test here.. * testsuite/gas/all/forward.d: ..do so here, removing alpha.
2018-10-22PR23040, .uleb128 directive doesn't accept some valid expressionsAlan Modra4-20/+48
What a trip down a rabbit hole this bug has been. First observation: You can't use deferred_expression in s_leb128. deferred_expression implements the semantics of .eqv or '==', saving an expression with minimal simplification for assignment to a symbol so that the expression is evaluated at uses of the symbol. In particular, the value of "dot" is not evaluated at the .eqv symbol assignment, but later. When s_leb128 uses deferred_expression, "later" is at the end of assembly, giving entirely the wrong value of "dot". There is no way to fix this for the s_leb128 use without breaking .equ (which incidentally was already somewhat broken, see commit e4c2619ad1). So, don't use deferred_expression in s_leb128. But that leads to the gas test elf/dwarf2-17 failing, because view symbols are calculated with a chain of expression symbols. In the dwarf2-17 .L1 case there is a "temp_sym_1 > temp_sym_2" expression, with temp_sym_1 and temp_sym_2 on either side of a ".balign". Since ".balign" and many other directives moving "dot" are not calculated on the first (and only) pass over source, .L1 cannot be calculated until final addresses are assigned to frags. However, ".uleb128 .L1" *is* calculated immediately, resulting in the wrong value. The reason why .L1 is calculated immediately is that code in expr.c:operand after the comment /* If we have an absolute symbol or a reg, then we know its value now. */ does as it says and fixes the value of .L1, because .L1 is assigned to absolute_section in dwarf2dbg.c:set_or_check_view. So, correct that to expr_section. Unfortunately that fix leads to failure of the elf/dwarf2-5 test with ../gas/elf/dwarf2-5.s: Error: attempt to get value of unresolved symbol `.L5' ../gas/elf/dwarf2-5.s: Error: attempt to get value of unresolved symbol `.L11' ../gas/elf/dwarf2-5.s: Error: attempt to get value of unresolved symbol `.L12' So why is that? Well, it turns out that .L5 is defined in terms of .L4, and apparently .L4 is undefined. But .L4 clearly is defined, otherwise we would hit an error when trying to use .L4 a little earlier. There are two copies of .L4! So, symbols are cloned when that should not happen. Symbol cloning is a technique used by gas to support saving the value of symbols that change between uses, but that isn't the case with .L4. Only one value is set and used for .L4, but indeed .L4 was being cloned by symbol_clone_if_forward_ref. This despite no forward refs being present. Also, .L4 is a local symbol and a cursory glance at symbol_clone_if_forward_ref "if (symbolP && !LOCAL_SYMBOL_CHECK (symbolP))" would seem to prevent cloning of local symbols. All is not as it seems though, a curse of using macros. LOCAL_SYMBOL_CHECK modifies its argument if a "struct local_symbol" is converted to the larger "struct symbol", as happens when assigning a view symbol value. That fact results in the recursive call to symbol_clone_if_forward_ref returning a different address for "add_symbol". This problem could have been fixed by using symbol_same_p rather than comparing symbol pointers, but I thought it better to use the real symbol throughout. Note that symbol_find_exact also returns the real symbol for a converted local symbol. Finally, this patch does expose lack of support for forward symbol definitions in various targets. For example: alpha-linux +ERROR: ../ld/testsuite/ld-elf/pr11138-2.c: compilation failed This is caused by view symbol uses. On alpha-linux-gcc (GCC) 8.1.1 20180502 they happen to occur in .byte directives so were silently broken in cases like elf/dwarf2-17 anyway. /tmp/ccvtsMfU.s: Assembler messages: /tmp/ccvtsMfU.s: Fatal error: unhandled relocation type BFD_RELOC_8 /tmp/ccvtsMfU.s: Fatal error: unhandled relocation type BFD_RELOC_8 md_apply_fix on those targets needs to handle fixups that resolve down to a constant. PR 23040 * symbols.c (get_real_sym): New function. (symbol_same_p): Use get_real_sym. (symbol_clone_if_forward_ref): Save real original add_symbol and op_symbol for comparison against that returned from lookup or recursive calls. * dwarf2dbg.c (set_or_check_view): Use expr_section for expression symbols, not absolute_section. (dwarf2_directive_loc): Check symbol_equated_p and tidy cloning of view symbols. * read.c (s_leb128): Don't use deferred_expression.
2018-10-20PR23800, .eqv doesn't always defer expression evaluationAlan Modra6-1/+55
.eqv (and ==) ought not simplify expressions involving dot or other symbols set by .eqv. If such simplification occurs, the value of dot will be that at the assignment rather than at the place where the symbol is used. PR 23800 * expr.c (expr): Don't simplify expressions involving forward_ref symbols when mode is expr_defer. * config/tc-spu.c (spu_cons): Parse expression using normal expression evaluation if @ppu is not detected. * testsuite/gas/all/eqv-dot.d, * testsuite/gas/all/eqv-dot.s: New test. * testsuite/gas/all/gas.exp: Run it.
2018-10-19Arm: Skip new binary decode tests on pe targetsTamar Christina3-2/+7
The two new test I added require the use of the ".inst" directive which the PE targets don't support. Because of that I excluded *-unknown-pe but the mask needs to be wider. I am now excluding *-*-pe. gas/ChangeLog: * testsuite/gas/arm/undefined-insn-arm.d: Widen pe skip. * testsuite/gas/arm/undefined-insn-thumb.d: Likewise.
2018-10-19Arm: Fix disassembler crashing on -b binary when thumb file and thumb not ↵Tamar Christina4-0/+17
forced. The disassembler for Arm has some aborts in it in places it assumes can never be reached. Under normal circumstances they indeed cannot be reached because the right options are selected from the ARM attributes in the ELF file. However when disassembling with -b binary then if you do not get the options right the disassembler just aborts. This changes it so it just prints how it was trying to interpret the instruction and prints UNKNOWN instructions next to it. This way the user has an idea of what's going. gas/ChangeLog: * testsuite/gas/arm/undefined-insn-arm.d: New test. * testsuite/gas/arm/undefined-insn-thumb.d: New test. * testsuite/gas/arm/undefined-insn.s: New test. opcodes/ChangeLog: * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode. (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode. (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
2018-10-19This set of changes clarifies the conditions for the R5900 short loop fix ↵Fredrik Noring4-10/+71
and extends its test with the border cases of six and seven instructions. * testsuite/gas/mips/r5900.s: Extend the R5900 short loop fix test with border cases. * testsuite/gas/mips/r5900.d: Add extra expected disassembly. * config/tc-mips.c (can_swap_branch_p): Clarify the R5900 short loop hardware bug conditions. Correct note on the R5900 instruction count short loop fix.
2018-10-16AArch64: Fix error checking for SIMD udot (by element)Matthew Malcomson4-0/+28
Committed on behalf of Matthew Malcomson: The SIMD UDOT instruction assembly has an unusual operand that selects a single 32 bit element with the mnemonic 4B. This unusual mnemonic is handled by a special operand qualifier and associated qualifier data in `aarch64_opnd_qualifiers`. The current qualifier data describes 4 1-byte elements with the structure {1, 4, 0x0, "4b", OQK_OPD_VARIANT} This makes sense, as the instruction does work on 4 1-byte elements, however some logic in the `operand_general_constraint_met_p` makes assumptions about the range of index allowed when selecting a SIMD_ELEMENT depending on element size. That function reasons that e.g. in order to select a byte-sized element in a 16 byte V register an index must allow selection of one of the 16 elements and hence its range will be in [0,15]. This reasoning breaks with the above description of a 4 part selection of 1 byte elements and allows an index outside the valid [0,3] range, triggering an assert later on in the program in `aarch64_ins_reglane`. vshcmd: > echo 'udot v0.2s, v1.8b, v2.4b[4]' | ../src/binutils-build/gas/as-new -march=armv8.4-a as-new: ../../binutils-gdb/opcodes/aarch64-asm.c:134: aarch64_ins_reglane: Assertion `reglane_index < 4' failed. {standard input}: Assembler messages: {standard input}:1: Internal error (Aborted). Please report this bug. This patch changes the operand qualifier data so that it describes a single 32 bit element. {4, 1, 0x0, "4b", OQK_OPD_VARIANT} Hence the calculation in `operand_general_constraint_met_p` provides the correct answer and the usual error checking machinery is used. vshcmd: > echo 'udot v0.2s, v1.8b, v2.4b[4]' | ../src/binutils-build/gas/as-new -march=armv8.4-a {standard input}: Assembler messages: {standard input}:1: Error: register element index out of range 0 to 3 at operand 3 -- `udot v0.2s,v1.8b,v2.4b[4]'
2018-10-15BFD_INIT_MAGICAlan Modra2-1/+8
This patch performs a run-time test that a shared libbfd.so has been compiled with the same size bfd_vma as that of apps using the library. On a 32-bit host it is easily possible to have one libbfd.so compiled to support 64-bit targets (or configured with --enable-64-bit-bfd) while another only supports 32-bit targets. The two libraries will have differently sized bfd_vma types, and if the wrong one is loaded all sorts of weird behaviour might be seen. bfd/ PR 23534 * init.c (BFD_INIT_MAGIC): Define. (bfd_init): Return BFD_INIT_MAGIC. bfd-in2.h: Regenerate. binutils/ PR 23534 * addr2line.c (main): Exit with fatal error if bfd_init returns an unexpected value. * ar.c (main): Likewise. * dlltool.c (identify_dll_for_implib): Likewise. * nm.c (main): Likewise. * objcopy.c (main): Likewise. * objdump.c (main): Likewise. * size.c (main): Likewise. * strings.c (main): Likewise. * windmc.c (main): Likewise. * windres.c (main): Likewise. gas/ PR 23534 * as.c (main): Exit with fatal error if bfd_init returns an unexpected value. ld/ PR 23534 * ldmain.c (main): Exit with fatal error if bfd_init returns an unexpected value.
2018-10-11x86: add {,V}MOVQ cases to xmmword testJan Beulich3-0/+19
I had overlooked these when putting together the original test.
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich2-6/+11
Only one of them can be set at a time, which means they can be expressed by a single 2-bit field instead of three 1-bit ones.
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das10-0/+220
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds support for the mitigation for Spectre Variant 4 by adding the PSTATE bit SSBS which are accessible using MSR and MRS instructions. Although this is a mandatory addition to the ARMv8.5-A, it is permitted to be added to any version of the ARMv8 architecture. This is enabled using the command line option of +ssbs for older versions. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SSBS): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (operand_general_constraint_met_p): Add SSBS in the check for one-bit immediate. (aarch64_sys_regs): New entry for SSBS. (aarch64_sys_reg_supported_p): New check for above. (aarch64_pstatefields): New entry for SSBS. (aarch64_pstatefield_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): Add new "ssbs". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/ssbs-illegal1.d: New test. * testsuite/gas/aarch64/ssbs-illegal1.l: New test. * testsuite/gas/aarch64/ssbs-illegal2.d: New test. * testsuite/gas/aarch64/ssbs-illegal2.l: New test. * testsuite/gas/aarch64/ssbs.s: New test. * testsuite/gas/aarch64/ssbs1.d: Test with +ssbs * testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
2018-10-09[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registersSudakshina Das4-0/+25
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New. (AARCH64_FEATURE_ID_PFR2): New. (AARCH64_ARCH_V8_5): Add both by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs): New entries for scxtnum_el[0,1,2,3,12] and id_pfr2_el1. (aarch64_sys_reg_supported_p): New checks for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test registers scxtnum_el[0,1,2,3,12] and id_pfr2_el1. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das7-4/+95
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification) The Branch Target Identification instructions (BTI) are allocated to existing HINT space, using HINT numbers 32, 34, 36, 38, such that bits[7:6] of the instruction identify the compatibility of the BTI instruction to different branches. BTI {<targets>} where <targets> one of the following, specifying which type of indirection is allowed: j : Can be a target of any BR Xn isntruction. c : Can be a target of any BLR Xn and BR {X16|X17}. jc: Can be a target of any free branch. A BTI instruction without any <targets> is the strictest of all and can not be a target of nay free branch. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BTI): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default. (aarch64_opnd): Add AARCH64_OPND_BTI_TARGET. (HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to define HINT #imm values. (HINT_OPD_JC, HINT_OPD_NULL): Likewise. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New. (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag with the hint immediate. * aarch64-opc.c (aarch64_hint_options): New entries for c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI. (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET while checking for HINT_OPD_F_NOPRINT flag. * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to extract value. * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New. (aarch64_opcode_table): Add entry for BTI. (AARCH64_OPERANDS): Add new description for BTI targets. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_bti_operand): New. (process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET. (parse_operands): Likewise. * testsuite/gas/aarch64/system.d: Update for BTI. * testsuite/gas/aarch64/bti.s: New. * testsuite/gas/aarch64/bti.d: New. * testsuite/gas/aarch64/illegal-bti.d: New. * testsuite/gas/aarch64/illegal-bti.l: New.
generated by cgit v1.1 at 2024-10-11 02:29:18 +0000