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2023-01-12Use __func__ rather than __FUNCTION__Alan Modra3-14/+14
We already use C99's __func__ in places, use it more generally. This patch doesn't change uses in the testsuite. I've also left one in gold.h that is protected by GCC_VERSION < 4003. If any of the remaining uses bothers anyone I invite patches. bfd/ * bfd-in.h: Replace __FUNCTION__ with __func__. * elf32-bfin.c: Likewise. * elfnn-aarch64.c: Likewise. * elfxx-sparc.c: Likewise. * bfd-in2.h: Regenerate. gas/ * config/tc-cris.c: Replace __FUNCTION__ with __func__. * config/tc-m68hc11.c: Likewise. * config/tc-msp430.c: Likewise. gold/ * dwp.h: Replace __FUNCTION__ with __func__. * gold.h: Likewise, except for use inside GCC_VERSION < 4003. ld/ * emultempl/pe.em: Replace __FUNCTION__ with __func__. * emultempl/pep.em: Likewise. * pe-dll.c: Likewise.
2023-01-11gas/RISC-V: adjust assembler for opcode table re-orderingJan Beulich1-0/+11
PR gas/29940 With the single-operand JAL entry now sitting ahead of the two-operand one, the parsing of a two-operand insn would first try to parse an 'a'- style operand, resulting in the insertion of bogus (and otherwise unused) undefined symbols in the symbol table, having register names. Since 'a' is used as 1st operand only with J and JAL, and since JAL is the only insn _also_ allowing for a register as 1st operand (and then there being a 2nd one), special case this parsing aspect right there. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-01-11Tidy some global bfd state used by gasAlan Modra1-0/+2
* subsegs.c (subsegs_end): Clear abs and und userdata.
2023-01-11now_seg after closing output fileAlan Modra1-0/+2
now_seg, a pointer into the output file sections, isn't valid after the output file is closed. gas doesn't and shouldn't use now_seg after this point of course, but let's be safe. * output-file.c (output_file_close): Clear now_seg and now_subseg.
2023-01-10gas: Restore tc_pe_dwarf2_emit_offset for pe-aarch64Mark Harmstone2-0/+16
Restores tc_pe_dwarf2_emit_offset in tc-aarch64.c, which is needed to make sure that DWARF offsets are encoded correctly (they're secrels in COFF). There were remnants of this there before, but they were removed by Jedidiah's original patch - presumably because we didn't yet have .secrel32.
2023-01-10Add aarch64-w64-mingw32 targetMark Harmstone2-2/+2
This adds a mingw target for aarch64, including windres and dlltool. Note that the old value of jmp_aarch64_bytes was wrong, and this does the same thing as MSVC does.
2023-01-10Add .secrel32 for pe-aarch64Mark Harmstone2-19/+60
Adds the .secrel32 pseudo-directive and its corresponding relocation.
2023-01-10Add pe-aarch64 relocationsMark Harmstone3-21/+395
This adds the remaining pe-aarch64 relocations, and gets them working. It also brings in the constant directives from ELF, as otherwise .word would be 2 rather than 4 bytes, and .xword and .dword wouldn't be defined.
2023-01-06sframe: fix the defined SFRAME_FRE_TYPE_*_LIMIT constantsIndu Bhagat1-6/+6
An earlier commit 3f107464 defined the SFRAME_FRE_TYPE_*_LIMIT constants. These constants are used (by gas and libsframe) to pick an SFrame FRE type based on the function size. Those constants, however, were buggy, causing the generated SFrame sections to be bloated as SFRAME_FRE_TYPE_ADDR2/SFRAME_FRE_TYPE_ADDR4 got chosen more often than necessary. gas/ * sframe-opt.c (sframe_estimate_size_before_relax): Use typecast. (sframe_convert_frag): Likewise. libsframe/ * sframe.c (sframe_calc_fre_type): Use a more appropriate type for argument. Adjust the check for SFRAME_FRE_TYPE_ADDR4_LIMIT to keep it warning-free but meaningful. include/ * sframe-api.h (sframe_calc_fre_type): Use a more appropriate type for the argument. * sframe.h (SFRAME_FRE_TYPE_ADDR1_LIMIT): Correct the constant. (SFRAME_FRE_TYPE_ADDR2_LIMIT): Likewise. (SFRAME_FRE_TYPE_ADDR4_LIMIT): Likewise.
2023-01-03Fix a translation problem in the x86 assembler.Nick Clifton2-7/+25
PR 29952 * config/tc-i386.c (md_assemble): Avoid constructing translatable strings.
2023-01-03Updated translations for various languages and sub-directoriesNick Clifton3-5281/+5672
2023-01-02obsolete target tidyAlan Modra13-42/+9
Delete a few files only used for obsolete targets, and tidy config, xfails and other pieces of support specific to those targets. And since I was editing target triplets in test files, fix the nm alpha-linuxecoff fails.
2023-01-01Update year range in copyright notice of binutils filesAlan Modra578-582/+582
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2022-12-31Update version number and regenerate filesNick Clifton2-2619/+2800
2022-12-31Add markers for 2.40 branchNick Clifton2-0/+6
2022-12-30PR29948, heap-buffer-overflow in display_debug_lines_decodedAlan Modra1-2/+2
This fixes a couple of places in display_debug_lines_decoded that were off by one in checking DWARF5 .debug_line directory indices. It also displays the DWARF5 entry 0 for the program current directory rather than "." as is done for pre-DWARF5. I decided against displaying DW_AT_comp_dir for pre-DWARF5 since I figure it is better for readelf to minimally interpret debug info. binutils/ PR 29948 * dwarf.c (display_debug_lines_decoded): Display the given directory entry 0 for DWARF5. Properly check directory index against number of entries in the table. Revert to using unsigned int for n_directories and associated variables. Correct warning messages. gas/ * testsuite/gas/elf/dwarf-5-loc0.d: Update.
2022-12-29RISC-V: Simplify riscv_csr_address logic on state enable extensionsTsukasa OI1-7/+9
This commit makes CSR class handling for 'Smstateen' and 'Ssstateen' extensions simpler using fall-throughs (as used in CSR_CLASS_I{,_32}). gas/ChangeLog: * config/tc-riscv.c (riscv_csr_address): Simplify the logic for 'Smstateen' and 'Ssstateen' extensions.
2022-12-27RISC-V: Fix T-Head Fmv vendor extension encodingChristoph Müllner1-2/+2
A recent change in the XTheadFmv spec fixed an encoding bug in the document. This patch changes the code to follow this bugfix. Spec patch can be found here: https://github.com/T-head-Semi/thead-extension-spec/pull/11 Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-12-23RISC-V: Relax the order checking for the architecture stringNelson Chu7-14/+8
* riscv-toolchain-conventions, PR, https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14 Issue, https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/11 * Refer to the commit afc41ffb, RISC-V: Reorder the prefixed extensions which are out of order. In the past we only allow to reorder the prefixed extensions. But according to the PR 14 in the riscv-toolchain-convention, we can also relax the order checking to allow the whole extensions be written out of orders, including the single standard extensions and the prefixed multi-letter extensions. Just that we still need to follow the following rules as usual, 1. prefixed extensions need to be seperated with `_'. 2. prefixed extensions need complete <major>.<minor> version if set. Please see the details in the march-ok-reorder gas testcase. Passed the riscv-gnu-toolchain regressions. bfd/ * elfxx-riscv.c (enum riscv_prefix_ext_class): Changed RV_ISA_CLASS_UNKNOWN to RV_ISA_CLASS_SINGLE, since everything that does not belong to the multi-keyword will possible be a single extension for the current parser. (parse_config): Likewise. (riscv_get_prefix_class): Likewise. (riscv_compare_subsets): Likewise. (riscv_parse_std_ext): Removed, and merged with riscv_parse_prefixed_ext into riscv_parse_extensions. (riscv_parse_prefixed_ext): Likewise. (riscv_parse_subset): Only need to call riscv_parse_extensions to parse both single standard and prefixed extensions. gas/ * testsuite/gas/riscv/march-fail-order-std.d: Removed since the relaxed order checking. * testsuite/gas/riscv/march-fail-order-std.l: Likewise. * testsuite/gas/riscv/march-fail-order-x-std.d: Likewise. * testsuite/gas/riscv/march-fail-order-z-std.d: Likewise. * testsuite/gas/riscv/march-fail-order-zx-std.l: Likewise. * testsuite/gas/riscv/march-fail-unknown-std.l: Updated. * testsuite/gas/riscv/march-ok-reorder.d: New testcase.
2022-12-22gas: sframe: testsuite: add testcase for .cfi_b_key_frameIndu Bhagat3-0/+64
This is actually a composite test that checks SFrame unwind information generation for both the .cfi_negate_ra_state and .cfi_b_key_frame directives on aarch64. ChangeLog: * testsuite/gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.d: New test. * testsuite/gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.s: Likewise. * testsuite/gas/cfi-sframe/cfi-sframe.exp: Run new test.
2022-12-22gas: sframe: add support for .cfi_b_key_frameIndu Bhagat3-5/+26
Gather the information from the DWARF FDE on whether frame's return addresses are signed using the B key or A key. Reflect the information in the SFrame counterpart data structure, the SFrame FDE. ChangeLog: * gas/gen-sframe.c (get_dw_fde_pauth_b_key_p): New definition. (sframe_v1_set_func_info): Add new argument for pauth_key. (sframe_set_func_info): Likewise. (output_sframe_funcdesc): Likewise. * gas/gen-sframe.h (struct sframe_version_ops): Add new argument to the function pointer declaration. * gas/sframe-opt.c (sframe_convert_frag): Handle pauth_key.
2022-12-22gas: re-arrange listing output for .irp and alikeJan Beulich2-14/+14
It is kind of odd to have the expansions of such constructs ahead of their definition in listings with macro expansion enabled. Adjust this by pulling ahead the output of the definition lines, taking care to avoid producing a listing line for (non-existing) line 0 when the source is stdin. Note that with the code movement the conditional operator isn't necessary anymore - list->line now match up.
2022-12-22x86: correct/improve TSX controlsJan Beulich2-4/+6
TSXLDTRK takes RTM as a prereq. Additionally introduce an umbrella "tsx" extension option covering both RTM and HLE, paralleling the "abm" one we already have.
2022-12-22x86: add dependencies on SVMEJan Beulich1-4/+4
SEV-ES is an extension to SVME. SNP in turn is an extension to SEV-ES, and yet in turn RMPQUERY is a SNP extension. Note that cpu_arch[] has no SNP entry, so CPU_ANY_SNP_FLAGS remains unused (just like CPU_SNP_FLAGS already is).
2022-12-22x86: add dependencies on VMXJan Beulich1-3/+3
Both EPT and VMFUNC are extensions to VMX.
2022-12-22x86: correct dependencies of a few AVX512 sub-featuresJan Beulich1-6/+6
Like AVX512-FP16, several other extensions require wider than 16-bit mask registers. As a result they take AVX512BW as a prereq, not (just) AVX512F. Which in turn points out wrong expectations in the noavx512-1 testcase.
2022-12-22x86: rework noavx512-1 testcaseJan Beulich3-587/+415
So far the set of ".noavx512*" has been accumulating, which isn't ideal. In particular this hides issues with dependencies between features. Switch back to the default ISA before disabling a particular subset. Furthermore limit redundancy by wrapping the repeated block of insns in an .irp.
2022-12-22x86: add dependencies on AVX2Jan Beulich1-2/+2
Like AVX-VNNI both VAES and VPCLMUL take AVX2 as a prereq, for operating on up to 256-bit packed integer vectors.
2022-12-22x86: correct SSE dependenciesJan Beulich1-4/+4
SSE itself takes FXSR as a prereq. Like AES, PCLMUL, and SHA both GFNI and KL take SSE2 as a prereq, for operating on packed integers. And while correcting KL also record it as a prereq to WIDEKL.
2022-12-22x86: correct what gets disabled by certain ".arch .no*"Jan Beulich1-18/+18
Features with prereqs as well as features with dependents cannot re-use CPU_*_MASK for the 3rd argument of SUBARCH() - they need to use CPU_ANY_*_MASK in order to avoid disabling too many (when there are prereqs) and/or too few (when there are dependents) features. Generally any CPU_ANY_*_MASK which exist should not remain unused. Exceptions are - FISTTP which has no corresponding entry in cpu_arch[], - IAMCU which is a base architecture and hence uses ARCH(), not SUBARCH() (only extensions can be disabled, but unlike for Cpu*86 it would be a little more clumsy to suppress generating of the #define).
2022-12-22x86: re-work ISA extension dependency handlingJan Beulich1-27/+27
Getting both forward and reverse ISA dependencies right / consistent has been a permanent source of mistakes. Reduce what needs specifying manually to just the direct forward dependencies. Transitive forward dependencies as well as reverse ones are now derived and hence cannot go out of sync anymore (at least in the vast majority of cases; there are a few special cases to still take care of manually). In the course of this several CPU_ANY_*_FLAGS disappear, requiring adjustment to the assembler's cpu_arch[]. Note that to retain the correct reverse dependency of AVX512F wrt AVX512-VP2INTERSECT, the latter has the previously missing AVX512F prereq added. Note further that to avoid adding the following undue prereqs: * ATHLON, K8, and AMDFAM10 gain CMOV and FXSR, * IAMCU gains 387, auxiliary table entries (including a colon-separated modifier) are introduced in addition to the ones representing from converting the old table. To maintain forward-only dependencies between AVX (XOP) and SSE* (SSE4a) (i.e. "nosse" not disabling AVX), reverse dependency tracking is artifically suppressed. As a side effect disabling of SSE or SSE2 will now also disable AES, PCLMUL, and SHA (respective elements were missing from CPU_ANY_SSE2_FLAGS).
2022-12-21x86: rename CheckRegSize to CheckOperandSizeJan Beulich1-2/+2
While originally indeed used for register size checking only, the attribute has been used for memory operand size checking as well already for quite a while, with more such uses recently having been added.
2022-12-19Arm: break gas dependency on libopcodesJan Beulich2-2/+2
gas doesn't use anything from libopcodes (anymore?) - suppress linking in that library.
2022-12-16gas: sframe: testsuite: add testcase for .cfi_negate_ra_stateIndu Bhagat3-0/+39
Add a new test to check that .cfi_negate_ra_state on aarch64 is handled well (a non-empty SFrame section with valid SFrame FREs is generated). ChangeLog: * testsuite/gas/cfi-sframe/cfi-sframe-aarch64-2.d: New test. * testsuite/gas/cfi-sframe/cfi-sframe-aarch64-2.s: Likewise. * testsuite/gas/cfi-sframe/cfi-sframe.exp: Adjust the list accordingly.
2022-12-16gas: sframe: add support for .cfi_negate_ra_stateIndu Bhagat5-41/+39
DW_CFA_AARCH64_negate_ra_state in aarch64 is multiplexed with DW_CFA_GNU_window_save in the DWARF format. Remove the common-empty-4 testcase because the generated SFrame section will not be be empty anymore. A relevant test will be added in a later commit. ChangeLog: * gas/gen-sframe.c (sframe_v1_set_fre_info): Add new argument for mangled_ra_p. (sframe_set_fre_info): Likewise. (output_sframe_row_entry): Handle mangled_ra_p. (sframe_row_entry_new): Reset mangled_ra_p. (sframe_row_entry_initialize): Initialize mangled_ra_p. (sframe_xlate_do_gnu_window_save): New definition. (sframe_do_cfi_insn): Handle DW_CFA_GNU_window_save. * gas/gen-sframe.h (struct sframe_row_entry): New member. (struct sframe_version_ops): Add a new argument for mangled_ra_p. * gas/testsuite/gas/cfi-sframe/cfi-sframe.exp: Remove test. * gas/testsuite/gas/cfi-sframe/common-empty-4.d: Removed. * gas/testsuite/gas/cfi-sframe/common-empty-4.s: Removed.
2022-12-16gas: restore Dwarf info generation after macro diagnostic adjustmentsJan Beulich6-5/+29
While 6fdb723799e2 ("gas: re-work line number tracking for macros and their expansions") was meant to leave generated Dwarf as is, it really didn't (and the testcase intended to catch that wasn't covering the case which broke). Its adjustment to buffer_and_nest() didn't go far enough, leading to the "linefile" directive inserted at the top to also be processed later in the PR gas/16908 workaround (which clearly isn't intended - it's being put there for processing during macro expansion only). That unnoticed flaw in turn led me to work around it by a (suspicious to me already at the time) conditional in as_where().
2022-12-14RISC-V: Add string length check for operands in ASLi Xu4-1/+9
The current AS accepts invalid operands due to miss of operands length check. For example, "e6" is an invalid operand in (vsetvli a0, a1, e6, mf8, tu, ma), but it's still accepted by assembler. In detail, the condition check "strncmp (array[i], *s, len) == 0" in arg_lookup function passes with "strncmp ("e64", "e6", 2)" in the case above. So the generated encoding is same as that of (vsetvli a0, a1, e64, mf8, tu, ma). This patch fixes issue above by prompting an error in such case and also adds a new testcase. gas/ChangeLog: * config/tc-riscv.c (arg_lookup): Add string length check for operands. * testsuite/gas/riscv/vector-insns-fail-vsew.d: New testcase for an illegal vsew. * testsuite/gas/riscv/vector-insns-fail-vsew.l: Likewise. * testsuite/gas/riscv/vector-insns-fail-vsew.s: Likewise.
2022-12-14x86: adjust type checking constructsJan Beulich1-2/+2
As Alan points out, ASAN takes issue with these constructs, for current_templates being NULL. Wrap them in sizeof(), so the expressions aren't actually evaluated.
2022-12-13gas: re-work line number tracking for macros and their expansionsJan Beulich62-2592/+9757
The PR gas/16908 workaround aimed at uniformly reporting line numbers to reference macro invocation sites. As mentioned in a comment this may be desirable for small macros, but often isn't for larger ones. As a first step improve diagnostics to report both locations, while aiming at leaving generated debug info unaltered. Note that macro invocation context is lost for any diagnostics issued only after all input was processed (or more generally for any use of as_*_where(), as the functions can't know whether the passed in location is related to [part of] the present stack of locations). To maintain the intended workaround behavior for PR gas/16908, a new as_where() is introduced to "look through" macro invocations, while the existing as_where() is renamed (and used in only very few places for now). Down the road as_where() will likely want to return a list of (file,line) pairs.
2022-12-13Arm: avoid unhelpful uses of .macro in testsuiteJan Beulich141-2306/+2237
Macros with just a single use site are a little pointless to have, and even in further cases .irp is more suitable for the purpose. Expand such inline, avoiding the need to touch the testcases when diagnostics are changed for code resulting from macro expansion. While there also make what was "iter_mla" in sp-usage-thumb2-relax cover smlatt as well, rather than testing smlabt twice.
2022-12-12x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich9-12/+189
PR gas/29524 Having templates with a suffix explicitly present has always been quirky. After prior adjustment all that's left to also eliminate the anomaly from move-with-sign-extend is to consolidate the insn templates and to make may_need_pass2() cope (plus extend testsuite coverage).
2022-12-12x86: drop (now) stray IsStringJan Beulich1-9/+7
The need for them on the operand-less string insns has gone away with the removal of maybe_adjust_templates() and associated logic. Since i386_index_check() needs adjustment then anyway, take the opportunity and also simplify it, possible again as a result of said removal (plus the opcode template adjustments done here).
2022-12-12x86: move bad-use-of-TLS-reloc checkJan Beulich1-32/+35
Having it in match_template() is unhelpful. Neither does looking for the next template to possibly match make any sense in that case, nor is the resulting diagnostic making clear what the problem is. While moving the check, also generalize it to include all SIMD and VEX- encoded insns. This way an existing conditional can be re-used in md_assemble(). Note though that this still leaves a lof of insns which are also wrong to use with these relocations. Further fold the remaining check (BFD_RELOC_386_GOT32) with the XRELEASE related one a few lines down. This again allows re-using an existing conditional.
2022-12-12x86-64: allow HLE store of accumulator to absolute 32-bit addressJan Beulich4-5/+26
In commit 1212781b35c9 ("ix86: allow HLE store of accumulator to absolute address") I was wrong to exclude 64-bit code. Dropping the check also leads to better diagnostics in 64-bit code ("MOV", after all, isn't invalid with "XRELEASE"). While there also limit the amount of further checks done: The operand type checks that were there were effectively redundant with other ones anyway, plus it's quite fine to also have "xrelease mov <disp>, %eax" look for the next MOV template (in fact again also improving diagnostics).
2022-12-12ix86: don't recognize/derive Q suffix in the common caseJan Beulich14-51/+140
Have its use, except where actually legitimate, result in the same "only supported in 64-bit mode" diagnostic as emitted for other 64-bit only insns. Also suppress deriving of the suffix in Intel mode except in the legitimate cases. This in exchange allows dropping the respective code from match_template(). To maintain reasonable diagnostics (in particular to avoid "`mov' is only supported in 64-bit mode" on the SIMD forms of MOVQ) we need to defer parse_insn()'s emitting of errors unrelated to prefix parsing. Utilize i.error just like match_template() does. Oddly enough despite gcc's preference towards FILDQ and FIST{,T}Q we had no testcase whatsoever for these. Therefore such tests are being added. Note that the removed line in the x86-64-lfence-load testcase was redundant with the exact same one a few lines up.
2022-12-12x86: re-work insn/suffix recognitionJan Beulich7-163/+195
Having templates with a suffix explicitly present has always been quirky. Introduce a 2nd matching pass in case the 1st one couldn't find a suitable template _and_ didn't itself already need to trim off a suffix to find a match at all. This requires error reporting adjustments (albeit luckily fewer than I was afraid might be necessary), as errors previously reported during matching now need deferring until after the 2nd pass (because, obviously, we must not emit any error if the 2nd pass succeeds). While also related to PR gas/29524, it was requested that move-with-sign-extend be left as broken as it always was. PR gas/29525 Note that with the dropped CMPSD and MOVSD Intel Syntax string insn templates taking operands, mixed IsString/non-IsString template groups (with memory operands) cannot occur anymore. With that maybe_adjust_templates() becomes unnecessary (and is hence being removed). PR gas/29526 Note further that while the additions to the intel16 testcase aren't really proper Intel syntax, we've been permitting all of those except for the MOVD variant. The test therefore is to avoid re-introducing such an inconsistency.
2022-12-12x86: constify parse_insn()'s inputJan Beulich1-7/+8
The function doesn't alter its input buffer: Reflect this in its prototype. To avoid using any kind of cast, simply calculate the update of "line" from the function's input and output.
2022-12-12x86: revert disassembler parts of "x86: Allow 16-bit register source for LAR ↵Jan Beulich6-52/+52
and LSL" This reverts the disassembler parts of 859aa2c86dc9 ("x86: Allow 16-bit register source for LAR and LSL"), adjusting testcases as necessary. That change was itself a partial revert of c9f5b96bdab0 ("x86: correct handling of LAR and LSL"), without actually saying so. While the earlier commit was properly agreed upon, the partial revert was not, and hence should not have been committed. This is even more so that the revert part of that change wasn't even necessary to address PR gas/29844.
2022-12-12gas/codeview: avoid "shadowing" of glibc function nameJan Beulich1-4/+4
While not "index" this time, old enough glibc also has an (unguarded) declaration of fileno() in stdio.h, which triggers a "shadows a global declaration" warning with our choice of warning level and with at least some gcc versions.
2022-12-12x86: generate template sets data at build timeJan Beulich1-15/+10
Speed up gas startup by avoiding runtime allocation of the instances of type "templates". At the same time cut the memory requirement to just very little over half (not even accounting for any overhead notes_alloc() may incur) by reusing the "end" slot of a preceding entry for the "start" slot of the subsequent one.