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2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist20-1030/+36
2018-01-11gas tc-arm.c warning fixAlan Modra2-1/+6
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich13-381/+402
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich7-0/+46
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson3-0/+21
2018-01-09[Arm] Add CSDB instructionJames Greenhalgh6-0/+44
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh2-1/+6
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu5-0/+145
2018-01-08Add a description of the X86_64 assembler's .largcomm pseudo-op.Nick Clifton2-1/+16
2018-01-04RISC-V: Add 2 missing privileged registers.Jim Wilson3-24/+33
2018-01-03Update year range in copyright notice of binutils filesAlan Modra578-580/+584
2018-01-03ChangeLog rotationAlan Modra2-4407/+4421
2018-01-02Fix typo in do_mrs function in ARM assembler.Nick Clifton2-1/+7
2017-12-28RISC-V: Add missing privileged spec registers.Jim Wilson3-0/+522
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson14-0/+110
2017-12-19Correct disassembly of dot product instructions.Tamar Christina3-434/+446
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina5-3/+35
2017-12-18Resolve PR 22493 - the encoding to be used when pushing the stack pointer ont...Nick Clifton2-0/+11
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich2-38/+52
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich4-125/+146
2017-12-18x86: drop FloatReg and FloatAccJan Beulich2-11/+18
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich3-133/+138
2017-12-17x86: Check pseudo prefix without instructionH.J. Lu5-0/+32
2017-12-15x86: correct operand type checksJan Beulich2-4/+9
2017-12-15x86: correct abort checkJan Beulich2-2/+7
2017-12-14Update the address of the FSF in the copyright notice of files which were usi...Nick Clifton8-21/+31
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson3-0/+22
2017-12-13This patch enables disassembler_needs_relocs for PRU. It is needed to print c...Dimitar Dimitrov3-0/+21
2017-12-12Don't mask X_add_number containing a register numberAlan Modra2-1/+6
2017-12-08gas: xtensa: fix comparison of trampoline chain symbolsMax Filippov2-4/+28
2017-12-04Documentation fixAlan Modra2-1/+6
2017-12-04Run powerpc vle gas tests for all powerpc ELF targetsAlan Modra19-39/+58
2017-12-03Fix for texinfo 4.8.Jim Wilson2-2/+6
2017-12-01Update and clean up RISC-V gas documentation.Jim Wilson3-19/+134
2017-12-01Use consistent types for holding instructions, instruction masks, etc.Peter Bergner2-32/+44
2017-11-30x86: drop Vec_Disp8Jan Beulich2-54/+28
2017-11-30x86/Intel: issue diagnostics for redundant segment override prefixesJan Beulich6-7/+64
2017-11-30Revert "x86: Update segment register check in Intel syntax"Jan Beulich7-57/+18
2017-11-29Give Palmer co-credit for last patch.Jim Wilson1-0/+1
2017-11-29Fix riscv malloc error on small alignment after norvc.Jim Wilson5-11/+23
2017-11-29In x86 -n docs, mention that you need an explicit nop fill byte.Jim Wilson2-1/+7
2017-11-29[GAS][AARCH64]Fix a typo for IP1 register alias.Renlin Li4-2/+12
2017-11-29Support --localedir, --datarootdir and --datadirStefan Stroe2-4/+10
2017-11-29Use the record_alignment function when creating a .note section, in case the ...Nick Clifton2-2/+7
2017-11-27Compress loads/stores with implicit 0 offset.Jim Wilson7-6/+99
2017-11-27gas: xtensa: speed up find_trampoline_segMax Filippov2-1/+13
2017-11-27gas: xtensa: implement trampoline coalescingMax Filippov7-28/+341
2017-11-27gas: xtensa: reuse trampoline placement codeMax Filippov3-91/+23
2017-11-27gas: xtensa: rewrite xg_relax_trampolineMax Filippov5-301/+284
2017-11-27gas: xtensa: merge trampoline_frag into xtensa_frag_typeMax Filippov3-67/+83