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2017-11-23Fix build error with --enable-targets=all.Jim Wilson3-0/+13
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist18-96/+215
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich5-5/+28
2017-11-23x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base regJan Beulich4-2/+21
2017-11-23x86: drop redundant VSIB handling codeJan Beulich2-7/+6
2017-11-23x86: correct UDnJan Beulich9-11/+21
2017-11-23x86/Intel: don't report multiple errors for a single insn operandJan Beulich4-8/+11
2017-11-22Riscv ld-elf/stab failure and fake label cleanup.Jim Wilson10-14/+57
2017-11-22Update docs on filling text with nops.Jim Wilson2-3/+8
2017-11-22[GAS/ARM] Clarify relation between reg_expected_msgs and arm_reg_typeThomas Preud'homme2-23/+33
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss2-0/+15
2017-11-21x86: Add tests for -n option of x86 assemblerH.J. Lu5-0/+58
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss23-155/+193
2017-11-21xtensa error messageAlan Modra2-16/+11
2017-11-21mingw gas testsuite fixAlan Modra2-0/+5
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina5-2/+15
2017-11-16Correct AArch64 crypto dependencies.Tamar Christina1-0/+7
2017-11-16Update documentation for Arvm8.4-A changes to AArch64.Tamar Christina2-3/+16
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina13-0/+12823
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich3-4/+82
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich5-1/+13
2017-11-16i386: Replace .code64/.code32 with .byteH.J. Lu2-13/+13
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a int...Tamar Christina7-5/+24
2017-11-15Add support to readelf and objdump for following links to separate debug info...Nick Clifton13-12/+29
2017-11-15x86: use correct register namesJan Beulich3-0/+27
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich4-0/+28
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich9-0/+85
2017-11-14First part of fix for riscv gas lns-common-1 failure.Jim Wilson2-0/+5
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich4-1194/+1199
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich7-0/+224
2017-11-14x86: string insns don't allow displacementsJan Beulich6-33/+52
2017-11-13gas/arm64: don't emit stack pointer symbol table entriesJan Beulich2-5/+11
2017-11-13gas/ia64: fix testsuite failuresJan Beulich4-11/+18
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich4-1/+20
2017-11-13x86/Intel: don't mistake riz/eiz as base registerJan Beulich4-1/+20
2017-11-13x86-64/Intel: issue diagnostic for out of range displacementJan Beulich5-29/+56
2017-11-09Fix riscv dwarf2-10 gas testsuite failure.Jim Wilson2-1/+5
2017-11-09Enable the Dot Product extension by default for Armv8.4-a.Tamar Christina3-0/+17
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina6-0/+555
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina2-0/+17
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina2-0/+11
2017-11-08Fix typo in changelogNick Clifton1-1/+1
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton2-1/+13
2017-11-08Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang12-3/+1552
2017-11-08xtensa message pluralizationAlan Modra2-4/+18
2017-11-07RISC-V: Fix riscv g++ testsuite EH failures.Jim Wilson5-0/+47
2017-11-07RISC-V: Add satp as an alias for sptbrPalmer Dabbelt5-0/+23
2017-11-07This patch similarly to the AArch64 one enables Dot Product support by defaul...Tamar Christina2-68/+87
2017-11-07bundle_lock message tidyAlan Modra3-13/+20
2017-11-07readelf ngettext fixesAlan Modra32-132/+167
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