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Adjust the gas testsuite to suit commit de203ed568f6.
* testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d:
Expect data alignment of -8. Tidy.
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PR gas/31752
These are effectively macro-like, without any separate macro definition.
They already support \@, so they would better also support \+. This
allows, where desired, to get away without maintaining an explicit count
variable in source code.
With this the recently introduced testcase doesn't need any xfails
anymore.
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The present handling of inner double quotes can lead to very strange
diagnostics. Follow one of the two possible interpretations of the doc:
@dots{} referring to possibly multiple white space separated
@var{values}, each of which may be quoted. The original implementation,
prior to 465e5617233f ("PR gas/3856"), hints at the other possible
interpretation: When quoted there's only a single @var{values}, with
inner quotes taken as ordinary characters. That, however, seems overall
less useful to me.
While touching the documentation, mirror the (inverse) spelling
correction (@section line inconsistent with actual description) to .irp
as well.
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As already suggested during review, rather than having an extra
conditional in build_modrm_byte() (a code path used for quite a few
more insns, including even certain GPR ones), adjust the attribute in
the installed template to properly describe things with operands
swapped.
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These run after template matching. Therefore operands are already known
to match the template in use. With the loop bodies skipping anything not
a GPR in the actual operands, there's therefore no need to check the
template's operand type for permitting Reg or Accum.
At the same time bring the three functions in sync for the "byte" part
of the logic, as far as checking the template for other sizes (qword
specifically) goes. Plus drop a stale comment from check_qword_reg(),
when all three are now behaving the same in this regard.
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Properly reject inappropriate suffixes (No_lSuf / No_qSuf mistakenly
omitted by cf665fee1d6c ["x86: re-work AVX512 embedded rounding / SAE"]),
to avoid emitting bad or arbitrarily guessed instructions. Interestingly
check_{long,qword}_suffix() don't help here, which perhaps is another
indication that the way they work right now isn't quite appropriate.
Sadly correcting just the templates breaks operand ambiguity detection,
since so far that worked from a single template permitting more than one
suffix. Here we have ambiguity though which can now be noticed only when
taking all (matching) templates together. Therefore we need to determine
further matching templates (see code comments for constraints), to then
accumulate permitted suffixes across all of them.
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A build with --enable-maintainer-mode is currently failing with:
make[4]: *** No rule to make target '<SRC>/gas/config/te-ia64aix.h',
needed by '<SRC>/gas/po/gas.pot'. Stop.
make[4]: Leaving directory '<$OBJ>/gas/po'
make[3]: *** [Makefile:1695: all-recursive] Error 1
...
As config/te-ia64aix.h is now removed, remove the corresponding fragment
from the makefile.
gas/
* Makefile.am: Remove config/te-ia64aix.h.
* Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
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This patch fixes a mistake in the encoding of the system register
pmsdsfr_el1.
Reference:
https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers/PMSDSFR-EL1--Sampling-Data-Source-Filter-Register?lang=en
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This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc.
Since the spec only recommends one form of setzu, I won't be adding
set<cc>reg32/reg64 support in this patch.
gas/ChangeLog:
* config/tc-i386.c (build_apx_evex_prefix): Handle ZU.
* testsuite/gas/i386/x86-64.exp: Added new tests for ZU.
* testsuite/gas/i386/x86-64.exp: Added new tests for ZU.
* testsuite/gas/i386/x86-64-apx-zu-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto.
* testsuite/gas/i386/x86-64-apx-zu.d: Ditto.
* testsuite/gas/i386/x86-64-apx-zu.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~
PREFIX_EVEX_MAP4_4F.
* i386-dis-evex.h: Ditto.
* i386-dis.c (struct dis386): Add new micro 'ZU'.
(putop): Handle %ZU.
* i386-gen.c: Added ZU.
* i386-opc.h: Ditto.
* i386-opc.tbl: Added new templates to support ZU.
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Resulting code will do better without the extra conditional branch.
Remove "i.rex" to eliminate extra conditional branch.
gas/ChangeLog:
* config/tc-i386.c (establish_rex): Remove i.rex.
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Since APX supports EVEX from legacy instructions, we need to check
the 8-bit old registers in EVEX format. And add test cases for it.
gas/ChangeLog:
* config/tc-i386.c (md_assemble): Add invalid check for old byte
registers in EVEX format.
* testsuite/gas/i386/x86-64-apx-inval.l: Add new test.
* testsuite/gas/i386/x86-64-apx-inval.s: Ditto.
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Split "REX/REX2 old register checking" and "add empty rex prefix"
into two separate branches.
gas/ChangeLog:
* config/tc-i386.c (establish_rex): Split the judgments.
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A previous commit 80ec235 fixed the memory leaks, but brought to light
that the code should ideally make consistent use of snprintf and not
allocate/free more buffers than necessary.
gas/
* ginsn.c (ginsn_dst_print): Use snprintf consistently.
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With BFD not supporting that target anymore, GAS can't possibly support
it either.
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to DW_CFA_def_cfa
The DWARF specification (especially, DWARF4 and 5 [1,2]) states that
DW_CFA_def_cfa_register cannot be used as the first CFI operation.
It said DW_CFA_def_cfa_register as follows:
... This operation is valid only if the current CFA rule is defined
to use a register and offset.
So, DW_CFA_def_cfa_register can be used after that other definition
operation such as DW_CFA_def_cfa is called. However, the current gas
code emits DW_CFA_def_cfa_register as an initial CFI operation for RISCV.
In the libgcc, the unwinding function does not care about it, so it can
unwind the call stack. However, on the third party library such as
libunwindstack in Android, it causes a fatal error.
This patch changes the initial CFI operation to DW_CFA_def_cfa with
offset 0. It works as same as the previous one, but it does not have
any limitation so it satisfies the DWARF spec. This change resolves
the compatibility issue while preserving the original behaviour.
[1] DWARF4 specification, https://dwarfstd.org/doc/DWARF4.pdf
[2] DWARF5 specification, https://dwarfstd.org/doc/DWARF5.pdf
Signed-off-by: Sung-hun Kim <sfoon.kim@samsung.com>
Reviewed-By: Andrew Burgess <aburgess@redhat.com>
Approved-By: Nelson Chu <nelson@rivosinc.com>
gas/
PR 31733
config/tc-riscv.c (riscv_cfi_frame_initial_instructions): Use
DW_CFA_def_cfa rather than DW_CFA_def_cfa_register.
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It's opcode was wrong, as was e.g. easily visible from the inappropriate
testcase expectation.
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Like their byte, half, word, and doubleword counterparts their
immediates are multiples of 3 / 4 respectively.
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Set DWARF2_CIE_DATA_ALIGNMENT (data alignment factors) to -8.
It helps to save space.
Data Alignment Factor
A signed LEB128 encoded value that is factored out of all offset
instructions that are associated with this CIE or its FDEs. This value
shall be multiplied by the register offset argument of an offset
instruction to obtain the new offset value.
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gas/
* gen-sframe.c (output_sframe_internal): Use BP instead of FP.
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Add the SME2 variant of the FP8 convert and scale
instructions, enabled at assembly-time using the `+sme2+fp8'
architectural extension flag. More specifically, support is
added for the following instructions:
Multi-vector floating-point convert from FP8 to
BFloat16 (in-order):
-----------------------------------------------
- bf1cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
- bf2cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
Multi-vector floating-point convert from FP8 to
deinterleaved BFloat16:
-----------------------------------------------
- bf1cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
- bf2cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
Multi-vector floating-point convert from BFloat16
to packed FP8 format:
-------------------------------------------------
- bfcvt <Zd>.B, { <Zn1>.H-<Zn2>.H }
Multi-vector floating-point convert from FP8 to
half-precision (in-order):
-----------------------------------------------
- f1cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
- f2cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
Multi-vector floating-point convert from FP8 to
deinterleaved half-precision:
-----------------------------------------------
- f1cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
- f2cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
Multi-vector floating-point convert from half-precision
to packed FP8 format:
-------------------------------------------------------
fcvt_2h
Multi-vector floating-point convert from single-precision
to packed FP8 format:
---------------------------------------------------------
fcvt_4s
Multi-vector floating-point convert from single-precision
to interleaved FP8 format:
---------------------------------------------------------
- fcvtn <Zd>.B, { <Zn1>.S-<Zn4>.S }
Multi-vector floating-point adjust exponent by vector:
------------------------------------------------------
- fscale { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H },
<Zm>.H
- fscale { <Zdn1>.S-<Zdn2>.S }, { <Zdn1>.S-<Zdn2>.S },
<Zm>.S
- fscale { <Zdn1>.D-<Zdn2>.D }, { <Zdn1>.D-<Zdn2>.D },
<Zm>.D
Multi-vector floating-point adjust exponent:
--------------------------------------------
- fscale { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H },
{ <Zm1>.H - <Zm2>.H }
- fscale { <Zdn1>.S-<Zdn2>.S }, { <Zdn1>.S-<Zdn2>.S },
{ <Zm1>.S - <Zm2>.S }
- fscale { <Zdn1>.D-<Zdn2>.D }, { <Zdn1>.D-<Zdn2>.D },
{ <Zm1>.D - <Zm2>.D }
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Add the SVE2 variant of the FP8 convert and scale instructions,
enabled at assembly-time using the `+sve2+fp8' architectural
extension flag. More specifically, support is added for the
following instructions:
FP8 convert to BFloat16 (bottom/top):
-------------------------------------
- bf1cvt Z<d>.H, Z<n>.B
- bf2cvt Z<d>.H, Z<n>.B
- bf1cvtlt Z<d>.H, Z<n>.B
- bf2cvtlt Z<d>.H, Z<n>.B
FP8 convert to half-precision (bottom/top):
-------------------------------------------
- f1cvt Z<d>.H, Z<n>.B
- f2cvt Z<d>.H, Z<n>.B
- f1cvtlt Z<d>.H, Z<n>.B
- f2cvtlt Z<d>.H, Z<n>.B
BFloat16/half-precision convert, narrow and
interleave to FP8:
-------------------------------------------
- bfcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H }
- fcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H }
Single-precision convert, narrow and interleave
to FP8 (bottom/top):
-----------------------------------------------
- fcvtnb Z<d>.B, { Z<n>1.S - Z<n>2.S }
- fcvtnt Z<d>.B, { Z<n>1.S - Z<n>2.S }
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Add the advanced SIMD variant of the FP8 convert and scale
instructions, enabled at assembly-time using the `+fp8'
architectural extension flag. More specifically, support is
added for the following instructions:
FP8 convert to BFloat16 (vector):
---------------------------------
- bf1cvtl V<d>.8H, V<n>.8B
- bf2cvtl V<d>.8H, V<n>.8B
- bf1cvtl2 V<d>.8H, V<n>.16B
- bf2cvtl2 V<d>.8H, V<n>.16B
FP8 convert to half-precision (vector):
---------------------------------------
- f1cvtl V<d>.8H, V<n>.8B
- f2cvtl V<d>.8H, V<n>.8B
- f1cvtl2 V<d>.8H, V<n>.16B
- f2cvtl2 V<d>.8H, V<n>.16B
Single-precision to FP8 convert and narrow (vector):
----------------------------------------------------
- fcvtn V<d>.8B, V<n>.4S, V<m>.4S
- fcvtn2 V<d>.16B, V<n>.4S, V<m>.4S
Half-precision to FP8 convert and narrow (vector):
--------------------------------------------------
- fcvtn V<d>.8B, V<n>.4H, V<m>.4H
- fcvtn V<d>.16B, V<n>.8H, V<m>.8H
Floating-point adjust exponent by vector:
-----------------------------------------
- fscale V<d>.4H, V<n>.4H, V<m>.4H
- fscale V<d>.8H, V<n>.8H, V<m>.8H
- fscale V<d>.2S, V<n>.2S, V<m>.2S
- fscale V<d>.4S, V<n>.4S, V<m>.4S
- fscale V<d>.2d, V<n>.2d, V<m>.2d
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that do not support it.
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This hunk of code in move_or_literal_pool just looks wrong, but I
can't find a testcase that will tickle it to prove it. It looks a bit
like it was intended to catch cases where a bignum contained a
floating-point value, but there were a number of problems with it.
- It tested X_add_number == -1, but an FP bignum is indicated by any
value <= 0.
- It converted the floating-point value to extended precision, but
that's not used on Arm beyond the legacy FPA code. No attempt was
made to match the FP value to the intended memory/mov operation.
Since I can't construct a viable testcase, I've just removed the existing
code and made the function error out in this case: this seems more sensible
than generating wrong code or trying to write something more complex that
can't be tested anyway.
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spu-elf and z80-coff fail this test due to "def" being a pseudo-op.
tic30-unknown-coff fails it due to '#' not starting comments.
* testsuite/gas/macros/altmacro.s: Use /* */ comments. Rename
DEF to EDF.
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.irp and .irpc receive a null macro_entry. \+ causes a crash after the
recent \+ support. Restore the previous behavior.
Signed-off-by: Fangrui Song <maskray@gcc.gnu.org>
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We should revisit sysreg feature enablement and dependencies in future, but
this change should help until then.
OK for master?
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This matches the existing behaviour in GCC and LLVM, and also the current
documentation.
OK for master?
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This patch rewrites assembly tests to use utils macros declared in
sysreg-test-utils.inc. Some tests were adapted to use the new macro
rw_sys_reg.
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This patch aims at grouping write and read for a same system register
one after another so that the diff for the macro replacement does not
generate too much noise.
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This patch aims at making easier to replacement of read and write
instructions to system registers by a macro that will use the same
registers for read and write.
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This patch removes the instruction addresses from the objdump's expected
output (.d files). The intended benefit from this clean-up is to allow to
swap lines around more easilly, and removes the noise of patches that add,
remove or reorder instructions.
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Finally, update the documentation and add a NEWS item.
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Remove the patterns to match Maverick co-processor instructions from
the disassembly tables.
This required fixing a couple of tests in the assembler testsuite
where we, probably incorrectly, disassembled generic co-processor
instructions as a Maverick instruction (it particularly made no sense
to do this for Armv6t2 in Thumb state).
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Delete all the Maverick instructions and register handling from the
assembler. We continue to recognize -mcpu=ep9312, but treat it as an
alias for arm920t. We no-longer recognize -mfpu=maverick.
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Before removing the code itself, remove the tests that will no-longer
apply.
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a macro has been invoked.
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* https://github.com/riscv/riscv-b/tags
Added standard B extension back, which implies Zba, Zbb and Zbs extensions.
* https://github.com/riscv/riscv-zaamo-zalrsc/tags
Splited standard A extension into two new extensions, Zaamo and Zalrsc.
The A extension implies Zaamo and Zalrsc extensions.
Not sure if we need to do the similar check as i and zicsr/zifencei.
Passed riscv[32|64]-[elf/linux] binutils testcases.
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules
for A and B extensions. The A implies Zaamo and Zalrsc, the
B implies Zba, Zbb and Zbs.
(riscv_supported_std_ext): Supported B extension with v1.0.
(riscv_supported_std_z_ext): Supported Zaamo and Zalrsc with v1.0.
(riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Updated.
include/
* opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_A, Added
INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC.
opcodes/
* riscv-opc.c (riscv_opcodes): Splited standard A extension into two
new extensions, Zaamo and Zalrsc.
gas/
* testsuite/gas/riscv/march-imply-a.d: New testcase.
* testsuite/gas/riscv/march-imply-b.d: New testcase.
* testsuite/gas/riscv/attribute-01.d: Updated.
* testsuite/gas/riscv/attribute-02.d: Updated.
* testsuite/gas/riscv/attribute-03.d: Updated.
* testsuite/gas/riscv/attribute-04.d: Updated.
* testsuite/gas/riscv/attribute-05.d: Updated.
* testsuite/gas/riscv/attribute-10.d: Updated.
* testsuite/gas/riscv/mapping-symbols.d: Updated.
* testsuite/gas/riscv/march-imply-g.d: Updated.
* testsuite/gas/riscv/march-imply-unsupported.d: Updated.
* testsuite/gas/riscv/march-ok-reorder.d: Updated.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Updated.
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gas/ChangeLog:
* config/tc-i386.c (build_modrm_byte): Dropped the use of
extension_opcode to encode the vvvv register.
* testsuite/gas/i386/x86-64-sse2avx.d: Added new testcases.
* testsuite/gas/i386/x86-64-sse2avx.s: Diito.
opcodes/ChangeLog:
* i386-opc.tbl: Added DstVVVV to some extension_opcode instructions.
* i386-tbl.h: Regenerated.
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gas/ChangeLog:
* config/tc-i386.c (build_modrm_byte): Dropped the use of
SWAP_SOURCES to encode the vvvv register.
opcodes/ChangeLog:
* i386-opc.h (SWAP_SOURCES): Dropped.
(NO_DEFAULT_MASK): Adjusted the value.
(ADDR_PREFIX_OP_REG): Ditto.
(DISTINCT_DEST): Ditto.
(IMPLICIT_STACK_OP): Ditto.
(VexVVVV_SRC2): New.
* i386-opc.tbl: Dropped SwapSources and replaced its VexVVVV
with Src1VVVV.
* i386-tbl.h: Regenerated.
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Use vexvvvv as the switch state, and replace VexVVVV with Src1VVVV.
Src1VVVV means using VEX.vvvv encodes the first source register
operand. The old logic did not check vexvvvv first, which made the
logic here very complicated.
gas/ChangeLog:
* config/tc-i386.c (optimize_encoding): Replaced 1 with Src1VVVV.
(build_modrm_byte): Used vexvvvv to encode the vvvv register.
(s_insn): Replaced 1 with Src1VVVV.
opcodes/ChangeLog:
* i386-opc.h (VexVVVV_DST): Adjusted the value.
(Src1VVVV): New.
* i386-opc.tbl: Replaced part VexVVVV with Src1VVVV.
* i386-tbl.h: Regenerated.
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Since {vex}/{vex3} are respected on legacy mnemonics when -msse2avx is
in use, {evex} should be respected, too. So far this is the case only
for insns where eGPR-s can come into play. Extend coverage to insns with
only %xmm register and possibly immediate operands.
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Legacy encoded SIMD insns are converted to AVX ones in that mode. When
eGPR-s are in use, i.e. with APX, convert to AVX10 insns (where
available; there are quite a few which can't be converted).
Note that LDDQU is represented as VMOVDQU32 (and the prior use of the
sse3 template there needs dropping, to get the order right).
Note further that in a few cases, due to the use of templates, AVX512VL
is used when AVX512F would suffice. Since AVX10 is the main reference,
this shouldn't be too much of a problem.
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In certain cases we were calculating the jump displacement incorrectly
when deciding whether to relax a branch. This meant for some branches,
such as a very long backwards conditional branch, relaxation was not
done when it should have been. The result was to error later, because
the actual jump displacement was too large to fit in the original
instruction.
This patch fixes up the displacement calculation so that those branches
are correctly relaxed and no longer result in an error. In addition, it
changes md_convert_frag to install fixups for the JAL instructions in
the resulting relaxations rather than encoding the displacement value
directly.
gas/
* config/tc-bpf.c (relaxed_branch_length): Correct displacement
calculation when relaxing.
(md_convert_frag): Likewise. Install fixups for JAL
instructions resulting from relaxation.
* testsuite/gas/bpf/jump-relax-ja-be.d: Correct and expand test.
* testsuite/gas/bpf/jump-relax-ja.d: Likewise.
* testsuite/gas/bpf/jump-relax-ja.s: Likewise.
* testsuite/gas/bpf/jump-relax-jump-be.d: Likewise.
* testsuite/gas/bpf/jump-relax-jump.d: Likewise.
* testsuite/gas/bpf/jump-relax-jump.s: Likewise.
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Gas should not emit ADD/SUB relocation pairs for label differences
if they are in the same section without code flag even relax enabled.
Because the real value is not be affected by relaxation and it can be
compute out in assembly stage. Thus, correct the `TC_FORCE_RELOCATION
_SUB_SAME` and the label differences in same section without code
flag can be resolved in fixup_segment().
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