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2024-05-24Re: LoongArch: gas: Adjust DWARF CIE alignment factorsAlan Modra1-22/+22
2024-05-24gas: extend \+ support to .irp / .irpcJan Beulich6-23/+24
2024-05-24gas: adjust handling of quotes for .irpcJan Beulich5-21/+40
2024-05-24x86: simplify VexVVVV_SRC2 handling for the XOP caseJan Beulich1-9/+5
2024-05-24x86: simplify / consolidate check_{word,long,qword}_reg()Jan Beulich1-16/+4
2024-05-24x86: correct VCVT{,U}SI2SDJan Beulich3-5/+56
2024-05-22restore build with --enable-maintainer-modeIndu Bhagat3-3/+0
2024-05-22aarch64: fix incorrect encoding for system register pmsdsfr_el1Matthieu Longo1-2/+2
2024-05-22Support APX zero-upperCui, Lili7-2/+288
2024-05-22X86: Remove "i.rex" to eliminate extra conditional branchCui, Lili1-1/+1
2024-05-22Add check for 8-bit old registers in EVEX formatCui, Lili3-3/+9
2024-05-22x86: Split REX/REX2 old registers judgment.Cui, Lili1-16/+14
2024-05-21gas: ginsn: remove unnecessary buffer allocation and freeIndu Bhagat1-15/+12
2024-05-21gas: drop remnants of ia64-*-aix*Jan Beulich2-24/+0
2024-05-20aarch64: Add support for the fpmr system registerClaudio Bantaloukas4-0/+23
2024-05-20RISC-V: PR31733, Change initial CFI operation from DW_CFA_def_cfa_register to...Sung-hun Kim1-1/+1
2024-05-17aarch64: correct SVE2.1 ld2q (scalar plus scalar)Jan Beulich1-1/+1
2024-05-17aarch64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate)Jan Beulich3-13/+13
2024-05-17LoongArch: gas: Adjust DWARF CIE alignment factorsmengqinggang1-5/+9
2024-05-16gas: sframe: fix typo to use FP instead of BPIndu Bhagat1-4/+4
2024-05-16aarch64: fp8 convert and scale - add sme2 insn variantsVictor Do Nascimento6-2/+623
2024-05-16aarch64: fp8 convert and scale - add sve2 insn variantsVictor Do Nascimento7-0/+313
2024-05-16aarch64: fp8 convert and scale - Add advsimd insn variantsVictor Do Nascimento5-0/+581
2024-05-16aarch64: fp8 convert and scale - add feature flags and related structuresVictor Do Nascimento2-0/+3
2024-05-16aarch64: add SPMU feature and its associated registersMatthieu Longo3-0/+27
2024-05-16Move assembler "IRP \+" test into a separate file. Add XFAILs for targets th...Nick Clifton6-9/+19
2024-05-16arm: remove incorrect handling of FP bignums in move_or_literal_poolRichard Earnshaw1-6/+24
2024-05-16Fix FAIL: macros altmacroAlan Modra1-5/+5
2024-05-15gas: Fix \+ expansion for .irp and .irpcFangrui Song3-1/+10
2024-05-15aarch64: Add sysreg features to +d128 dependenciesAndrew Carlotti1-2/+5
2024-05-15aarch64: Add simd dependency to +sha2Andrew Carlotti1-1/+1
2024-05-15aarch64: testsuite: share test utils macros and use themMatthieu Longo23-519/+576
2024-05-15aarch64: testsuite: reorder write and read to match macro orderMatthieu Longo11-292/+286
2024-05-15aarch64: testsuite: use same regs for read and write testsMatthieu Longo8-377/+377
2024-05-15aarch64: testsuite: replace instruction addresses by regexMatthieu Longo1-28/+28
2024-05-14Fix gas's 'macro count' test for various targetsNick Clifton2-10/+15
2024-05-14arm: update documentation for removal of the Maverick extensionRichard Earnshaw1-7/+4
2024-05-14arm: opcodes: remove Maverick disassembly.Richard Earnshaw2-8/+8
2024-05-14arm: remove Maverick support from the assembler.Richard Earnshaw1-179/+4
2024-05-14arm: remove tests for Maverick FPU extensionsRichard Earnshaw12-2010/+0
2024-05-13Add new assembler macro pseudo-variable \+ which counts the number of times a...Nick Clifton10-14/+77
2024-05-08RISC-V: Support B, Zaamo and Zalrsc extensions.Nelson Chu13-10/+25
2024-05-06x86: Drop using extension_opcode to encode vvvv registerCui, Lili3-6/+17
2024-05-06x86: Drop SwapSourcesCui, Lili1-8/+11
2024-05-06x86: Use vexvvvv as the switch state to encode the vvvv registerCui, Lili1-15/+17
2024-05-03x86/APX: further extend SSE2AVX coverageJan Beulich3-0/+974
2024-05-03x86/APX: extend SSE2AVX coverageJan Beulich7-3/+613
2024-04-25bpf: fix calculation when deciding to relax branchDavid Faust7-43/+95
2024-04-25LoongArch: gas: Simplify relocations in sections without code flagJinyang He3-3/+19
2024-04-23arm: Fix MVE vmla encodingClaudio Bantaloukas3-1355/+2041