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2023-10-08Add testsuits for new assembler option of mthin-add-sub.gdb-14-branchpointcailulu6-24/+131
2023-10-08as: add option for generate R_LARCH_32/64_PCREL.cailulu2-6/+36
Some older kernels cannot handle the newly generated R_LARCH_32/64_PCREL, so the assembler generates R_LARCH_ADD32/64+R_LARCH_SUB32/64 by default, and use the assembler option mthin-add-sub to generate R_LARCH_32/64_PCREL as much as possible. The Option of mthin-add-sub does not affect the generation of R_LARCH_32_PCREL relocation in .eh_frame.
2023-10-07Revert "opcodes: microblaze: Add new bit-field instructions"Michael J. Eager1-76/+1
This reverts commit 6bbf249557ba17cfebe01c67370df4da9e6a56f9. Maciej W. Rozycki <macro@orcam.me.uk>: Yet it has caused numerous regressions: microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges microblaze-elf +FAIL: binutils-all/pr26548 microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output) microblaze-elf +FAIL: readelf --debug-dump=loc locview-1 (reason: unexpected output) Yet it has caused numerous regressions: microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges microblaze-elf +FAIL: binutils-all/pr26548 microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output) ...
2023-10-06opcodes: microblaze: Add new bit-field instructionsNeal Frager1-1/+76
This patches adds new bsefi and bsifi instructions. BSEFI- The instruction shall extract a bit field from a register and place it right-adjusted in the destination register. The other bits in the destination register shall be set to zero. BSIFI- The instruction shall insert a right-adjusted bit field from a register at another position in the destination register. The rest of the bits in the destination register shall be unchanged. Further documentation of these instructions can be found here: https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-05aarch64: Enable Cortex-X4 CPUSaurabh Jha4-1/+12
2023-10-02Fix memory leak in RiscV assembler.Nick Clifton2-0/+7
PR 30861 * config/tc-riscv.c (riscv_insert_uleb128_fixes): Release duplicated memory.
2023-09-29tc-microblaze.c - int compare for X_add_number.Neal Frager1-1/+1
The range check should be checking for the range ffffffff80000000..7fffffff, not ffffffff70000000. This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-09-28Added support in gas for mlittle-endian and mbig-endian flags as options.Michael J. Eager3-1/+22
Updated show usage for MicroBlaze specific assembler options to include new entries. This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> --- V1->V2: - removed new options which were unnecessary - added documentation for MicroBlaze specific options Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-09-27x86: prefer VEX encodings over EVEX ones when possibleJan Beulich10-10/+246
AVX-* features / insns paralleling earlier introduced AVX512* ones can be encoded more compactly when the respective feature was explicitly enabled by the user.
2023-09-27x86: drop cpu_arch_tune_flagsJan Beulich1-22/+4
Apparently from its introduction the variable was only ever written (the only read is merely to determine whether to write it with another value). (Since, due to the need to re-indent, the adjacent lines setting cpu_arch_tune need touching anyway, switch to using PREOCESSOR_* constants where applicable, to make more obvious what the resulting state is going to be.)
2023-09-27x86: correct cpu_arch_isa_flags maintenanceJan Beulich4-47/+83
These may not be set from a value derived from cpu_arch_flags: That starts with (almost) all functionality enabled, while cpu_arch_isa_flags is supposed to track features that were explicitly enabled (and perhaps later disabled) by the user. To avoid needing to do any such adjustment in two places (each), introduce helper functions used by both command line handling and directive processing.
2023-09-27x86: fold FMA VEX and EVEX templatesJan Beulich1-0/+4
Following the folding of some generic AVX/AVX2 templates with their AVX512F counterpart ones, do this for FMA ones as well, requiring one further adjustment to cpu_flags_match().
2023-09-27x86: fold VAES/VPCLMULQDQ VEX and EVEX templatesJan Beulich1-4/+12
Following the folding of some generic AVX/AVX2 templates with their AVX512F counterpart ones, do this for VAES and VPCLMULQDQ ones as well.
2023-09-27x86: fold certain VEX and EVEX templatesJan Beulich2-5/+102
In anticipation of APX introduce logic to reduce the number of templates we have now, allowing to limit some the number of ones we then need to gain. The fundamental requirements are that - attributes be compatible, which specifically means VexW needs to be the same in the templates (which often isn't the case, for VEX encodings having far more WIG tha, EVEX ones), - the EVEX form being AVX512F (with or without AVX512VL), not any of its extensions (the same will then be required for APX - it'll need to be APX_F). Note that in check_register() there's now a redundant zmm check. Since this logic will need revisiting for APX anyway, I'd like to keep it that way for now. (Similarly a couple of if()-s which could be folded are kept separate, to reduce code churn when adding APX support.)
2023-09-27x86: tighten .insn SAE and broadcast checkingJan Beulich1-2/+3
SAE / embedded rounding are invalid when there's the memory operand, as the bit encoding this specifies broadcast in that case. Broadcast needs to be specified on the memory operand.
2023-09-27x86-64: REX.W overrides DATA_PREFIXJan Beulich1-2/+5
REX.W needs to be respected when immediate size and relocation type are determined.
2023-09-27x86-64: fix suffix-less PUSH of symbol addressJan Beulich3-1/+18
PR gas/30856 In 5cc007751cdb ("x86: further adjust extend-to-32bit-address conditions") I neglected the case of PUSH, which is the only insn allowing (proper) symbol addresses to be used as immediates (not displacements, like CALL/JMP) in the absence of any register operands. Since it defaults to 64-bit operand size, guessing an L suffix is wrong there.
2023-09-27Add support for "pcaddi rd, symbol"mengqinggang6-155/+174
Add a macro pcaddi instruction to support "pcaddi rd, symbol". pcaddi has a 20-bit signed immediate, it can address a +/- 2MB pc relative address, and the address should be 4-byte aligned.
2023-09-26aarch64: Restructure feature flag handlingRichard Sandiford1-300/+162
The AArch64 feature-flag code is currently limited to a maximum of 64 features. This patch reworks it so that the limit can be increased more easily. The basic idea is: (1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum counting bit positions. (2) Make the feature-list macros take an array index argument (currently always 0). The macros then return the aarch64_feature_set contents for that array index. An N-element array would then be initialised as: { MACRO (0), ..., MACRO (N - 1) } (3) Provide convenience macros for initialising an aarch64_feature_set for: - a single feature - a list of individual features - an architecture version - an architecture version + a list of additional features (2) and (3) use the preprocessor to generate static initialisers. The main restriction was that uses of the same preprocessor macro cannot be nested. So if a macro wants to do something for N individual arguments, it needs to use a chain of N macros to do it. There then needs to be a way of deriving N, as a preprocessor token suitable for pasting. The easiest way of doing that was to precede each list of features by the number of features in the list. So an aarch64_feature_set initialiser for three features A, B and C would be written: AARCH64_FEATURES (3, A, B, C) This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-25Revert "arc: Add new GAS tests for ARCv3."Claudiu Zissulescu17-920/+0
This reverts commit 462693a455f04fc52c1c91ffc52ea2446a086444.
2023-09-25Revert "arc: Update ARC's Gnu Assembler backend with ARCv3 ISA."Claudiu Zissulescu6-563/+241
This reverts commit f3d38d7d0b7346515ba603454feeddc58a3fc451.
2023-09-25Revert "arc: Update arc's gas tests"Claudiu Zissulescu17-53/+53
This reverts commit ef90c0991e78c28bebdd3ed31a77c05be0444191.
2023-09-25Revert "arc: Update NEWS files"Claudiu Zissulescu1-2/+0
This reverts commit a47d304b1229ecf8912fac17ee9c48d1bf3c729a.
2023-09-25arc: Update NEWS filesClaudiu Zissulescu1-0/+2
Add ARCv3 support in NEWS files. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2023-09-25arc: Update arc's gas testsClaudiu Zissulescu17-53/+53
The disassembler can recognize the alternative register names ILINK1 and ILINK2. Update tests. gas/testsuite/gas/arc xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gas/testsuite/gas/arc/adc.d: Update ILINK1/INLINK2 reg names. * gas/testsuite/gas/arc/add.d: Likewise. * gas/testsuite/gas/arc/and.d: Likewise. * gas/testsuite/gas/arc/asl.d: Likewise. * gas/testsuite/gas/arc/asr.d: Likewise. * gas/testsuite/gas/arc/bic.d: Likewise. * gas/testsuite/gas/arc/lsr.d: Likewise. * gas/testsuite/gas/arc/nps400-1.d: Likewise. * gas/testsuite/gas/arc/or.d: Likewise. * gas/testsuite/gas/arc/ror.d: Likewise. * gas/testsuite/gas/arc/sbc.d: Likewise. * gas/testsuite/gas/arc/sub.d: Likewise. * gas/testsuite/gas/arc/textinsn3op.d: Likewise. * gas/testsuite/gas/arc/warn.exp: Update predicate. * gas/testsuite/gas/arc/arc.exp: Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-25arc: Update ARC's Gnu Assembler backend with ARCv3 ISA.Claudiu Zissulescu6-241/+563
The new Synopsys ARCv3 ISA has a similar instruction format like the old ARCv1 and ARCv2 ISA. Thus, the ARCv3 addition is using whatever we have for old ARC processors plus some ARCv3 spcific mods. To distinguish between various ARC variants, we introduced two new configure defines named TARGET_ARCv3_32 and TARGET_ARCv3_64 which are set when we choose either an ARC32 (ARCv3/32) ISA toolchain or an ARC64 (ARCv3/64) ISA toolchain. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gas/config/tc-arc.h: Selectively define default target macros. * gas/configure.ac: Add ARC64 target. * gas/configure.tgt: Likewise. * gas/configure: Regenerate * gas/config.in: Regenerate. * gas/config/tc-arc.c (DEFAULT_ARCH): New macro. (default_arch): New variable. (md_pseudo_table): Add xword. (md_shortopts): Only a few options are recognized by the new ARC64 assembler. (md_longopts): Likewise. (ARC_CPU_TYPE_A64x): New define. (ARC_CPU_TYPE_A32x): Likewise. (cpu_type): New arch field. (selected_cpu): Update fields. (arc_opcode_hash_entry_iterator_init): Formating. (arc_opcode_hash_entry_iterator_next): Likewise. (arc_select_cpu): Likewise. (arc_option): Likewise. (check_cpu_feature): Likewise. (debug_exp): Recognize new expression operands. (parse_reloc_symbol): Parse new signed/unsigend cases. (parse_opcode_flags): Update for the case when the flags needs insert/extract functions. (find_opcode_match): Match new signed/unsigned 32-bit immediates. (autodetect_attributes): PLT34 only available for ARC64. (md_assemble): Extend match characters. (declare_fp_set): New function. (init_default_arch): Likewise. (md_begin): Detect and initialize the correct CPU and coresponding registers. (md_pcrel_from_section): Add new relocs. (arc_target_format): New function. (md_apply_fix): Add new relocs. (md_parse_option): Update options. (arc_show_cpu_list): Update with ARC64 cpus. (md_show_usage): Update messages. (may_relax_expr): Add PLT34 case. (assemble_insn): Update for ARC64. (arc_make_nops): New function. (arc_handle_align): Refurbish this function, use arc_make_nops. (tc_arc_fix_adjustable): Update messages. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-25arc: Add new GAS tests for ARCv3.Claudiu Zissulescu17-0/+920
Add new assembler tests for ARCv3 ISA. All the new tests are added in a distinct folder named arc64. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gas/testsuite/gas/arc64/arc64.exp: New file. * gas/testsuite/gas/arc64/float01.d: Likewise. * gas/testsuite/gas/arc64/float01.s: Likewise. * gas/testsuite/gas/arc64/ldd.d: Likewise. * gas/testsuite/gas/arc64/ldd.s: Likewise. * gas/testsuite/gas/arc64/lddl.d: Likewise. * gas/testsuite/gas/arc64/lddl.s: Likewise. * gas/testsuite/gas/arc64/load.d: Likewise. * gas/testsuite/gas/arc64/load.s: Likewise. * gas/testsuite/gas/arc64/st.d: Likewise. * gas/testsuite/gas/arc64/st.s: Likewise. * gas/testsuite/gas/arc64/std.d: Likewise. * gas/testsuite/gas/arc64/std.s: Likewise. * gas/testsuite/gas/arc64/stdl.d: Likewise. * gas/testsuite/gas/arc64/stdl.s: Likewise. * gas/testsuite/gas/arc64/stl.d: Likewise. * gas/testsuite/gas/arc64/stl.s: Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-20elf-attrs.c memory allocation failAlan Modra9-81/+137
Report errors rather than segfaulting. bfd/ * elf-attrs.c (elf_new_obj_attr): Return NULL on bfd_alloc fail. (bfd_elf_add_obj_attr_int): Handle NULL return from the above, and propagate return to callers. (elf_add_obj_attr_string, elf_add_obj_attr_int_string): Likewise. (bfd_elf_add_obj_attr_string): Similarly. (_bfd_elf_copy_obj_attributes): Report error on alloc fails. (_bfd_elf_parse_attributes): Likewise. * elf-bfd.h (bfd_elf_add_obj_attr_int): Update prototype. (bfd_elf_add_obj_attr_string): Likewise. (bfd_elf_add_obj_attr_int_string): Likewise. gas/ * config/obj-elf.c (obj_elf_vendor_attribute): Report fatal error on out of memory from bfd attribute functions. * config/tc-arc.c (arc_set_attribute_int): Likewise. (arc_set_attribute_string, arc_set_public_attributes): Likewise. * config/tc-arm.c (aeabi_set_attribute_int): Likewise. (aeabi_set_attribute_string): Likewise. * config/tc-mips.c (mips_md_finish): Likewise. * config/tc-msp430.c (msp430_md_finish): Likewise. * config/tc-riscv.c (riscv_write_out_attrs): Likewise. * config/tc-sparc.c (sparc_md_finish): Likewise. * config/tc-tic6x.c (tic6x_set_attribute_int): Likewise. * config/tc-csky.c (md_begin): Likewise. (set_csky_attribute): Return ok status.
2023-09-18Fix: Use of uninitialized memoryJacob Navia2-1/+6
* config/tc-riscv.c (riscv_ip_hardcode): Fully initialise the allocated riscv_opcode structure.
2023-09-15LoongArch: Enable gas sort relocsJinyang He1-0/+1
The md_pre_output_hook creating fixup is asynchronous, causing relocs may be out of order in .eh_frame. Define GAS_SORT_RELOCS so that reorder relocs when write_relocs. Reported-by: Rui Ueyama <rui314@gmail.com>
2023-09-15x86: fold CpuLM and Cpu64Jan Beulich1-3/+3
Now that CpuLM is used solely in cpu_arch_flags and cpu_arch[] while Cpu64 is solely used in insn templates, they no longer need to be treated different from other "ordinary" flags; the only "unusual" one left if CpuNo64. Fold both, leaving just Cpu64.
2023-09-15x86: don't play with cpu_arch_flags.cpu{,no}64Jan Beulich1-37/+6
A total four places exists where we set the two bits from flag_code, but these values are never used. The two bits are evaluated only when coming from insn templates. Drop these assignments. Also make obvious that cpu_flags_check_cpu64() is only ever used against insn templates.
2023-09-15x86: make code size vs CPU arch checking consistentJan Beulich8-6/+25
While update_code_flag() checks for LM / i386, set_cpu_arch() so far didn't, allowing e.g. 64-bit code to be emitted after ".arch generic32". Oddly enough a few of our testcases actually exhibit bad behavior (and hence need minor adjustments).
2023-09-15x86: re-order update_code_flag()Jan Beulich1-19/+16
Do checks before updating state, and bail upon failure of either of the checks. While moving the code, eliminate some redundancy.
2023-09-14x86: support AVX10.1 vector size restrictionsJan Beulich25-178/+761
Recognize "/<number>" suffixes on both -march=+avx10.1 and the corresponding .arch directive, setting an upper bound on the vector size that insns may use. Such a restriction can be reset by setting a new base architecture, by using a suffix-less form, by disabling AVX10, or by enabling any other VEX/EVEX-based vector extension. While for most insns we can suppress their use with too wide operands via registers becoming unavailable (or in Intel syntax memory operand size specifiers not being recognized), mask register insns have to have their minimum required vector size specified in a new attribute. (Of course this new attribute could also be used on other insns.) Note that .insn continues to be permitted to emit EVEX{512,256} (and VEX256 ones) encodings regardless of vector size restrictions in place. Of course these can't be expressed using zmm (or ymm) operands then, but need using the EVEX.512.* forms (broadcast forms may be usable right now, but this may go away so shouldn't be relied upon). This is why no assertions should be added to build_{e,}vex_prefix().
2023-09-14x86: support AVX10.1/512Jan Beulich82-45/+2125
Since this is merely a re-branding of certain AVX512* features, there's little code to be added. The main aspect here are new testcases. In order to be able to re-use some of the existing testcases, several of them need their start symbols adjusted. Note that 256- and 128-bit tests want adding here, as these need to work right away. Subsequently they'll gain vector length constraints. Since it was missing and is wanted here, also add an AVX512VL+VPOPCNTDQ test.
2023-09-09Make sure DW_CFA_advance_loc4 is in the same fragJinyang He1-1/+1
Do the same as commit b9d8f5601bcf in another place generating DW_CFA_advance_loc4. The idea behind commit b9d8f5601bcf was that when a DW_CFA_advance_loc4 of zero is seen in eh_frame_relax_frag and eh_frame_convert_frag we want to remove the opcode entirely, not just convert to a nop. If the opcode was split over two frags then a size adjustment would need to be done to the first frag, not just the second as is correct for other cases with split frags. This would complicate the eh relaxation. It's easier to ensure the frag is not split. * ehopt.c (check_eh_frame): Don't allow DW_CFA_advance_loc4 to be placed in a different frag to the rs_cfa.
2023-09-08aarch64: Remove unused functionRichard Sandiford1-7/+0
set_expected_error is no longer used. It has been replaced by more specific error messages.
2023-09-08x86: restrict prefix use with .insn VEX/XOP/EVEXJan Beulich1-0/+23
Avoid triggering the respective abort() in output_insn().
2023-09-08kvx: Add a testcase for bundles with KVXMAXBUNDLEWORDS syllablesPaul Iannetta3-0/+53
* testsuite/gas/kvx/fat-bundles.s: New test. * testsuite/gas/kvx/kv3-1-fat-bundles.d: New test. * testsuite/gas/kvx/kv3-2-fat-bundles.d: New test.
2023-09-07Add testcase for generation of 32/64_PCREL.cailulu4-0/+204
2023-09-07Use 32/64_PCREL to replace a pair of ADD32/64 and SUB32/64.cailulu2-12/+22
Subtraction for labels that require static relocation usually generates ADD32/64 and SUB32/64. If subsy of BFD_RELOC_32/64 and PC in same segment, and disable relax or PC at start of subsy or enable relax but not in SEC_CODE, we generate 32/64_PCREL to replace a pair of ADD32/64 and SUB32/64.
2023-09-07RISC-V: Clarify the naming rules of vendor operands.Nelson Chu2-86/+99
The vendor operands should be named starting with `X', and preferably the second letter (or multiple following letters) is enough to differentiate them from other vendors. Therefore, added letter `t' after `X' for t-head operands, to differentiate from future different vendor's operands. bfd/ * elfxx-riscv.c (riscv_supported_vendor_x_ext): Removed the vendor document link since it should already be recorded in the gas/doc/c-riscv.texi. gas/ * config/tc-riscv.c (validate_riscv_insn): Added `t' after `X' for t-head operands. Minor updates for indents and comments. (riscv_ip): Likewise. * doc/c-riscv.texi: Minor updates. opcodes/ * riscv-dis.c (print_insn_args): Added `t' after `X' for t-head operands. Minor updates for indents and comments. * riscv-opc.c (riscv_opcode): Likewise.
2023-09-07PR30828, notes obstack memory corruptionAlan Modra1-2/+6
Commit 3bab069c29b3 carelessly allowed "string" to be released from the notes obstack twice, with the second call to obstack_free releasing memory for a fixup that just happened to be the same size as the original string. The fixup then of course was overwritten. This patch fixes that problem, and another that could occur on an error path. PR 30828 * stabs.c (s_stab_generic): Don't free string twice. Don't blow away entire notes obstack on a missing string.
2023-09-05RISC-V: fold duplicate code in vector_macro()Jan Beulich1-40/+5
There's no need to have almost identical code twice. Do away with M_VMSGEU and instead simply use an unused (for these macros) field to tell apart both variants.
2023-09-05RISC-V: Fix typo in the testsuiteTsukasa OI1-1/+1
gas/ChangeLog: * testsuite/gas/riscv/csr.s: Fix typo. mhcounteren is superseded by minstretcfg, not mcyclecfg.
2023-09-05RISC-V: Add 'Smcntrpmf' extension and its CSRsTsukasa OI12-46/+214
This commit adds now stable and approved 'Smcntrpmf' extension defined by the RISC-V Cycle and Instret Privilege Mode Filtering specification. Note that, because mcyclecfg and minstretcfg CSRs conflict with the privileged specification version 1.9.1, CSRs for this extension are only enabled on the privileged specification version 1.10 or later. By checking the base privileged specification, we no longer need to change the design of base CSR handling. This is based on the specification version v1.0_rc1 (Frozen): <https://github.com/riscv/riscv-smcntrpmf/commit/32b752c40d59c1b5e95de83399c1f54be6669163> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add implication rule from the new 'Smcntrpmf' extension. (riscv_supported_std_s_ext): Add 'Smcntrpmf' to the supported S extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add new CSR classes CSR_CLASS_SMCNTRPMF and CSR_CLASS_SMCNTRPMF_32. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. Move "mscounteren" and "mhcounteren" CSRs and note that they are now aliases. * testsuite/gas/riscv/csr-dw-regnums.d: Reflect the change. * testsuite/gas/riscv/csr.s: Add new CSRs. Move "mscounteren" and "mhcounteren" CSRs and note that they are now reused for the 'Smcntrpmf' extension. * testsuite/gas/riscv/csr-version-1p9p1.d: Reflect the changes of csr.s. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h: Add new CSRs noting that this extension is incompatible with the privileged specification version 1.9.1. Move "mscounteren" and "mhcounteren" CSRs, make them aliases and reuse the CSR numbers from the 'Smcntrpmf' extension. (CSR_MSCOUNTEREN, CSR_MHCOUNTEREN) Remove as "mscounteren" and "mhcounteren" are now aliases and new CSR macros are used instead. (CSR_MCYCLECFG, CSR_MINSTRETCFG, CSR_MCYCLECFGH, CSR_MINSTRETCFGH): New CSR macros.
2023-09-05RISC-V: Prohibit combination of 'E' and 'H'Tsukasa OI2-0/+5
According to the ratified privileged specification (version 20211203), it says: > The hypervisor extension depends on an "I" base integer ISA with 32 x > registers (RV32I or RV64I), not RV32E, which has only 16 x registers. Also in the latest draft, it also prohibits RV64E with the 'H' extension. This commit prohibits the combination of 'E' and 'H' extensions. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Prohibit 'E' and 'H' combinations. gas/ChangeLog: * testsuite/gas/riscv/march-fail-rv32eh.d: New failure test to make sure that RV32E + 'H' is prohibited. * testsuite/gas/riscv/march-fail-rv32eh.l: Likewise.
2023-09-01x86: unindent most of set_cpu_arch()Jan Beulich1-151/+154
Inverting the initial if()'s condition allows to move out the bulk of the function by a level, improving readability at least a bit. While doing that also pull the push/pop handling up first, such that "else if" after "return" isn't needed anymore; the order in which special cases are checked doesn't really matter.
2023-09-01x86: rename CpuPCLMULJan Beulich1-3/+3
The name we use internally isn't in line with the SDM, and also isn't in line with CpuVPCLMULQDQ. Add the missing suffix, but of course leave alone user facing names.
generated by cgit v1.1 at 2024-07-31 21:20:07 +0000