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2021-11-30aarch64: Add missing system registers [PR27145]Richard Sandiford10-6/+877
2021-11-30aarch64: Make LOR registers conditional on +lorRichard Sandiford4-1/+13
2021-11-30aarch64: Remove ZIDR_EL1Richard Sandiford3-7/+0
2021-11-30aarch64: Allow writes to MFAR_EL3Richard Sandiford5-20/+13
2021-11-30aarch64: Mark PMSIDR_EL1 as read-onlyRichard Sandiford5-3/+8
2021-11-30aarch64: Remove duplicate system register entriesRichard Sandiford2-4/+0
2021-11-30aarch64: Check for register aliases before mnemonicsRichard Sandiford6-34/+38
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu2-0/+13
2021-11-30RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu2-68/+28
2021-11-29PR28629 NIOS2 falloutAlan Modra1-1/+1
2021-11-26gas: Update commit 4780e5e4933H.J. Lu2-2/+2
2021-11-26[gas] Fix file 0 dir with -gdwarf-5Tom de Vries3-3/+16
2021-11-25gas: enable silent build rulesMike Frysinger2-2/+42
2021-11-23Update bug reporting addressAlan Modra2-6/+2
2021-11-22RISC-V: Replace .option rvc/norvc with .option arch, +c/-c.Nelson Chu16-18/+22
2021-11-19RISC-V: Support new .option arch directive.Nelson Chu12-18/+134
2021-11-19Re: Add multibyte character warning option to the assembler.Alan Modra1-10/+10
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu6-0/+101
2021-11-18Add multibyte character warning option to the assembler.Nick Clifton14-10/+205
2021-11-18RISC-V: Add testcases for z[fdq]inxjiawei6-0/+222
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei1-1/+3
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus6-0/+348
2021-11-17aarch64: [SME] Add new SME system registersPrzemyslaw Wirkus5-0/+61
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus6-8/+122
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus16-8/+801
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus6-0/+334
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus15-1/+575
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus10-1/+872
2021-11-17aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus3-0/+19
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu19-14/+4293
2021-11-16x86: Don't allow KMOV in TLS code sequencesH.J. Lu6-5/+35
2021-11-16RISC-V: Scalar crypto instruction and entropy source CSR testcases.jiawei41-3/+490
2021-11-16RISC-V: Scalar crypto instructions and operand set.jiawei1-0/+29
2021-11-15Deal with full path in .file 0 directiveEric Botcazou8-24/+184
2021-11-15PowerPC64 @notoc in non-power10 codeAlan Modra1-0/+7
2021-11-11RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu4-92/+28
2021-11-10arm: enable Cortex-A710 CPUPrzemyslaw Wirkus4-0/+14
2021-11-10PR 28447: implement multiple parameters for .file on XCOFFClément Chigot6-1/+94
2021-11-06Modernise yyerrorAlan Modra2-5/+7
2021-11-04RISC-V: Clarify the behavior of .option rvc or norvc.Nelson Chu1-21/+18
2021-11-03asan: dlltool buffer overflow: embedded NUL in stringAlan Modra1-3/+1
2021-11-02ARM: match armeb output for unwind-pacbti-m testAlan Modra1-3/+3
2021-11-01arm: add armv9-a architecture to -marchPrzemyslaw Wirkus5-4/+41
2021-10-29Re: arm: add unwinder encoding support for PACBTIAlan Modra3-0/+59
2021-10-28ARM assembler: Allow up to 32 single precision registers in the VPUSH and VPO...Markus Klein4-17/+41
2021-10-28arm: add unwinder encoding support for PACBTITejas Belagod1-5/+57
2021-10-27RISC-V: Tidy riscv assembler and disassembler.Nelson Chu1-288/+304
2021-10-25x86: Also handle stores for -muse-unaligned-vector-moveH.J. Lu4-15/+74
2021-10-24LoongArch gas supportliuzhensong39-5/+4152
2021-10-22x86: Add -muse-unaligned-vector-move to assemblerH.J. Lu7-0/+110
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