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2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson18-24/+807
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson10-0/+372
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson3-1/+8
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich10-55/+45
2019-11-07x86: adjust register names printed for MONITOR/MWAITJan Beulich12-201/+80
2019-11-04x86: re-arrange process_operands()Jan Beulich2-57/+54
2019-10-31i386; Add .code16gcc fldenv testsH.J. Lu3-2/+20
2019-10-31Add support for context sensitive '.arch_extension' to the ARM assembler.Mihail Ionescu6-0/+68
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv6-44/+86
2019-10-30x86: add tests to cover defaulting of operand sizes for ambiguous insnsJan Beulich8-0/+392
2019-10-30x86: drop stray WJan Beulich2-5/+11
2019-10-29Re: Optimise away eh_frame advance_loc 0Alan Modra2-1/+12
2019-10-26Add some missing casts to suppress implicit cast warningsJohn David Anglin2-5/+12
2019-10-26Optimise away eh_frame advance_loc 0Alan Modra3-4/+28
2019-10-25PR25125, relaxation chooses wrong branch sizeAlan Modra2-4/+13
2019-10-16qsort: tc-xtensa.c tidyAlan Modra2-22/+33
2019-10-15remove more xmalloc in bfdAlan Modra2-6/+12
2019-10-09Fix the disassembly of the LDS and STS instructions of the AVR architecture.Nick Clifton3-0/+19
2019-10-08S/390: Add support for z15 as CPU name.Andreas Krebbel3-4/+5
2019-10-07Add support for new functionality in the msp430 backend of GCC.Jozef Lawrynowicz17-4/+252
2019-10-07add missing ChangeLog entry for d241b91073Jan Beulich1-0/+13
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich9-12/+233
2019-09-24Arm: Fix out of range conditional branch (PR/24991)Tamar Christina5-7/+38
2019-09-24[ARM]: Modify assembler to accept floating and signless datatypes for MVE ins...Srinath Parvathaneni5-6/+81
2019-09-23ecoff bfd.h tidyAlan Modra3-0/+7
2019-09-23arm bfd.h tidyAlan Modra2-0/+5
2019-09-21tc-i386.c gcc10 warning fixAlan Modra2-2/+6
2019-09-20bfd macro conversion to inline functions, sectionAlan Modra2-1/+5
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich4-4/+25
2019-09-19[gas][news] NEWS (2.33) note new SVE2 and TME instructions for AArch64Matthew Malcomson2-0/+10
2019-09-19bfd_section_* macrosAlan Modra73-370/+358
2019-09-18bfd_asymbol_* macrosAlan Modra2-2/+7
2019-09-18Re-generate many configure and Makefile.in filesSimon Marchi4-22/+14
2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson2-7/+26
2019-09-16Update version to 2.33.50 and regenerate configure scripts.Phil Blundell4-18/+36
2019-09-10Enhance the disassembler so that it will reliably determine whether a reloc a...Nick Clifton3-0/+41
2019-09-10[PATCH][ARM][GAS]: Support to MVE VCTP instruction.Srinath Parvathaneni6-0/+177
2019-09-09Add markers for 2.33 branch to NEWS and ChangeLog files.Phil Blundell2-0/+6
2019-09-05PowerPC warning on symbol+offset@gotAlan Modra2-3/+8
2019-08-30[PATCH][ARM][GAS]: Assembler support to interpret MVE VMOV instruction correc...Srinath Parvathaneni3-1/+86
2019-08-27Add support for the MVE VMOV instruction to the ARM assembler. This instruct...Srinath Parvathaneni5-202/+243
2019-08-25RISC-V: Improve li expansion for better code density.Kito Cheng5-5/+108
2019-08-23Updated Swedish translation for the gas sub-directory.Nick Clifton2-49/+26
2019-08-22Arm: Add support for missing CPUsDennis Zhang6-0/+39
2019-08-22Fix the assembler's floating point number parser so that it can correctly han...Bosco Garc?a5-7/+49
2019-08-22Implement a float16 directive for assembling 16 bit IEEE 754 floating point n...Barnaby Wilks7-5/+70
2019-08-22[AArch64][gas] Update MTE system register encodingsKyrylo Tkachov2-10/+15
2019-08-20Remove test files for a different patch accidentally committed with patch for...Nick Clifton2-35/+0
2019-08-20Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77...Dennis Zhang12-0/+112
2019-08-19MIPS/gas: Fix misaligned address errors to disregard ISA mode bitFaraz Shahbazker2-5/+32
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