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AgeCommit message (Expand)AuthorFilesLines
2022-10-03RISC-V: Add testcase for DWARF register numbersTsukasa OI2-0/+296
2022-09-30RISC-V: Relax "fmv.[sdq]" requirementsTsukasa OI6-0/+6
2022-09-30RISC-V: Reorganize and enhance 'Zfinx' testsTsukasa OI6-106/+207
2022-09-30RISC-V: Eliminate long-casts of X_add_number in diagnosticsChristoph Müllner1-8/+8
2022-09-30RISC-V: fallout from "re-arrange opcode table for consistent alias handling"Jan Beulich4-14/+14
2022-09-30RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich1-4/+4
2022-09-30RISC-V: drop stray INSN_ALIAS flagsJan Beulich2-0/+35
2022-09-30RISC-V: re-arrange opcode table for consistent alias handlingJan Beulich21-159/+375
2022-09-30x86: improve match_template()'s diagnosticsJan Beulich7-67/+86
2022-09-30x86/Intel: restrict suffix derivationJan Beulich6-61/+230
2022-09-30LoongArch: Update ELF e_flags handling according to specification.liuzhensong1-10/+10
2022-09-28The help document of as misses some many optionsNick Clifton4-34/+90
2022-09-26binutils, gdb: support zstd compressed debug sectionsFangrui Song12-47/+380
2022-09-23RISC-V: Add Zawrs ISA extension supportChristoph Müllner3-0/+25
2022-09-22RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner6-0/+88
2022-09-22RISC-V: Add support for literal instruction argumentsChristoph Müllner1-0/+10
2022-09-22RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner6-0/+137
2022-09-22RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner6-0/+85
2022-09-22RISC-V: Add T-Head MAC vendor extensionChristoph Müllner3-0/+27
2022-09-22RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner3-0/+19
2022-09-22RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner16-0/+141
2022-09-22RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner1-0/+74
2022-09-22RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner6-0/+40
2022-09-22RISC-V: Add T-Head CMO vendor extensionChristoph Müllner6-0/+103
2022-09-22RISC-V: Add generic support for vendor extensionsChristoph Müllner1-0/+14
2022-09-22RISC-V: Add macro-only operands to validate_riscv_insnTsukasa OI1-0/+3
2022-09-21RISC-V: Fix riscv_set_tso declarationTsukasa OI1-1/+1
2022-09-21RISC-V: Set EF_RISCV_TSO also on .option archTsukasa OI1-0/+3
2022-09-21RISC-V: Implement Ztso extensionShihua2-0/+19
2022-09-21RISC-V: Always generate R_RISCV_CALL_PLT reloc for call in assembler.Nelson Chu3-8/+4
2022-09-21Re: PowerPC64 pcrel got relocs against local symbolsAlan Modra1-6/+52
2022-09-21ppc/svp64: test setvl ms operandDmitry Selyutin2-0/+2
2022-09-20LoongArch: Set macro SUB_SEGMENT_ALIGN to 0.liuzhensong1-0/+2
2022-09-16PowerPC64 pcrel got relocs against local symbolsAlan Modra1-0/+6
2022-09-16RISC-V: Make g imply zmmul extension.Nelson Chu8-8/+8
2022-09-15bfd, binutils, gas: Remove/mark unused variablesTsukasa OI1-3/+0
2022-09-14bfd: Stop using -Wstack-usage=262144 when built with ClangTsukasa OI1-0/+18
2022-09-12ppc: Document the -mfuture and -Mfuture options and make them usablePeter Bergner2-0/+5
2022-09-10Re: PR29466, APP/NO_APP with linefileAlan Modra1-1/+1
2022-09-09RISC-V: Fix vector CSR requirementsTsukasa OI5-57/+57
2022-09-08Gas generated incorrect debug info (top-level DW_TAG_unspecified_type DIE)Nick Clifton6-30/+50
2022-09-07LoongArch: fix gas BFD_RELOC_8/16/24 bugmengqinggang3-18/+58
2022-09-02RISC-V: Print highest address (-1) on the disassemblerTsukasa OI6-0/+71
2022-09-02RISC-V: PR29342, Fix RV32 disassembler address computationTsukasa OI4-1/+135
2022-09-02RISC-V: Add address printer tests with ADDIWTsukasa OI3-0/+64
2022-08-31Add OpenBSD AArch64 GAS support.Frederic Cambus2-0/+5
2022-08-30Add a testcase for PR 29494.Nick Clifton3-0/+10001
2022-08-30LoongArch: Fix redefinition of "PACKAGE".liuzhensong1-1/+1
2022-08-30RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI15-2/+143
2022-08-28PR29494 Trailing jump table on ARMAlan Modra1-6/+6
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