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2023-06-15GAS/doc: Correct Tag_GNU_MIPS_ABI_MSA attribute descriptionMaciej W. Rozycki1-3/+4
Rewrite the paragraph to match the style of Tag_GNU_MIPS_ABI_FP text immediately above, correcting grammar and formatting at the same time. gas/ * doc/as.texi (MIPS Attributes): Correct Tag_GNU_MIPS_ABI_MSA attribute description.
2023-06-15Revert "MIPS: gas: alter 64 or 32 for mipsisa triples if march is implicit"Maciej W. Rozycki2-162/+122
This reverts commit 094025a30bb2da19df3990e0c0ff8167af823aa1. It was applied unapproved.
2023-06-15Revert "MIPS: default r6 if vendor is img"Maciej W. Rozycki2-14/+2
This reverts commit be0d391f22fe6009c3be907753975a984cbbcc23. It was applied unapproved.
2023-06-15Revert "MIPS: fix r6 testsuites"Maciej W. Rozycki155-354/+183
This reverts commit ffc528aed56b9e2c171137da28690a9bb6861b0b. It was applied unapproved.
2023-06-15Revert "MIPS: fix -gnuabi64 testsuite"Maciej W. Rozycki35-682/+461
This reverts commit cb81e84c72933a7fad10b75b7e270d92d8d65251. It was applied unapproved.
2023-06-15Revert "MIPS: add MT ASE support for micromips32"Maciej W. Rozycki5-637/+7
This reverts commit acce83dacff0ce43677410c67aaae32817afe991. It was applied unapproved.
2023-06-14asprintf memory leaksAlan Modra1-1/+5
A number of backends want to return bfd_reloc_dangerous messaqes from relocation special_function, and construct the message using asprintf. Such messages are not freed anywhere, leading to small memory leaks inside libbfd. To limit the leaks, I'd implemented a static buffer in the ppc backends that was freed before use in asprintf output. This patch extends that scheme to other backends using a shared static buffer and goes further in freeing the buffer on any bfd_close. The patch also fixes a few other cases where asprintf output was not freed after use. bfd/ * bfd.c (_input_error_msg): Make global and rename to.. (_bfd_error_buf): ..this. (bfd_asprintf): New function. (bfd_errmsg): Use bfd_asprintf. * opncls.c (bfd_close_all_done): Free _buf_error_buf. * elf32-arm.c (find_thumb_glue, find_arm_glue): Use bfd_asprintf. * elf32-nios2.c (nios2_elf32_relocate_section): Likewise. * elf32-ppc.c (ppc_elf_unhandled_reloc): Likewise. * elf64-ppc.c (ppc64_elf_unhandled_reloc): Likewise. * elfnn-riscv.c (riscv_resolve_pcrel_lo_relocs): Likewise. (riscv_elf_relocate_section): Likewise. * libbfd.h: Regenerate. gas/ * read.c (read_end): Free current_name and current_label. (do_s_func): Likewise on error path. strdup label. ld/ * pe-dll.c (make_head, make_tail, make_one), (make_singleton_name_thunk, make_import_fixup_entry), (make_runtime_pseudo_reloc), (pe_create_runtime_relocator_reference: Free oname after use.
2023-06-12LoongArch: gas: Relocations simplification when -mno-relaxmengqinggang2-9/+26
Gas does not emit ADD/SUB relocation pairs for label differences when -mno-relax.
2023-06-09ecoff find_nearest_line and final link leaksAlan Modra2-0/+2
Freeing ecoff_debug_info "pointers to the unswapped symbolic info" isn't a simple matter, due to differing allocation strategies. In _bfd_ecoff_slurp_symbolic_info the pointers are to objalloc memory. In the ecoff linker they are to separately malloc'd memory. In gas we have most (obj-elf) or all (obj-ecoff) into a single malloc'd buffer. This patch fixes the leaks for binutils and ld, leaving the gas leaks for another day. The mips elf backend already had this covered, and the ecoff backend had a pointer, raw_syments used as a flag, so most of the patch is moving these around a little so they are accessible for both ecoff and elf. include/ * coff/ecoff.h (struct ecoff_debug_info): Add alloc_syments. bfd/ * libecoff.h (struct ecoff_tdata): Delete raw_syments. * elfxx-mips.c (free_ecoff_debug): Delete. Replace uses with _bfd_ecoff_free_ecoff_debug_info. (_bfd_mips_elf_final_link): Init debug.alloc_syments. * ecofflink.c (_bfd_ecoff_free_ecoff_debug_info): New function. * ecoff.c (_bfd_ecoff_bfd_free_cached_info): Call _bfd_ecoff_free_ecoff_debug_info. (_bfd_ecoff_slurp_symbolic_info): Replace uses of raw_syments with alloc_syments. (ecoff_final_link_debug_accumulate): Likewise. Use _bfd_ecoff_free_ecoff_debug_info. (_bfd_ecoff_bfd_copy_private_bfd_data): Set alloc_syments for copied output. * elf64-alpha.c (elf64_alpha_read_ecoff_info): Use _bfd_ecoff_free_ecoff_debug_info. * libbfd-in.h (_bfd_ecoff_free_ecoff_debug_info): Declare. * libbfd.h: Regenerate. gas/ * config/obj-ecoff.c (ecoff_frob_file): Set alloc_syments. * config/obj-elf.c (elf_frob_file_after_relocs): Likewise.
2023-06-05MIPS: add MT ASE support for micromips32YunQiang Su5-7/+637
These instructions are descripted in MD00768. MIPS® Architecture for Programmers Volume IV-f: The MIPS® MT Module for the microMIPS32™ Architecture Document Number: MD00768 Revision 1.12 July 16, 2013 https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00768-1C-microMIPS32MT-AFP-01.12.pdf
2023-06-05Revert "MIPS: add MT ASE support for micromips32"YunQiang Su5-637/+7
This reverts commit 783a5f46b0583e9ed3a63acd3361009f46de5c17.
2023-06-05MIPS: add MT ASE support for micromips32YunQiang Su5-7/+637
These instructions are descripted in MD00768. MIPS® Architecture for Programmers Volume IV-f: The MIPS® MT Module for the microMIPS32™ Architecture Document Number: MD00768 Revision 1.12 July 16, 2013 https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00768-1C-microMIPS32MT-AFP-01.12.pdf
2023-06-05MIPS: fix -gnuabi64 testsuiteYunQiang Su35-461/+682
Test on: mips64-linux-gnuabi64 mips64el-linux-gnuabi64 mipsisa64-linux-gnuabi64 mipsisa64el-linux-gnuabi64 mipsisa64r2-linux-gnuabi64 mipsisa64r2el-linux-gnuabi64 mipsisa64r6-linux-gnuabi64 mipsisa64r6el-linux-gnuabi64
2023-06-05MIPS: fix r6 testsuitesYunQiang Su155-183/+354
Introduce run_dump_test_o32l run_dump_test_n32l run_dump_test_n64l Which use `-march=from-abi` for pre-R6 testcases, like micromips/mips16e etc. For cases doesn't use run_dump_test_*, we use -mips32r2 for micromips32 -mips1 for mips16-32 -march=from-abi for testcases to o32/n32/n64 both/all. Replace `addi` with `addiu` for some cases for both r6 and pre-R6. Introduce some new testcases for r6 with FPXX/FP64. Introduce new testcase: comdat-reloc-r6. Skip `default` in mips_arch_list_matching if triple is mipsisa*, due to: 1)it will cannot match mipsr6@*.d: since mips32rN/mips64rN will always be used, it won't be a problem. 2)some test think -march=mips64rN will alway true for mipsisa64rN, which is not true now. This patch fix testsuite for all r6-default gnu triples: mipsisa32r6-linux-gnu mipsisa32r6el-linux-gnu mips-img-linux-gnu mipsel-img-linux-gnu mipsisa64r6-linux-gnu mipsisa64r6el-linux-gnu
2023-06-05MIPS: default r6 if vendor is imgYunQiang Su2-2/+14
This behavior is used by downstream toolchain since 2014. We also set the default ABI for mips*-img-elf to O32. The previous value is NO_ABI, which is not good default ABI. We don't support mips64*-img* due to GCC doesn't support it, and We believe that the multilib should be used for this case.
2023-06-05MIPS: gas: alter 64 or 32 for mipsisa triples if march is implicitYunQiang Su2-122/+162
When configure with triples mipsisa[32,64]rN[el,], the march value is pinned to a fix value if not given explicitly. for example 1) mipsisa32r6-linux-gnu -n32 xx.s will complains that: -march=mips32r6 is not compatible with the selected ABI 2) mipsisa64r2el-linux-gnu -o32 generates objects with 64bit CPU: ELF 32-bit LSB relocatable, MIPS, MIPS64 rel2 version 1 (SYSV) They are not good default behaviors: Let's alter the CPU info Since we are using these triples as a regular linux distributions, let's alter march according to ABI.
2023-06-01RISC-V: PR30449, Add lga assembler macro support.Jim Wilson3-2/+59
Originally discussion, https://github.com/riscv/riscv-isa-manual/pull/539 Added new load address pseudo instruction which is always expanded to GOT access, no matter the .option rvc is set or not. gas/ PR 30449 * config/tc-riscv.c (macro): Add M_LGA support. * testsuite/gas/riscv/la-variants.d: New. * testsuite/gas/riscv/la-variants.s: New. include/ PR 30449 * opcode/riscv.h (M_LGA): New. opcodes/ PR 30449 * riscv-opc.c (riscv_opcodes): Add lga support.
2023-05-30LoongArch: gas: Add support for linker relaxation.mengqinggang30-229/+725
Add gas -mrelax and -mno-relax option. Add R_LARCH_RELAX reloc for instrction if it can be relaxed. ADD R_LARCH_ALIGN reloc for align pseudo instruction because relax. Add ADD/SUB reloc pair for debug and exception data to calculate symbol substraction because relax. gas/ChangeLog: * config/tc-loongarch.c: (struct loongarch_cl_insn): New macro_id member. (enum options): New OPTION_RELAX and OPTION_NO_RELAX. (struct option): New mrelax and mno-relax. (md_parse_option): Likewise. (get_internal_label): (loongarch_args_parser_can_match_arg_helper): Generate relax reloc. (move_insn): Set fx_frag and fx_where if exist. (append_fixp_and_insn): Call frag_wane and frag_new for linker relax relocs. (loongarch_assemble_INSNs): New loongarch_cl_insn pointer parameter. (md_assemble): Fix function call. (fix_reloc_insn): Likewise. (md_apply_fix): Generate ADD/SUB reloc pair for debug and exception data. (loongarch_fix_adjustable): Delete. (md_convert_frag): Generate new fix. (loongarch_pre_output_hook): New function. (loongarch_make_nops): Likewise. (loongarch_frag_align_code): Likewise. (loongarch_insert_uleb128_fixes): Likewise. (loongarch_md_finish): Likewise. * config/tc-loongarch.h (md_allow_local_subtract): New macro define. (loongarch_frag_align_code): New declare. (md_do_align): Likewise. (loongarch_fix_adjustable): Delete. (tc_fix_adjustable): New macro define. (TC_FORCE_RELOCATION_SUB_SAME): Likewise. (TC_LINKRELAX_FIXUP): Likewise. (TC_FORCE_RELOCATION_LOCAL): Likewise. (DWARF2_USE_FIXED_ADVANCE_PC): Likewise. (MD_APPLY_SYM_VALUE): Likewise. (tc_symbol_new_hook): New extern. (NOP_OPCODE): Delete. (loongarch_pre_output_hook): New macro define. (md_pre_output_hook): Likewise. (md_finish): Likewise. (loongarch_md_finish): New extern. * testsuite/gas/all/align.d: Mark as unsupported on LoongArch. * testsuite/gas/all/gas.exp: Xfail loongarch*-*. * testsuite/gas/all/relax.d: Likewise. * testsuite/gas/elf/dwarf-5-irp.d: Likewise. * testsuite/gas/elf/dwarf-5-loc0.d: Likewise. * testsuite/gas/elf/dwarf-5-macro-include.d: Likewise. * testsuite/gas/elf/dwarf-5-macro.d: Likewise. * testsuite/gas/elf/dwarf2-11.d: Likewise. * testsuite/gas/elf/dwarf2-15.d: Likewise. * testsuite/gas/elf/dwarf2-16.d: Likewise. * testsuite/gas/elf/dwarf2-17.d: Likewise. * testsuite/gas/elf/dwarf2-18.d: Likewise. * testsuite/gas/elf/dwarf2-19.d: Likewise. * testsuite/gas/elf/dwarf2-5.d: Likewise. * testsuite/gas/elf/ehopt0.d: Likewise. * testsuite/gas/elf/elf.exp: Likewise. * testsuite/gas/elf/section11.d: Likewise. * testsuite/gas/lns/lns.exp: Likewise. * testsuite/gas/loongarch/jmp_op.d: Regenerated. * testsuite/gas/loongarch/li.d: Likewise. * testsuite/gas/loongarch/macro_op.d: Likewise. * testsuite/gas/loongarch/macro_op_32.d: Likewise. * testsuite/gas/loongarch/macro_op_large_abs.d: Likewise. * testsuite/gas/loongarch/macro_op_large_pc.d: Likewise. * testsuite/gas/loongarch/relax_align.d: New test. * testsuite/gas/loongarch/relax_align.s: New test. * testsuite/gas/loongarch/uleb128.d: New test. * testsuite/gas/loongarch/uleb128.s: New test.
2023-05-30Don't define COFF_MAGICAlan Modra4-5/+0
This macro was unused apart from aout/encap.h, which has been deleted. * config/tc-arm.h (COFF_MAGIC): Don't define. * config/tc-sh.h (COFF_MAGIC): Don't define. * config/tc-z80.h (COFF_MAGIC): Don't define. * config/tc-z8k.h (COFF_MAGIC): Don't define.
2023-05-26iamcu: suppress tests which can't possibly workJan Beulich1-18/+23
With neither --32 nor --64 passed to gas, advanced features like AVX aren't available without explicitly enabling them.
2023-05-26x86-64: improve gas diagnostic when no 32-bit target is configuredJan Beulich1-1/+15
Make this similar to --64 and --x32: Check whether a suitable target exists.
2023-05-26x86-64: conditionalize tests using --32Jan Beulich1-2/+12
Using this option doesn't really work when no support for any 32-bit target was configured in (as is the case for at least cloudabi and rdos).
2023-05-26x86: split gas testsuite .exp fileJan Beulich2-615/+647
The set of 32-bit-only and 64-bit-only tests has grown quite large. In particular when one's after only the results for the 64-bit set, having them live in a separate .exp file is easier / faster.
2023-05-26x86: figure braces aren't really part of mnemonicsJan Beulich1-8/+24
Instead they're separators for pseudo-prefixes. Don't insert them in mnemonic_chars[], handling them explicitly in parse_insn() instead. Note that this eliminates the need for another separator after a pseudo- prefix. While maybe not overly interesting for a following real mnemonic, I view this as quite desirable between multiple successive pseudo-prefixes (bringing things in line with the other use of figure braces in AVX512's zeroing-masking). Drop the unused is_mnemonic_char() at this occasion.
2023-05-26x86: de-duplicate operand_special_chars[] wrt extra_symbol_chars[]Jan Beulich1-10/+7
Having to add characters to both arrays can easily lead to oversights. Consuming extra_symbol_chars[] when populating operand_chars[] also allows to drop two special cases in md_begin(). Constify operand_special_chars[] at this occasion.
2023-05-23x86/Intel: address quoted-symbol related FIXMEsJan Beulich1-8/+4
If in a "word ptr <address>" or alike construct the "ptr" part is double-quoted, it shouldn't be recognized as the specific keyword we're looking for (just like we don't recognize double-quoted operator or register names anymore). Be careful though to tell closing from opening double-quotes, as a quoted symbol may follow right afterwards.
2023-05-23x86: don't recognize quoted symbol names as registers or operatorsJan Beulich7-0/+53
The concept of quoted symbols names was introduced pretty late. Utilize it to allow access to symbols with names matching that of a register (or, in Intel syntax, also an identifier-like operator). This is primarily to aid gcc when generating Intel syntax output; see their bug target/53929.
2023-05-23Support Intel FRED LKGSZhang, Jun12-0/+147
gas/ChangeLog: * NEWS: Support Intel FRED LKGS. * config/tc-i386.c: Add fred lkgs * doc/c-i386.texi: Document .fred, .lkgs. * testsuite/gas/i386/i386.exp: Add FRED LKGS tests * testsuite/gas/i386/x86-64-fred-intel.d: Ditto. * testsuite/gas/i386/x86-64-fred.d: Ditto. * testsuite/gas/i386/x86-64-fred.s: Ditto. * testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto. * testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto. * testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto. * testsuite/gas/i386/x86-64-lkgs.d: Ditto. * testsuite/gas/i386/x86-64-lkgs.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New entry for fred, lkgs. * i386-gen.c: Add CPU_FRED CPU_LKGS. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h: Add fred, lkgs. * i386-opc.tbl: Add FRED, LKGS instructions. * i386-tbl.h: Regenerated.
2023-05-23Revert "Support Intel FRED LKGS"liuhongt12-147/+0
This reverts commit e5a497fe38e0ab19e16bdd9e4b4ed5e4d0056478.
2023-05-23Support Intel FRED LKGSZhang, Jun12-0/+147
gas/ChangeLog: * NEWS: Support Intel FRED LKGS. * config/tc-i386.c: Add fred lkgs * doc/c-i386.texi: Document .fred, .lkgs. * testsuite/gas/i386/i386.exp: Add FRED LKGS tests * testsuite/gas/i386/x86-64-fred-intel.d: Ditto. * testsuite/gas/i386/x86-64-fred.d: Ditto. * testsuite/gas/i386/x86-64-fred.s: Ditto. * testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto. * testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto. * testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto. * testsuite/gas/i386/x86-64-lkgs.d: Ditto. * testsuite/gas/i386/x86-64-lkgs.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New entry for fred, lkgs. * i386-gen.c: Add CPU_FRED CPU_LKGS. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h: Add fred, lkgs. * i386-opc.tbl: Add FRED, LKGS instructions. * i386-tbl.h: Regenerated.
2023-05-19RISC-V: Support subtraction of .uleb128.Kuan-Lin Chen1-2/+54
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/96d6e190e9fc04a8517f9ff7fb9aed3e9876cbd6 There are some known limitations for now, * Do not shrink the length of the uleb128 value, even if the value is reduced after relaxations. Also reports error if the length grows up. * The R_RISCV_SET_ULEB128 needs to be paired with and be placed before the R_RISCV_SUB_ULEB128. bfd/ * bfd-in2.h: Regenerated. * elfnn-riscv.c (perform_relocation): Perform R_RISCV_SUB_ULEB128 and R_RISCV_SET_ULEB128 relocations. Do not shrink the length of the uleb128 value, and report error if the length grows up. Called the generic functions, _bfd_read_unsigned_leb128 and _bfd_write_unsigned_leb128, to encode the uleb128 into the section contents. (riscv_elf_relocate_section): Make sure that the R_RISCV_SET_ULEB128 must be paired with and be placed before the R_RISCV_SUB_ULEB128. * elfxx-riscv.c (howto_table): Added R_RISCV_SUB_ULEB128 and R_RISCV_SET_ULEB128. (riscv_reloc_map): Likewise. (riscv_elf_ignore_reloc): New function. * libbfd.h: Regenerated. * reloc.c (BFD_RELOC_RISCV_SET_ULEB128, BFD_RELOC_RISCV_SUB_ULEB128): New relocations to support .uleb128 subtraction. gas/ * config/tc-riscv.c (md_apply_fix): Added BFD_RELOC_RISCV_SET_ULEB128 and BFD_RELOC_RISCV_SUB_ULEB128. (s_riscv_leb128): Updated to allow uleb128 subtraction. (riscv_insert_uleb128_fixes): New function, scan uleb128 subtraction expressions and insert fixups for them. (riscv_md_finish): Called riscv_insert_uleb128_fixes for all sections. include/ * elf/riscv.h ((R_RISCV_SET_ULEB128, (R_RISCV_SUB_ULEB128): Defined. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * testsuite/ld-riscv-elf/uleb128*: New testcase for uleb128 subtraction. binutils/ * testsuite/binutils-all/nm.exp: Updated since RISCV supports .uleb128.
2023-05-19x86: permit all relational operators in insn operandsJan Beulich4-1/+29
Oddly enough == and != were not permitted, because of '=' not having been listed in operand_special_chars[].
2023-05-19x86: further adjust extend-to-32bit-address conditionsJan Beulich8-6/+192
While a442cac5084e ("ix86: wrap constants") helped address a number of inconsistencies between BFD64 and !BFD64 builds, it has also resulted in certain bogus uses of constants to no longer be warned about. Leverage the md_optimize_expr() hook to adjust when to actually truncate expressions to 32 bits - any involvement of binary expressions (which would be evaluated in 32 bits only when !BFD64) signals the need for doing so. Plain constants (or ones merely subject to unary operators) should remain un-truncated - they would be handled as bignums when !BFD64, and hence are okay to permit. To compensate - slightly extend optimize_imm() (to be honest I never understood why the code being added - or something similar - wasn't there in the first place), - adjust expectations of the disp-imm-32 testcase (there are now warnings, as there should be for any code which won't build [warning- free] when !BFD64, and Disp8/Imm8 are no longer used in the warned about cases).
2023-05-19gas: invoke md_optimize_expr() also for unary expressionsJan Beulich4-22/+40
Give backends a chance to see these, just as they can see binary ones. Most of those which use this hook already cope with NULL being passed for the left operand (typically because of checking the operator first). Adjust the two which don't. Take the opportunity and also document the hook.
2023-05-19gas: maintain O_constant signedness in more casesJan Beulich9-12/+73
Unary '~' doesn't really produce an unsigned result. Neither does subtraction (unless taking operand values into consideration). And an abstract operator applied to two operands which aren't both unsigned can't be assumed to yield an unsigned result; exceptions are - shifts, where only signedness of the left hand operand matters, - comparisons, which - unlike unary '!' - produce signed results (they deliver 0 or ~0, as opposed to '!', which yields 0 or 1), - logical operators (yielding 0 or 1 and hence treated like unary '!'). While doing this (specifically while extending the all/quad testcase), update .quad and .8byte documentation: With 64-bit architectures now being common, it is highly inappropriate to state that these directives unconditionally require bignums.
2023-05-19x86: tighten extend-to-32bit-address conditionsJan Beulich1-2/+2
In a442cac5084e ("ix86: wrap constants") I made the truncation condition too relaxed: Any indication of a mode that's possible with BFD64 only should avoid the truncation. Therefore, like in the other two cases of calls to extend_to_32bit_address(), also check whether we're generating a 64-bit object.
2023-05-18PR11601, Solaris assembler compatibility doesn't workAlan Modra2-1/+5
Well, it doesn't work on x86 or ppc, which both have # starting comments anywhere on a line. I think it is therefore only useful on sparc. PR 11601 * config/obj-elf.c (obj_elf_section_word): Only compile for sparc. (obj_elf_section): Only support solaris .section directive on sparc. * doc/as.texi (Section): Mention that solaris .section directive is only supported for sparc.
2023-05-17gcc-4.5 build fixesAlan Modra1-1/+1
Trying to build binutils with an older gcc currently fails. Working around these gcc bugs is not onerous so let's fix them. bfd/ * elf32-csky.c (csky_elf_size_dynamic_sections): Don't type-pun pointer. * elf32-rl78.c (rl78_compute_complex_reloc): Rename "stat" variable to "status". gas/ * compress-debug.c (compress_finish): Supply all fields in ZSTD_inBuffer initialisation. include/ * xtensa-dynconfig.h (xtensa_isa_internal): Delete unnecessary forward declaration. opcodes/ * loongarch-opc.c: Supply all fields of zero struct initialisation in various opcode tables.
2023-05-13PR28955 mips gas segfaultAlan Modra1-2/+4
Testing for NULL in pic_need_relax fixes the other call to this function in md_estimate_size_before_relax. PR 28955 * config/tc-mips.c (mips_frob_file): Move NULL sym test to.. (pic_need_relax): ..here.
2023-05-12x86: slightly simplify i386_parse_name()Jan Beulich1-7/+2
With the switch to parse_real_register() (commit 4faaa10f3fab) "bad_reg" cannot come back anymore. Drop the respective check.
2023-05-12gas: equates of registersJan Beulich22-4/+64
There are two problems: symbol_equated_p() doesn't recognize equates of registers, and S_CAN_BE_REDEFINED() goes by section rather than by expression type. Both together undermine .eqv and .equiv clearly meaning to guard the involved symbols against re-definition (both ways). To compensate pseudo_set() now using O_symbol and S_CAN_BE_REDEFINED() now checking for O_register, - for targets creating register symbols through symbol_{new,create}() -> symbol_init() -> S_SET_VALUE() (alpha, arc, dlx, ia64, m68k, mips, mmix, tic4x, tic54x, plus anything using cgen or itbl-ops), have symbol_init() set their expressions to O_register, - x86'es parse_register() also can't go by section anymore when trying to "look through" equates; probably symbol_equated_p() should have been used there from the beginning, if only that had worked for equates of registers, - various targets need to "look through" equates when parsing insn operands (which also helps transitive forward equates); perhaps even more ought to, but many don't look to consider the possibility of register equates in the first place. This was uncovered by code reported in PR gas/30274 (duplicating PR gas/30272), except that there .eqv was used when really .equ was meant. Therefore that bug report is addressed here only in so far as gas wouldn't crash anymore; the code there still won't assemble successfully, just that now the issues there are properly diagnosed.
2023-05-06gas: documents .gnu_attribute Tag_GNU_MIPS_ABI_MSAYunQiang Su1-0/+11
It is added since 2016 by Add support for .MIPS.abiflags and .gnu.attributes sections b52717c0e104eb603e8189c3c0d3658ef5d903f5 But never documented.
2023-05-04RISC-V: tighten post-relocation-operator separator expectationJan Beulich3-1/+8
As per the spec merely a blank isn't okay as a separator, the operand to the relocation function ought to be parenthesized. Enforcing this then also eliminates an inconsistency in that lui t0, %hi sym lui t0, %hi 0x1000 were accepted, but lui t0, %hi +sym lui t0, %hi -0x1000 were not.
2023-05-04gas: fix building tc-bpf.c on s390xIlya Leoshkevich1-2/+4
char is unsigned on s390x, so there are a lot of warnings like: gas/config/tc-bpf.c: In function 'get_token': gas/config/tc-bpf.c:900:14: error: comparison is always false due to limited range of data type [-Werror=type-limits] 900 | if (ch == EOF || len > MAX_TOKEN_SZ) | ^~ Change its type to int, like in the other similar code. There is also: gas/config/tc-bpf.c:735:30: error: 'bpf_endianness' may be used uninitialized in this function [-Werror=maybe-uninitialized] 735 | dst, be ? size[endianness - BPF_BE16] : size[endianness - BPF_LE16]); | ~~~~~~~~~~~^~~~~~~~~~ -Wmaybe-uninitialized doesn't seem to understand the FSM; just initialize bpf_endianness to silence it. Add an assertion to build_bpf_endianness() in order to catch potential bugs.
2023-05-04MIPS: revert "default r6 if vendor is img"YunQiang Su2-18/+0
In commit: 9171de358f230b64646bbb525a74e5f8e3dbe0dc, The default output is set to r6 if the vendor is img, It is ugly and should not be in upstream. Let's revert it.
2023-05-03Remove unused args from bfd_make_debug_symbolAlan Modra1-1/+1
The ptr and size args are unused. Make the function look the same as bfd_make_empty_symbol.
2023-05-03Generated docs and include filesAlan Modra1-0/+2
bfd/doc/chew.c extracts documentation from source code comments annotated with keywords, and generates much of bfd.h and libbfd.h from those same comments. The docs have suffered from people (me too) adding things like CODE_FRAGMENT to the source to put code into bfd.h without realising that CODE_FRAGMENT also puts @example around said code into the docs. So we have random senseless things in the docs. This patch fixes that problem (well, the senseless things from CODE_FRAGMENT), moves most of the code out of bfd-in.h, and improves a few chew.c features. libbfd.h now automatically gets ATTRIBUTE_HIDDEN prototypes, and indentation in bfd.h and libbfd.h is better.
2023-04-28x86/Intel: reduce ELF/PE conditional scope in x86_cons()Jan Beulich1-6/+4
All the Intel syntax related state adjustments apply independent of target or object format.
2023-04-28gas: move shift count checkJan Beulich1-14/+14
... out of mainline code, grouping together the two case labels. This then also make more obvious that the comment there applies to both forms of shifts.
2023-04-28x86: rework AMX multiplication insn disassemblyJan Beulich1-1/+1
Consistently do 64-bit first, ModR/M second, VEX.L third, VEX.W fourth, and prefix last, resulting in fewer table entries. Note that in the course of the re-work wrong M_0 suffixes are also corrected to be M_1 (partly infixes now). Since it ended up confusing while testing the change, also adjust the test name in x86-64-amx-bad.d (to be distinct from x86-64-amx.d's).