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AgeCommit message (Expand)AuthorFilesLines
2018-01-03Update year range in copyright notice of binutils filesAlan Modra192-192/+192
2017-12-28RISC-V: Add missing privileged spec registers.Jim Wilson2-0/+518
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson12-0/+92
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-432/+432
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina3-0/+24
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-45/+45
2017-12-17x86: Check pseudo prefix without instructionH.J. Lu3-0/+17
2017-12-14Update the address of the FSF in the copyright notice of files which were usi...Nick Clifton1-3/+3
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson2-0/+17
2017-12-13This patch enables disassembler_needs_relocs for PRU. It is needed to print c...Dimitar Dimitrov2-0/+15
2017-12-04Run powerpc vle gas tests for all powerpc ELF targetsAlan Modra18-39/+37
2017-11-30x86/Intel: issue diagnostics for redundant segment override prefixesJan Beulich4-4/+26
2017-11-30Revert "x86: Update segment register check in Intel syntax"Jan Beulich5-43/+11
2017-11-29Fix riscv malloc error on small alignment after norvc.Jim Wilson3-9/+6
2017-11-29[GAS][AARCH64]Fix a typo for IP1 register alias.Renlin Li2-1/+5
2017-11-27Compress loads/stores with implicit 0 offset.Jim Wilson5-0/+54
2017-11-27gas: xtensa: implement trampoline coalescingMax Filippov5-16/+38
2017-11-27gas: xtensa: reuse trampoline placement codeMax Filippov1-3/+3
2017-11-27gas: xtensa: rewrite xg_relax_trampolineMax Filippov2-16/+15
2017-11-26gas: Update x86 sse-noavx testsH.J. Lu5-0/+7
2017-11-24x86: reject further invalid AVX-512 masking constructsJan Beulich4-0/+42
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich9-13/+16
2017-11-23Fix vax/ns32k/mmix gas testsuite regression.Jim Wilson1-1/+1
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist17-96/+192
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich3-0/+20
2017-11-23x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base regJan Beulich2-0/+10
2017-11-23x86: correct UDnJan Beulich8-11/+12
2017-11-23x86/Intel: don't report multiple errors for a single insn operandJan Beulich2-6/+0
2017-11-22Riscv ld-elf/stab failure and fake label cleanup.Jim Wilson1-0/+3
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss1-0/+11
2017-11-21x86: Add tests for -n option of x86 assemblerH.J. Lu4-0/+50
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss22-155/+168
2017-11-21mingw gas testsuite fixAlan Modra1-0/+1
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina2-2/+2
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina12-0/+12808
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich2-4/+76
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich3-0/+3
2017-11-16i386: Replace .code64/.code32 with .byteH.J. Lu1-13/+8
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a int...Tamar Christina4-4/+4
2017-11-15Add support to readelf and objdump for following links to separate debug info...Nick Clifton12-12/+12
2017-11-15x86: use correct register namesJan Beulich2-0/+21
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich3-0/+23
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich8-0/+73
2017-11-14First part of fix for riscv gas lns-common-1 failure.Jim Wilson1-0/+1
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich3-1194/+1194
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich6-0/+216
2017-11-14x86: string insns don't allow displacementsJan Beulich5-33/+43
2017-11-13gas/ia64: fix testsuite failuresJan Beulich3-11/+12
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich2-0/+11
2017-11-13x86/Intel: don't mistake riz/eiz as base registerJan Beulich2-0/+9
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