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2015-11-19Recent powerpc testcase failsAlan Modra1-0/+5
2015-11-12Fix dates in Changelog for previous commit.Ramana Radhakrishnan1-1/+1
2015-11-12Fix PR gas/19217Ramana Radhakrishnan1-0/+5
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner1-0/+16
2015-11-09gas: Fix left shift of negative value.Dominik Vogt1-0/+5
2015-11-02Disassemble RX NOP instructions as such.Nick Clifton1-0/+6
2015-11-02Fix disassembly of RX zero-offset register indirect instructions.Nick Clifton1-0/+5
2015-10-28Add tests for 16-bit versions of ARM teq, tst, cmp and cmn instructions.Nick Clifton1-0/+5
2015-10-27Fix RL78 disassembly of DE+offset addressing to always show the offset, even ...Vinay Kumar1-0/+7
2015-10-27Display system registers by their names when disassembling RL78 instructions.Vinay Kumar1-0/+7
2015-10-27Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, ev...Vinay Kumar1-0/+8
2015-10-22Add support for MSP430 silicon errata to the assembler.Nick Clifton1-0/+11
2015-10-22Add R_X86_64_[REX_]GOTPCRELX support to gas and ldH.J. Lu1-0/+10
2015-10-22Add R_386_GOT32X support to gas and ldH.J. Lu1-0/+9
2015-10-22Fix tests for PR 18500, revisitedAlan Modra1-0/+8
2015-10-21Fix tests for PR 18500 so that they will pass for big-endian ARM toolchains.Nick Clifton1-0/+8
2015-10-14Add missing changelog entriesAndreas Krebbel1-0/+7
2015-10-12avr: Fix bugs in org/align tracking.Andrew Burgess1-0/+5
2015-10-07New ARC implementation.Nick Clifton1-0/+77
2015-10-02[GAS][AARCH64]Add TLSDESC large memory model support.Renlin Li1-0/+9
2015-10-02[Binutils][AARCH64]Add TLS IE large memory support.Renlin Li1-0/+7
2015-10-02[GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC support.Renlin Li1-0/+5
2015-10-02[GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G1 support.Renlin Li1-0/+5
2015-10-02[GAS][AARCH64]Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC Support.Renlin Li1-0/+5
2015-10-02[GAS][AARCH64]Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 Support.Renlin Li1-0/+5
2015-09-30Revise new e500 invalid opcode testAlan Modra1-0/+6
2015-09-29Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine ...Dominik Vogt1-0/+16
2015-09-28Patches for illegal ppc 500 instructionsTom Rix1-0/+6
2015-08-25Update MIPS tests for test failures on some configurations.Simon Dardis1-0/+6
2015-08-25Support for the sparc %pmcdper privileged register.Jose E. Marchesi1-0/+9
2015-08-24Fix the partial disassembly of a broken three byte instruction at the end of ...Jan Stancek1-0/+6
2015-08-21Allow symbol and label names to be enclosed in double quotes.Nick Clifton1-0/+9
2015-08-21PR binutils/18257: Properly decode x86/Intel mask instructions.Alexander Fomin1-0/+8
2015-08-19[AArch64][5/6] GAS support TLSLD load/store relocation typesJiong Wang1-0/+19
2015-08-19[AArch64][3/6] GAS support TLSLD move/add relocation typesJiong Wang1-0/+23
2015-08-19[AArch64][1/6] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NCJiong Wang1-0/+7
2015-08-13Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.Andre Vieira1-0/+7
2015-08-12xtensa: add --auto-litpools optionMax Filippov1-0/+8
2015-08-12[MIPS] Map 'move' to 'or'.Simon Dardis1-0/+39
2015-08-11[AArch64][7/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12Jiong Wang1-0/+7
2015-08-11[AArch64][5/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NCJiong Wang1-0/+7
2015-08-11[AArch64][2/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21Jiong Wang1-0/+7
2015-08-10Add SIGRIE instruction for MIPS R6Robert Suchanek1-0/+7
2015-07-30Properly disassemble movnti in Intel modeH.J. Lu1-0/+7
2015-07-24Fix the evaluation of RL78 complex relocs, by making immediate values be comp...Nick Clifton1-0/+7
2015-07-24Remove leading/trailing white spaces in ChangeLogH.J. Lu1-1/+1
2015-07-22Fix memory operand size for vcvtt?ps2u?qq instructionsH.J. Lu1-0/+19
2015-07-21[ARM] Support correctly spelled ARMv6KZ architecture namesMatthew Wahab1-0/+5
2015-07-16[AArch64][2/3] GAS support BFD_RELOC_AARCH64_TLSLD_ADR_PREL21Jiong Wang1-0/+7
2015-07-16[ARM] Make human parsing of "processor does not support instruction in mode" ...James Greenhalgh1-0/+9