aboutsummaryrefslogtreecommitdiff
path: root/gas/doc
AgeCommit message (Collapse)AuthorFilesLines
2012-05-29gas/Roland McGrath1-3/+6
* read.c [HANDLE_BUNDLE] (bundle_lock_depth): New variable. (read_a_source_file) [HANDLE_BUNDLE]: Reset it. [HANDLE_BUNDLE] (s_bundle_lock, s_bundle_unlock): Allow nested pairs. gas/testsuite/ * gas/i386/bundle-bad.s: Remove nested .bundle_lock case. * gas/i386/bundle-bad.l: Remove expected error line. * gas/i386/bundle-lock.s: Add nested .bundle_lock case. * gas/i386/bundle-lock.d: Update expectations.
2012-05-28 * read.c (read_symbol_name): New function. Reads a symbol names.Nick Clifton1-4/+9
Allows escape codes in names. (s_comm_internal): Use read_symbol_name. (s_globl, s_lsym, s_set, s_weakref): Likewise. * doc/as.texinfo: Document support for multibyte characters in symbol names. * gas/elf/syms.s: New test - checks the generation of multibyte symbol names. * gas/elf/syms.d: New file - expected readelf output. * gas/elf/elf.exp: Add syms. * readelf.c (print_symbol): Display multibyte characters in symbol names. (process_section_headers): Use print_symbol. * ld-ifunc/ifunc-13a-i386.s: Fix use of .global directive. * ld-ifunc/ifunc-15a-i385.s: Likewise.
2012-05-17 PR 14072Nick Clifton1-6/+7
* configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * sysdep.h: Generate an error if included before config.h. * alpha-opc.c: Include sysdep.h before any other header file. * alpha-dis.c: Likewise. * avr-dis.c: Likewise. * cgen-opc.c: Likewise. * cr16-dis.c: Likewise. * cris-dis.c: Likewise. * crx-dis.c: Likewise. * d10v-dis.c: Likewise. * d10v-opc.c: Likewise. * d30v-dis.c: Likewise. * d30v-opc.c: Likewise. * h8500-dis.c: Likewise. * i370-dis.c: Likewise. * i370-opc.c: Likewise. * m10200-dis.c: Likewise. * m10300-dis.c: Likewise. * micromips-opc.c: Likewise. * mips-opc.c: Likewise. * mips61-opc.c: Likewise. * moxie-dis.c: Likewise. * or32-opc.c: Likewise. * pj-dis.c: Likewise. * ppc-dis.c: Likewise. * ppc-opc.c: Likewise. * s390-dis.c: Likewise. * sh-dis.c: Likewise. * sh64-dis.c: Likewise. * sparc-dis.c: Likewise. * sparc-opc.c: Likewise. * spu-dis.c: Likewise. * tic30-dis.c: Likewise. * tic54x-dis.c: Likewise. * tic80-dis.c: Likewise. * tic80-opc.c: Likewise. * tilegx-dis.c: Likewise. * tilepro-dis.c: Likewise. * v850-dis.c: Likewise. * v850-opc.c: Likewise. * vax-dis.c: Likewise. * w65-dis.c: Likewise. * xgate-dis.c: Likewise. * xtensa-dis.c: Likewise. * rl78-decode.opc: Likewise. * rl78-decode.c: Regenerate. * rx-decode.opc: Likewise. * rx-decode.c: Regenerate. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * sysdep.h: Generate an error if included before config.h. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in.h: Generate an error if included before config.h. * sysdep.h: Likewise. * bfd-in2.h: Regenerate. * compress.c: Remove #include "config.h". * plugin.c: Likewise. * elf32-m68hc1x.c: Include sysdep.h before alloca-conf.h. * elf64-hppa.c: Likewise. * som.c: Likewise. * xsymc.c: Likewise. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * aclocal.m4: Regenerate. * Makefile.am: Use wrappers around C files generated by flex. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * itbl-lex-wrapper.c: New file. * config/bfin-lex-wrapper.c: New file. * cgen.c: Include as.h before setjmp.h. * config/tc-dlx.c: Include as.h before any other header. * config/tc-h8300.c: Likewise. * config/tc-lm32.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-or32.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-xtensa.c: Likewise. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * unwind-ia64.h: Include config.h.
2012-05-15 * config/tc-m68hc11.c: Add S12X and XGATE co-processor support.Nick Clifton2-8/+28
Add option to offset S12 addresses into XGATE memory space. Tweak target flags to match other tools. (i.e. -m m68hc11). * doc/as.texinfo: Mention new options. * doc/c-m68hc11.texi: Document new options. * NEWS: Mention new support. * archures.c: Add bfd_arch_m9s12x and bfd_arch_m9s12xg. * config.bfd: Likewise. * cpu-m9s12x.c: New. * cpu-m9s12xg.c: New. * elf32-m68hc12.c: Add S12X and XGATE co-processor support. Add option to offset S12 addresses into XGATE memory space. Fix carry bug in IMM16 (IMM8 low/high) relocate. * Makefile.am (ALL_MACHINES): Add cpu-m9s12x and cpu-m9s12xg. (ALL_MACHINES_CFILES): Likewise. * reloc.c: Add S12X relocs. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * gas/m68hc11/insns9s12x.s: New * gas/m68hc11/insns9s12x.d: New * gas/m68hc11/hexprefix.s: New * gas/m68hc11/hexprefix.d: New * gas/m68hc11/9s12x-exg-sex-tfr.s: New * gas/m68hc11/9s12x-exg-sex-tfr.d: New * gas/m68hc11/insns9s12xg.s: New * gas/m68hc11/insns9s12xg.d: New * gas/m68hc11/9s12x-mov.s: New * gas/m68hc11/9s12x-mov.d: New * gas/m68hc11/m68hc11.exp: Updated * gas/m68hc11/*.d: Brought in line with changed objdump output. * gas/all/gas.exp: XFAIL all hc11/12 targets for redef2,3. * gas/elf/elf.exp: XFAIL all hc11/12 targets for redef. * gas/elf/dwarf2-1.d: Skip for hc11/12 targets. * gas/elf/dwarf2-2.d: Likewise. * ld-m68hc11/xgate-link.s: New. * ld-m68hc11/xgate-link.d: New. * ld-m68hc11/xgate-offset.s: New. * ld-m68hc11/xgate-offset.d: New. * ld-m68hc11/xgate1.s: New. * ld-m68hc11/xgate1.d: New. * ld-m68hc11/xgate2.s: New. * ld-m68hc11/m68hc11.exp: Updated. * ld-m68hc11/*.d: Brought in line with changed objdump output. * ld-gc/gc.exp: Update CFLAGS for m68hc11. * ld-plugin/plugin.exp: Likewise. * ld-srec/srec.exp: XFAIL for m68hc11 and m68hc12. * configure.in: Add S12X and XGATE co-processor support to m68hc11 target. * disassemble.c: Likewise. * configure: Regenerate. * m68hc11-dis.c: Make objdump output more consistent, use hex instead of decimal and use 0x prefix for hex. * m68hc11-opc.c: Add S12X and XGATE opcodes. * dis-asm.h (print_insn_m9s12x): Prototype. (print_insn_m9s12xg): Prototype. * m68hc11.h (R_M68HC12_16B, R_M68HC12_PCREL_9, R_M68HC12_PCREL_10) R_M68HC12_HI8XG, R_M68HC12_LO8XG): New relocations. (E_M68HC11_XGATE_RAMOFFSET): Define. * m68hc11.h: Add XGate definitions. (struct m68hc11_opcode): Add xg_mask field.
2012-05-15* config/tc-rx.c (rx_fetchalign): Declare.DJ Delorie1-0/+10
(md_pseudo_table): Add .fetchalign. (RX_NBASE_FETCHALIGN): New. (fetchalign_bytes): New. (rx_fetchalign): New. (rx_frag_init): If a "magic" value is found, also init the machine-specific data. (md_assemble): Note following opcode size if called for. (rx_next_opcode): New. (rx_relax_frag): Support .fetchalign. (md_convert_frag): Likewise. * doc/c-rx.texi (RX-Directives): Add .fetchalign.
2012-05-03Add support for Motorola XGATE embedded CPUNick Clifton5-0/+220
2012-04-27Document sparc's %l34 and %h34David S. Miller1-1/+16
gas/ * doc/c-sparc.text: Document %l34 and %h34.
2012-04-06 * doc/c-mips.texi (MIPS Opts): Correct -no-mfix-24k toMaciej W. Rozycki1-1/+1
-mno-fix-24k.
2012-03-292012-03-29 Terry Guo <terry.guo@arm.com>Matthew Gretton-Dann1-0/+1
* gas/config/tc-arm.c (arm_cpus): Add cortex-m0plus. * gas/doc/c-arm.texi (ARM Options): Document -mcpu=cortex-m0plus.
2012-03-24 gas/Maxim Kuvyrkov1-1/+2
* config/tc-mips.c (mips_cpu_info_table): Add entry for Broadcom XLP. * doc/c-mips.texi: Mention XLP. opcodes/ * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
2012-03-21gas/Thomas Schwinge2-9/+8
[SH] Support the .uaquad and .8byte directives also for non-sh64 configurations. * config/tc-sh.c (sh_cons_fix_new, md_apply_fix) [!HAVE_SH64]: Handle BFD_RELOC_64. * doc/c-sh64.texi (SH64 Machine Directives): Move .uaquad description... * doc/c-sh.texi (SH Machine Directives): ... here.
2012-03-15gas/Thomas Schwinge1-1/+1
* doc/as.texinfo (Bundle directives): Fix typo.
2012-03-14Replace @defn with @dfnH.J. Lu1-5/+5
2012-03-14 Ryan Mansfield <rmansfield@qnx.com> * doc/as.texinfo (Bundle directives): Replace @defn with @dfn.
2012-03-13gas/Roland McGrath1-1/+55
2012-03-12 Roland McGrath <mcgrathr@google.com> * config/tc-arm.c (arm_frag_max_var): New function. * config/tc-arm.h: Declare it. (md_frag_max_var): New macro. * config/tc-i386.c (i386_frag_max_var): New function. * config/tc-i386.h: Declare it. (md_frag_max_var): New macro. * doc/as.texinfo (Bundle directives): New node. (Pseudo Ops): Add it to the menu. * NEWS: Mention new feature. * read.c [md_frag_max_var] (HANDLE_BUNDLE): New macro. [HANDLE_BUNDLE] (bundle_align_p2): New variable. [HANDLE_BUNDLE] (bundle_lock_frchain, bundle_lock_frag): New variables. [HANDLE_BUNDLE] (start_bundle, pending_bundle_size, finish_bundle): New functions. (assemble_one): New function if [HANDLE_BUNDLE], #define directly to md_assembly if not. (read_a_source_file): Call assemble_one in place of md_assemble. (read_a_source_file) [HANDLE_BUNDLE]: Check for unterminated .bundle_lock at end of processing. [HANDLE_BUNDLE] (s_bundle_align_mode, s_bundle_lock, s_bundle_unlock): New functions. [HANDLE_BUNDLE] (potable): Add their entries. * read.h: Declare new functions. gas/testsuite/ 2012-03-12 Roland McGrath <mcgrathr@google.com> * gas/i386/bundle-bad.s: New file. * gas/i386/bundle-bad.d: New file. * gas/i386/bundle-bad.l: New file. * gas/i386/i386.exp: Run it. * gas/arm/bundle.s: New file. * gas/arm/bundle.d: New file. * gas/arm/bundle-lock.s: New file. * gas/arm/bundle-lock.d: New file. * gas/i386/bundle.s: New file. * gas/i386/bundle.d: New file. * gas/i386/x86-64-bundle.s: New file. * gas/i386/x86-64-bundle.d: New file. * gas/i386/bundle-lock.s: New file. * gas/i386/bundle-lock.d: New file. * gas/i386/i386.exp: Run them.
2012-03-09include/opcode/Alan Modra2-4/+10
* ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR. opcodes/ * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500". * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New. (PPCVEC2, PPCTMR, E6500): New short names. (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt, mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx, lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl, lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl, lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC optional operands on sync instruction for E6500 target. bfd/ * archures.c: Add bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add entryies for bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500. gas/ * config/tc-ppc.c (md_show_usage): Document -me5500 and -me6500. (ppc_handle_align): Add termination nop opcode for e500mc family. * doc/as.texinfo: Document options -me5500 and -me6500. * doc/c-ppc.texi: Likewise. gas/testsuite/ * gas/ppc/e500mc64_nop.s: New test case for e500mc family termination nops. * gas/ppc/e500mc64_nop.d: Likewise. * gas/ppc/e5500_nop.s: Likewise. * gas/ppc/e5500_nop.d: Likewise. * gas/ppc/e6500_nop.s: Likewise. * gas/ppc/e6500_nop.d: Likewise. * gas/ppc/e6500.s: New. * gas/ppc/e6500.d: Likewise. * gas/ppc/ppc.exp: Run e6500, e500mc64_nop, e5500_nop, and e6500_nop.
2012-02-25Improve TLS support on TILE-Gx/TILEPro:Walter Lee2-66/+70
- Add support for TLS LE references. - Support linker optimization of TLS references. - Delete relocations of GOT/tp relative offsets beyond 32-bits. This brings binutils in line with the support expected in gcc 4.7, for TILE-Gx/TILEPro. bfd/ * reloc.c: Add BFD_RELOC_TILEPRO_TLS_GD_CALL, BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD, BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD, BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD, BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD, BFD_RELOC_TILEPRO_TLS_IE_LOAD, BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE, BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE, BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO, BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO, BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI, BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI, BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA, BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA, BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE, BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE, BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE, BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE, BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE, BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE, BFD_RELOC_TILEGX_TLS_GD_CALL, BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD, BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD, BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD, BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD, BFD_RELOC_TILEGX_TLS_IE_LOAD, BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD, BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD, BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD, BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD. Delete BFD_RELOC_TILEGX_IMM16_X0_HW1_GOT, BFD_RELOC_TILEGX_IMM16_X1_HW1_GOT, BFD_RELOC_TILEGX_IMM16_X0_HW2_GOT, BFD_RELOC_TILEGX_IMM16_X1_HW2_GOT, BFD_RELOC_TILEGX_IMM16_X0_HW3_GOT, BFD_RELOC_TILEGX_IMM16_X1_HW3_GOT, BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_GOT, BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_GOT, BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_GD, BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_GD, BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_GD, BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_GD, BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_GD, BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_GD, BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_GD, BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_GD, BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_IE, BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_IE, BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_IE, BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_IE, BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_IE, BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_IE, BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_IE, BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_IE. * elf32-tilepro.c (tilepro_elf_howto_table): Update tilepro relocations. (tilepro_reloc_map): Ditto. (tilepro_info_to_howto_rela): Ditto. (reloc_to_create_func): Ditto. (tilepro_tls_translate_to_le): New. (tilepro_tls_translate_to_ie): New. (tilepro_elf_tls_transition): New. (tilepro_elf_check_relocs): Handle new tls relocations. (tilepro_elf_gc_sweep_hook): Ditto. (allocate_dynrelocs): Ditto. (tilepro_elf_relocate_section): Ditto. (tilepro_replace_insn): New. (insn_mask_X1): New. (insn_mask_X0_no_dest_no_srca): New (insn_mask_X1_no_dest_no_srca): New (insn_mask_Y0_no_dest_no_srca): New (insn_mask_Y1_no_dest_no_srca): New (srca_mask_X0): New (srca_mask_X1): New (insn_tls_le_move_X1): New (insn_tls_le_move_zero_X0X1): New (insn_tls_ie_lw_X1): New (insn_tls_ie_add_X0X1): New (insn_tls_ie_add_Y0Y1): New (insn_tls_gd_add_X0X1): New (insn_tls_gd_add_Y0Y1): New * elfxx-tilegx.c (tilegx_elf_howto_table): Update tilegx relocations. (tilegx_reloc_map): Ditto. (tilegx_info_to_howto_rela): Ditto. (reloc_to_create_func): Ditto. (tilegx_elf_link_hash_table): New field disable_le_transition. (tilegx_tls_translate_to_le): New. (tilegx_tls_translate_to_ie): New. (tilegx_elf_tls_transition): New. (tilegx_elf_check_relocs): Handle new tls relocations. (tilegx_elf_gc_sweep_hook): Ditto. (allocate_dynrelocs): Ditto. (tilegx_elf_relocate_section): Ditto. (tilegx_copy_bits): New. (tilegx_replace_insn): New. (insn_mask_X1): New. (insn_mask_X0_no_dest_no_srca): New. (insn_mask_X1_no_dest_no_srca): New. (insn_mask_Y0_no_dest_no_srca): New. (insn_mask_Y1_no_dest_no_srca): New. (insn_mask_X0_no_operand): New. (insn_mask_X1_no_operand): New. (insn_mask_Y0_no_operand): New. (insn_mask_Y1_no_operand): New. (insn_tls_ie_ld_X1): New. (insn_tls_ie_ld4s_X1): New. (insn_tls_ie_add_X0X1): New. (insn_tls_ie_add_Y0Y1): New. (insn_tls_ie_addx_X0X1): New. (insn_tls_ie_addx_Y0Y1): New. (insn_tls_gd_add_X0X1): New. (insn_tls_gd_add_Y0Y1): New. (insn_move_X0X1): New. (insn_move_Y0Y1): New. (insn_add_X0X1): New. (insn_add_Y0Y1): New. (insn_addx_X0X1): New. (insn_addx_Y0Y1): New. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * tc-tilepro.c (O_tls_le): Define operator. (O_tls_le_lo16): Ditto. (O_tls_le_hi16): Ditto. (O_tls_le_ha16): Ditto. (O_tls_gd_call): Ditto. (O_tls_gd_add): Ditto. (O_tls_ie_load): Ditto. (md_begin): Delete old operators; handle new operators. (emit_tilepro_instruction): Ditto. (md_apply_fix): Ditto. * tc-tilegx.c (O_hw1_got): Delete operator. (O_hw2_got): Ditto. (O_hw3_got): Ditto. (O_hw2_last_got): Ditto. (O_hw1_tls_gd): Ditto. (O_hw2_tls_gd): Ditto. (O_hw3_tls_gd): Ditto. (O_hw2_last_tls_gd): Ditto. (O_hw1_tls_ie): Ditto. (O_hw2_tls_ie): Ditto. (O_hw3_tls_ie): Ditto. (O_hw2_last_tls_ie): Ditto. (O_hw0_tls_le): Define operator. (O_hw0_last_tls_le): Ditto. (O_hw1_last_tls_le): Ditto. (O_tls_gd_call): Ditto. (O_tls_gd_add): Ditto. (O_tls_ie_load): Ditto. (O_tls_add): Ditto. (md_begin): Delete old operators; handle new operators. (emit_tilegx_instruction): Ditto. (md_apply_fix): Ditto. * doc/c-tilegx.texi: Delete old operators; document new operators. * doc/c-tilepro.texi: Ditto. include/elf/ * tilegx.h (R_TILEGX_IMM16_X0_HW1_GOT): Delete. (R_TILEGX_IMM16_X1_HW1_GOT): Ditto. (R_TILEGX_IMM16_X0_HW2_GOT): Ditto. (R_TILEGX_IMM16_X1_HW2_GOT): Ditto. (R_TILEGX_IMM16_X0_HW3_GOT): Ditto. (R_TILEGX_IMM16_X1_HW3_GOT): Ditto. (R_TILEGX_IMM16_X0_HW2_LAST_GOT): Ditto. (R_TILEGX_IMM16_X1_HW2_LAST_GOT): Ditto. (R_TILEGX_IMM16_X0_HW1_TLS_GD): Ditto. (R_TILEGX_IMM16_X1_HW1_TLS_GD): Ditto. (R_TILEGX_IMM16_X0_HW2_TLS_GD): Ditto. (R_TILEGX_IMM16_X1_HW2_TLS_GD): Ditto. (R_TILEGX_IMM16_X0_HW3_TLS_GD): Ditto. (R_TILEGX_IMM16_X1_HW3_TLS_GD): Ditto. (R_TILEGX_IMM16_X0_HW2_LAST_TLS_GD): Ditto. (R_TILEGX_IMM16_X1_HW2_LAST_TLS_GD): Ditto. (R_TILEGX_IMM16_X0_HW1_TLS_IE): Ditto. (R_TILEGX_IMM16_X1_HW1_TLS_IE): Ditto. (R_TILEGX_IMM16_X0_HW2_TLS_IE): Ditto. (R_TILEGX_IMM16_X1_HW2_TLS_IE): Ditto. (R_TILEGX_IMM16_X0_HW3_TLS_IE): Ditto. (R_TILEGX_IMM16_X1_HW3_TLS_IE): Ditto. (R_TILEGX_IMM16_X0_HW2_LAST_TLS_IE): Ditto. (R_TILEGX_IMM16_X1_HW2_LAST_TLS_IE): Ditto. (R_TILEGX_IMM16_X0_HW0_TLS_LE): New relocation. (R_TILEGX_IMM16_X1_HW0_TLS_LE): Ditto. (R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE): Ditto. (R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE): Ditto. (R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE): Ditto. (R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE): Ditto. (R_TILEGX_TLS_GD_CALL): Ditto. (R_TILEGX_IMM8_X0_TLS_GD_ADD): Ditto. (R_TILEGX_IMM8_X1_TLS_GD_ADD): Ditto. (R_TILEGX_IMM8_Y0_TLS_GD_ADD): Ditto. (R_TILEGX_IMM8_Y1_TLS_GD_ADD): Ditto. (R_TILEGX_TLS_IE_LOAD): Ditto. (R_TILEGX_IMM8_X0_TLS_ADD): Ditto. (R_TILEGX_IMM8_X1_TLS_ADD): Ditto. (R_TILEGX_IMM8_Y0_TLS_ADD): Ditto. (R_TILEGX_IMM8_Y1_TLS_ADD): Ditto. * tilepro.h (R_TILEPRO_TLS_GD_CALL): New relocation. (R_TILEPRO_IMM8_X0_TLS_GD_ADD): Ditto. (R_TILEPRO_IMM8_X1_TLS_GD_ADD): Ditto. (R_TILEPRO_IMM8_Y0_TLS_GD_ADD): Ditto. (R_TILEPRO_IMM8_Y1_TLS_GD_ADD): Ditto. (R_TILEPRO_TLS_IE_LOAD): Ditto. (R_TILEPRO_IMM16_X0_TLS_LE): Ditto. (R_TILEPRO_IMM16_X1_TLS_LE): Ditto. (R_TILEPRO_IMM16_X0_TLS_LE_LO): Ditto. (R_TILEPRO_IMM16_X1_TLS_LE_LO): Ditto. (R_TILEPRO_IMM16_X0_TLS_LE_HI): Ditto. (R_TILEPRO_IMM16_X1_TLS_LE_HI): Ditto. (R_TILEPRO_IMM16_X0_TLS_LE_HA): Ditto. (R_TILEPRO_IMM16_X1_TLS_LE_HA): Ditto. include/opcode/ * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS, TILEGX_OPC_LD_TLS. * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS, TILEPRO_OPC_LW_TLS_SN. opcodes/ * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS. * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and TILEPRO_OPC_LW_TLS_SN.
2012-02-25Add big-endian support for tilegx.Walter Lee2-1/+6
bfd/ * config.bfd (tilegx-*-*): rename little endian vector; add big endian vector. (tilegxbe-*-*): New case. * configure.in (bfd_elf32_tilegx_vec): Rename... (bfd_elf32_tilegx_le_vec): ... to this. (bfd_elf32_tilegx_be_vec): New vector. (bfd_elf64_tilegx_vec): Rename... (bfd_elf64_tilegx_le_vec): ... to this. (bfd_elf64_tilegx_be_vec): New vector. * configure: Regenerate. * elf32-tilegx.c (TARGET_LITTLE_SYM): Rename. (TARGET_LITTLE_NAME): Ditto. (TARGET_BIG_SYM): Define. (TARGET_BIG_NAME): Define. * elf64-tilegx.c (TARGET_LITTLE_SYM): Rename. (TARGET_LITTLE_NAME): Ditto. (TARGET_BIG_SYM): Define. (TARGET_BIG_NAME): Define. * targets.c (bfd_elf32_tilegx_vec): Rename... (bfd_elf32_tilegx_le_vec): ... to this. (bfd_elf32_tilegx_be_vec): Declare. (bfd_elf64_tilegx_vec): Rename... (bfd_elf64_tilegx_le_vec): ... to this. (bfd_elf64_tilegx_be_vec): Declare. (_bfd_target_vector): Add / rename above vectors. binutils/testsuite/ * binutils-all/objdump.exp (cpus_expected): Add tilegx. gas/ * tc-tilegx.c (tilegx_target_format): Handle big endian. (OPTION_EB): Define. (OPTION_EL): Define. (md_longopts): Add entries for "EB" and "EL". (md_parse_option): Handle OPTION_EB and OPTION_EL. (md_show_usage): Add -EB and -EL. (md_number_to_chars): New. * tc-tilegx.h (TARGET_BYTES_BIG_ENDIAN): Guard definition with ifndef. (md_number_to_chars): Delete. * configure.tgt (tilegx*be): Handle. * doc/as.texinfo [TILE-Gx]: Document -EB and -EL. * doc/c-tilegx.texi: Ditto. ld/ * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32tilegx_be.c. (ALL_64_EMULATION_SOURCES): Add eelf64tilegx_be.c. (eelf32tilegx_be.c): Add rule to build this file. (eelf64tilegx_be.c): Ditto. * Makefile.in: Regenerate. * configure.tgt (tilegx-*-*): Support big endian. (tilegxbe-*-*): New. * emulparams/elf32tilegx.sh (OUTPUT_FORMAT): Rename. (BIG_OUTPUT_FORMAT): Define. (LITTLE_OUTPUT_FORMAT): Define. * emulparams/elf32tilegx_be.sh: New. * emulparams/elf64tilegx.sh (OUTPUT_FORMAT): Rename. (BIG_OUTPUT_FORMAT): Define. (LITTLE_OUTPUT_FORMAT): Define. * emulparams/elf64tilegx_be.sh: New. ld/testsuite/ * ld-tilegx/reloc-be.d: New. * ld-tilegx/reloc-le.d: New. * ld-tilegx/reloc.d: Delete. * ld-tilegx/tilegx.exp: Test big and little endian.
2012-02-08Implement Intel Transactional Synchronization ExtensionsH.J. Lu1-1/+4
gas/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (HLE_PREFIX): New. (check_hle): Likewise. (_i386_insn): Add have_hle. (cpu_arch): Add .hle and .rtm. (md_assemble): Call check_hle if i.have_hle isn't zero. (parse_insn): Set i.have_hle to 1 for HLE prefix. (output_jump): Support up to 2 byte opcode. * doc/c-i386.texi: Document hle/.hle and rtm/.rtm. gas/testsuite/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/hle-intel.d: New. * gas/i386/hle.d: Likewise. * gas/i386/hle.s: Likewise. * gas/i386/hlebad.l: Likewise. * gas/i386/hlebad.s: Likewise. * gas/i386/rtm-intel.d: Likewise. * gas/i386/rtm.d: Likewise. * gas/i386/rtm.s: Likewise. * gas/i386/x86-64-hle-intel.d: Likewise. * gas/i386/x86-64-hle.d: Likewise. * gas/i386/x86-64-hle.s: Likewise. * gas/i386/x86-64-hlebad.l: Likewise. * gas/i386/x86-64-hlebad.s: Likewise. * gas/i386/x86-64-rtm-intel.d: Likewise. * gas/i386/x86-64-rtm.d: Likewise. * gas/i386/x86-64-rtm.s: Likewise. * gas/i386/i386.exp: Run hle, hle-intel, hlebad x86-64-hle, rtm, rtm-intel, x86-64-hle-intel, x86-64-hlebad, x86-64-rtm and x86-64-rtm-intel. include/opcode/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * i386.h (XACQUIRE_PREFIX_OPCODE): New. (XRELEASE_PREFIX_OPCODE): Likewise. opcodes/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (HLE_Fixup1): New. (HLE_Fixup2): Likewise. (HLE_Fixup3): Likewise. (Ebh1): Likewise. (Evh1): Likewise. (Ebh2): Likewise. (Evh2): Likewise. (Ebh3): Likewise. (Evh3): Likewise. (MOD_C6_REG_7): Likewise. (MOD_C7_REG_7): Likewise. (RM_C6_REG_7): Likewise. (RM_C7_REG_7): Likewise. (XACQUIRE_PREFIX): Likewise. (XRELEASE_PREFIX): Likewise. (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov. (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg, not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use MOD_C6_REG_7 and MOD_C7_REG_7. (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7. (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and xtest. (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX. (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b. * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and CPU_RTM_FLAGS. (cpu_flags): Add CpuHLE and CpuRTM. (opcode_modifiers): Add HLEPrefixOk. * i386-opc.h (CpuHLE): New. (CpuRTM): Likewise. (HLEPrefixOk): Likewise. (i386_cpu_flags): Add cpuhle and cpurtm. (i386_opcode_modifier): Add hleprefixok. * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory operand. Add xacquire, xrelease, xabort, xbegin, xend and xtest. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2012-01-312012-01-31 Paul Brook <paul@codesourcery.com>Paul Brook1-1/+0
gas/ * doc/c-tic6x.c: Fix typo.
2012-01-20Add .d8 suffix support to x86 assemblerH.J. Lu1-2/+2
gas/ 2012-01-20 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (_i386_insn): Replace disp32_encoding with disp_encoding. (md_assemble): Updated. (output_branch): Likewise. (parse_insn): Support .d8 suffix. (build_modrm_byte): Fake zero displacement for .d8 and .d32 suffixes. * doc/c-i386.texi: Document .d8 suffix. gas/testsuite/ 2012-01-20 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/disp32.s: Add tests for .d8 suffix. * gas/i386/x86-64-disp32.s: Likewise. * gas/i386/disp32.d: Updated. * gas/i386/x86-64-disp32.d: Likewise.
2012-01-13Add vmfuncH.J. Lu1-1/+2
gas/ 2012-01-13 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add ".vmfunc". * doc/c-i386.texi: Document vmfunc. gas/testsuite/ 2012-01-13 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run vmfunc and x86-64-vmfunc. * gas/i386/vmfunc.d: New. * gas/i386/vmfunc.s: Likewise. * gas/i386/x86-64-vmfunc.d: Likewise. opcodes/ 2012-01-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (mod_table): Add vmfunc. * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS. (cpu_flags): CpuVMFUNC. * i386-opc.h (CpuVMFUNC): New. (i386_cpu_flags): Add cpuvmfunc. * i386-opc.tbl: Add vmfunc. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2011-12-13 * doc/internals.texi (TC_FORCE_RELOCATION_SUB_SAME): UpdateNick Clifton1-2/+1
to match code.
2011-12-08bfd:Andrew Pinski1-0/+1
2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * archures.c (bfd_mach_mips_octeon2): New macro * bfd-in2.h: Regenerate. * cpu-mips.c (I_mipsocteon2): New enum value. (arch_info_struct): Add bfd_mach_mips_octeon2. * elfxx-mips.c (_bfd_elf_mips_mach): Support E_MIPS_MACH_OCTEON2. (mips_set_isa_flags): Add bfd_mach_mips_octeon2. (mips_mach_extensions): Add bfd_mach_mips_octeon2. gas: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * tc-mips.c (CPU_IS_OCTEON): Add Octeon2. (mips_cpu_info_table): Add Octeon2. * doc/c-mips.texi: Document octeon2 as an acceptable value for -march=. gas/testsuite: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * gas/mips/mips.exp: Add Octeon2 for an architecture. Run octeon2 test. * gas/mips/octeon2.d: New file. * gas/mips/octeon2.s: New file. include/opcode: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. (INSN_OCTEON2): New macro. (CPU_OCTEON2): New macro. (OPCODE_IS_MEMBER): Add Octeon2. opcodes: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * mips-dis.c (mips_arch_choices): Add Octeon2. For "octeon+", just include OcteonP for the insn. * mips-opc.c (IOCT): Include Octeon2. (IOCTP): Include Octeon2. (IOCT2): New macro. (mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad", "ladd", "lai", "laid", "las", "lasd", "law", "lawd". Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard loads are, and add IOCT2 to them. Add "lbx" and "lhux". Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00", "qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03". Add "zcb" and "zcbt".
2011-11-29opcode/Andrew Pinski1-0/+1
2011-11-29 Andrew Pinski <apinski@cavium.com> * mips-dis.c (mips_arch_choices): Add Octeon+. * mips-opc.c (IOCT): Include Octeon+. (IOCTP): New macro. (mips_builtin_opcodes): Add "saa" and "saad". bfd/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * archures.c (bfd_mach_mips_octeonp): New macro. * bfd-in2.h: Regenerate. * bfd/cpu-mips.c (I_mipsocteonp): New enum value. (arch_info_struct): Add bfd_mach_mips_octeonp. * elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp. (mips_mach_extensions): Add bfd_mach_mips_octeonp. include/opcodes/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. (INSN_OCTEONP): New macro. (CPU_OCTEONP): New macro. (OPCODE_IS_MEMBER): Add Octeon+. (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values. gas/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * config/tc-mips.c (CPU_IS_OCTEON): New macro function. (CPU_HAS_SEQ): Change to use CPU_IS_OCTEON. (NO_ISA_COP): Likewise. (macro) <ld_st>: Add support when off0 is true. Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB. (mips_cpu_info_table): Add octeon+. * doc/c-mips.texi: Document octeon+ as an acceptable value for -march=. gas/testsuite/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * gas/mips/mips.exp: Add octeon+ for an architecture. Run octeon-saa-saad test. (run_dump_test_arch): For Octeon architectures, also try octeon@. * gas/mips/octeon-pref.d: Remove -march=octeon from command line. * gas/mips/octeon.d: Likewise. * gas/mips/octeon-saa-saad.d: New file. * gas/mips/octeon-saa-saad.s: New file
2011-11-16 * config/tc-mips.c (mips_cpu_info_table): Add "m14ke" andMaciej W. Rozycki1-0/+2
"m14kec". * doc/c-mips.texi (MIPS architecture options): Add "m14ke" and "m14kec" to the list of -march options.
2011-11-07 * gas/config/tc-arm.c (arm_cpus): Add cortex-a7 entry.Matthew Gretton-Dann1-0/+1
* gas/doc/c-arm.texi (ARM Options): Add cortex-a7 to list of accepted CPUs.
2011-11-04* doc/c-rl78.texi (RL78-Float): Remove unused menu entry.DJ Delorie1-1/+0
2011-11-02 * config/tc-arm.c (md_begin): Remove ARM_PLT32 reloc associatedNick Clifton1-2/+4
with the (PLT) instruction suffix when operating in eabi mode. * doc/c-arm.texi (ARM_Relocations): Extend description of (PLT) suffix. * gas/arm/pic.d: Update expected output.
2011-11-02[.]DJ Delorie5-0/+131
* configure.ac (rl78-*-*) New case. * configure: Regenerate. [bfd] * Makefile.am (ALL_MACHINES): Add cpu-rl78.lo. (ALL_MACHINES_CFILES): Add cpu-rl78.c. (BFD32_BACKENDS): Add elf32-rl78.lo. (BFD32_BACKENDS_CFILES): Add elf32-rl78.c. (Makefile.in): Regenerate. * archures.c (bfd_architecture): Define bfd_arch_rl78. (bfd_archures_list): Add bfd_rl78_arch. * config.bfd: Add rl78-*-elf. * configure.in: Add bfd_elf32_rl78_vec. * reloc.c (bfd_reloc_code_type): Add BFD_RELOC_RL78_* relocations. * targets.c (bfd_target_vector): Add bfd_elf32_rl78_vec. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * cpu-rl78.c: New file. * elf32-rl78.c: New file. [binutils] * readelf.c: Include elf/rl78.h (guess_is_rela): Handle EM_RL78. (dump_relocations): Likewise. (get_machine_name): Likewise. (is_32bit_abs_reloc): Likewise. * NEWS: Mention addition of RL78 support. * MAINTAINERS: Add myself as RL78 port maintainer. [gas] * Makefile.am (TARGET_CPU_CFILES): Add tc-rl78.c. (TARGET_CPU_HFILES): Add rc-rl78.h. (EXTRA_DIST): Add rl78-parse.c and rl78-parse.y. (rl78-parse.c, rl78-parse.h, rl78-parse.o, rl78-defs.h): New rules. * Makefile.in: Regenerate. * configure.in: Add rl78 case. * configure: Regenerate. * configure.tgt: Add rl78 case. * config/rl78-defs.h: New file. * config/rl78-parse.y: New file. * config/tc-rl78.c: New file. * config/tc-rl78.h: New file. * NEWS: Add Renesas RL78. * doc/Makefile.am (c-rl78.texi): New. * doc/Makefile.in: Likewise. * doc/all.texi: Enable it. * doc/as.texi: Add it. [include] * dis-asm.h (print_insn_rl78): Declare. [include/elf] * common.h (EM_RL78, EM_78K0R): New. * rl78.h: New. [include/opcode] * rl78.h: New file. [ld] * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32rl78.c. (+eelf32rl78.c): New rule. * Makefile.in: Regenerate. * configure.tgt: Add rl78-*-* case. * emulparams/elf32rl78.sh: New file. * NEWS: Mention addition of Renesas RL78 support. [opcodes] * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and rl78-dis.c. (MAINTAINERCLEANFILES): Add rl78-decode.c. (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c. * Makefile.in: Regenerate. * configure.in: Add bfd_rl78_arch case. * configure: Regenerate. * disassemble.c: Define ARCH_rl78. (disassembler): Add ARCH_rl78 case. * rl78-decode.c: New file. * rl78-decode.opc: New file. * rl78-dis.c: New file.
2011-10-27bfd:Joern Rennecke1-1/+1
* cpu-epiphany.c: Reinstate full list of Copyright years. * elf32-epiphany.c: Likewise. cpu: * epiphany.cpu, epiphany.opc: Likewise. gas: * config/tc-epiphany.c, config/tc-epiphany.h: Likewise. * doc/c-epiphany.texi: Likewise. include: * elf/epiphany.h: Likewise.
2011-10-26gas:Joern Rennecke1-8/+13
* doc/as.texinfo [EPIPHANY]: Include c-epiphany.texi to avoid duplication. opcodes: * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
2011-10-25bfd:Nick Clifton5-2/+100
* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo . (ALL_MACHINES_CFILES): Add cpu-epiphany.c . (BFD32_BACKENDS): Add elf32-epiphany.lo . (BFD32_BACKENDS_CFILES): Add elf32-epiphany.c . * Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate. * archures.c (bfd_arch_epiphany): Add. (bfd_mach_epiphany16, bfd_mach_epiphany32): Define. (bfd_epiphany_arch): Declare. (bfd_archures_list): Add &bfd_epiphany_arch. * config.bfd (epiphany-*-elf): New target case. * configure.in (bfd_elf32_epiphany_vec): New target vector case. * reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation. (BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise. (BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise. (BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise. * targets.c (bfd_elf32_epiphany_vec): Declare. (_bfd_target_vector): Add bfd_elf32_epiphany_vec. * po/SRC-POTFILES.in, po/bfd.pot: Regenerate. * cpu-epiphany.c, elf32-epiphany.c: New files. binutils: * readelf.c (include "elf/epiphany.h") (guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY. (get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise. (is_16bit_abs_reloc, is_none_reloc): Likewise. * po/binutils.pot: Regenerate. cpu: * cpu/epiphany.cpu, cpu/epiphany.opc: New files. gas: * NEWS: Mention addition of Adapteva Epiphany support. * config/tc-epiphany.c, config/tc-epiphany.h: New files. * Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c . (TARGET_CPU_HFILES): Add config/tc-epiphany.h . * Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate. * configure.in: Also set using_cgen for epiphany. * configure.tgt: Handle epiphany. * doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi . * doc/all.texi: Set EPIPHANY. * doc/as.texinfo: Add EPIPHANY-specific text. * doc/c-epiphany.texi: New file. * po/gas.pot: Regenerate. gas/testsuite: * gas/epiphany: New directory. include: * dis-asm.h (print_insn_epiphany): Declare. * elf/epiphany.h: New file. * elf/common.h (EM_ADAPTEVA_EPIPHANY): Define. ld: * NEWS: Mention addition of Adapteva Epiphany support. * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c . (eelf32epiphany.c): New rule. * Makefile.in: Regenerate. * configure.tgt: Handle epiphany-*-elf. * po/ld.pot: Regenerate. * testsuite/ld-srec/srec.exp: xfail epiphany. * emulparams/elf32epiphany.sh: New file. opcodes: * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h . (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c, epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c . (CLEANFILES): Add stamp-epiphany. (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it. (stamp-epiphany): New rule. * Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate. * configure.in: Handle bfd_epiphany_arch. * disassemble.c (ARCH_epiphany): Define. (disassembler): Handle bfd_arch_epiphany. * epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files. * epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise. * epiphany-opc.h: Likewise.
2011-10-05 * readelf.c (get_machine_dlags): Add support for RX's PID mode.Nick Clifton1-7/+44
* ld-scripts/phdrs.exp: Expect to fail for the RX. * elf32-rx.c: Add support for PID mode. (rx_elf_relocate_section): Add checks for unsafe PID relocations. Include addend in R_RX_SYM relocations. * config/rx-defs.h (rx_pid_register): New. (rx_gp_register): New. * config/rx-parse.y (rx_lex): Add support for %gpreg and %pidreg. (displacement): Add PID support. * config/tc-rx.c (rx_pid_mode): New. (rx_num_int_regs): New. (rx_pid_register): New. (rx_gp_register): New. (options): Add -mpid and -mint-register= options. (md_longopts): Likewise. (md_parse_option): Likewise. (md_show_usage): Likewise. (rx_pid_symbol): New. (rx_pidreg_symbol): New. (rx_gpreg_symbol): New. (md_begin): Support PID. (rx_validate_fix_sub): Support PID. (tc_gen_reloc): Support PID. * doc/c-rx.texi: Document PID support. * rx.h (E_FLAG_RX_PID): New.
2011-09-22Add new sparc options to control instruction availability.David S. Miller1-9/+69
gas/ * config/tc-sparc.c (hwcap_allowed): New. (struct sparc_arch): New field 'hwcap_allowed' containing a bitmask of F_FOO flags which are enabled by the particular arch setting. Add new options that provide explicit access to new instructions. (md_parse_option): Only bump max_architecture if the requested one is larger, or this is the first explicit request. (get_hwcap_name): New function. (sparc_ip): Validate that hwcaps used by an instruction have actually been enabled. * doc/c-sparc.texi: Document new sparc options.
2011-08-19 * doc/as.texinfo: Include c-xstormy16.texi.Nick Clifton1-0/+7
2011-08-09 * config/tc-mips.c (mips_cpu_info_table): Add "m14k" andMaciej W. Rozycki1-0/+2
"m14kc". * doc/c-mips.texi (MIPS architecture options): Add "m14k" and "m14kc" to the list of -march options.
2011-08-09 gas/Maciej W. Rozycki2-0/+21
* config/tc-mips.c (mips_set_options): Add ase_mcu. (mips_opts): Initialise ase_mcu to -1. (ISA_SUPPORTS_MCU_ASE): New macro. (MIPS_CPU_ASE_MCU): Likewise. (is_opcode_valid): Handle MCU. (macro_build, macro): Likewise. (validate_mips_insn, validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_MCU and OPTION_NO_MCU. (md_longopts): Add mmcu and mno-mcu. (md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU. (mips_after_parse_args): Handle MCU. (s_mipsset): Likewise. (md_show_usage): Handle MCU options. * doc/as.texinfo: Document -mmcu and -mno-mcu options. * doc/c-mips.texi: Likewise, and document ".set mcu" and ".set nomcu" directives. gas/testsuite/ * gas/mips/micromips@mcu.d: New test. * gas/mips/mcu.d: Likewise. * gas/mips/mcu.s: New test source. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. (INSN_ASE_MASK): Add the MCU bit. (INSN_MCU): New macro. (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. opcodes/ * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2" and "mips64r2". (print_insn_args, print_insn_micromips): Handle MCU. * micromips-opc.c (MC): New macro. (micromips_opcodes): Add "aclr", "aset" and "iret". * mips-opc.c (MC): New macro. (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
2011-07-28 * dwarf2dbg.c (out_debug_line): Ignore non-normal segments, with aNick Clifton1-0/+10
warning. * doc/as.texinfo (Offset): Document .offset directive. testsuite/ * gas/elf/warn-2.s: New.
2011-07-24bfd/Richard Sandiford2-4/+25
2011-02-25 Chao-ying Fu <fu@mips.com> Ilie Garbacea <ilie@mips.com> Maciej W. Rozycki <macro@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Catherine Moore <clm@codesourcery.com> Richard Sandiford <rdsandiford@googlemail.com> * archures.c (bfd_mach_mips_micromips): New macro. * cpu-mips.c (I_micromips): New enum value. (arch_info_struct): Add bfd_mach_mips_micromips. * elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New prototype. (_bfd_mips_elf_relax_section): Likewise. (_bfd_mips16_elf_reloc_unshuffle): Rename to... (_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS ASE. (_bfd_mips16_elf_reloc_shuffle): Rename to... (_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE. (gprel16_reloc_p): Handle microMIPS ASE. (literal_reloc_p): New function. * elf32-mips.c (elf_micromips_howto_table_rel): New variable. (_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE. (mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle and _bfd_mips_elf_reloc_shuffle changes. (mips_elf_gprel32_reloc): Update comment. (micromips_reloc_map): New variable. (bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE. (mips_elf32_rtype_to_howto): Likewise. (mips_info_to_howto_rel): Likewise. (bfd_elf32_bfd_is_target_special_symbol): Define. (bfd_elf32_bfd_relax_section): Likewise. * elf64-mips.c (micromips_elf64_howto_table_rel): New variable. (micromips_elf64_howto_table_rela): Likewise. (mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle and _bfd_mips_elf_reloc_shuffle changes. (micromips_reloc_map): Likewise. (bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE. (bfd_elf64_bfd_reloc_name_lookup): Likewise. (mips_elf64_rtype_to_howto): Likewise. (bfd_elf64_bfd_is_target_special_symbol): Define. * elfn32-mips.c (elf_micromips_howto_table_rel): New variable. (elf_micromips_howto_table_rela): Likewise. (mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle and _bfd_mips_elf_reloc_shuffle changes. (micromips_reloc_map): Likewise. (bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE. (bfd_elf32_bfd_reloc_name_lookup): Likewise. (mips_elf_n32_rtype_to_howto): Likewise. (bfd_elf32_bfd_is_target_special_symbol): Define. * elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro. (LA25_LUI_MICROMIPS_2): Likewise. (LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise. (LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise. (TLS_RELOC_P): Handle microMIPS ASE. (mips_elf_create_stub_symbol): Adjust value of stub symbol if target is a microMIPS function. (micromips_reloc_p): New function. (micromips_reloc_shuffle_p): Likewise. (got16_reloc_p, call16_reloc_p): Handle microMIPS ASE. (got_disp_reloc_p, got_page_reloc_p): New functions. (got_ofst_reloc_p): Likewise. (got_hi16_reloc_p, got_lo16_reloc_p): Likewise. (call_hi16_reloc_p, call_lo16_reloc_p): Likewise. (hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE. (micromips_branch_reloc_p): New function. (tls_gd_reloc_p, tls_ldm_reloc_p): Likewise. (tls_gottprel_reloc_p): Likewise. (_bfd_mips16_elf_reloc_unshuffle): Rename to... (_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS ASE. (_bfd_mips16_elf_reloc_shuffle): Rename to... (_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE. (_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE. (mips_tls_got_index, mips_elf_got_page): Likewise. (mips_elf_create_local_got_entry): Likewise. (mips_elf_relocation_needs_la25_stub): Likewise. (mips_elf_calculate_relocation): Likewise. (mips_elf_perform_relocation): Likewise. (_bfd_mips_elf_symbol_processing): Likewise. (_bfd_mips_elf_add_symbol_hook): Likewise. (_bfd_mips_elf_link_output_symbol_hook): Likewise. (mips_elf_add_lo16_rel_addend): Likewise. (_bfd_mips_elf_check_relocs): Likewise. (mips_elf_adjust_addend): Likewise. (_bfd_mips_elf_relocate_section): Likewise. (mips_elf_create_la25_stub): Likewise. (_bfd_mips_vxworks_finish_dynamic_symbol): Likewise. (_bfd_mips_elf_gc_sweep_hook): Likewise. (_bfd_mips_elf_is_target_special_symbol): New function. (mips_elf_relax_delete_bytes): Likewise. (opcode_descriptor): New structure. (RA): New macro. (OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise. (b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables. (beq_insn_32): Likewise. (b_insn_16, bz_insn_16): New variables. (BZC32_REG_FIELD): New macro. (bz_rs_insns_32, bz_rt_insns_32): New variables. (bzc_insns_32, bz_insns_16):Likewise. (BZ16_REG, BZ16_REG_FIELD): New macros. (jal_insn_32_bd16, jal_insn_32_bd32): New variables. (jal_x_insn_32_bd32): Likewise. (j_insn_32, jalr_insn_32): Likewise. (ds_insns_32_bd16, ds_insns_32_bd32): Likewise. (jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise. (JR16_REG): New macro. (ds_insns_16_bd16): New variable. (lui_insn): Likewise. (addiu_insn, addiupc_insn): Likewise. (ADDIUPC_REG_FIELD): New macro. (MOVE32_RD, MOVE32_RS): Likewise. (MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise. (move_insns_32, move_insns_16): New variables. (nop_insn_32, nop_insn_16): Likewise. (MATCH): New macro. (find_match): New function. (check_br16_dslot, check_br32_dslot): Likewise. (check_br16, check_br32): Likewise. (IS_BITSIZE): New macro. (check_4byte_branch): New function. (_bfd_mips_elf_relax_section): Likewise. (_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16 and microMIPS modules together. (_bfd_mips_elf_print_private_bfd_data): Handle microMIPS ASE. * reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation. (BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise. (BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise. (BFD_RELOC_MICROMIPS_GPREL16): Likewise. (BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise. (BFD_RELOC_MICROMIPS_HI16_S): Likewise. (BFD_RELOC_MICROMIPS_LO16): Likewise. (BFD_RELOC_MICROMIPS_LITERAL): Likewise. (BFD_RELOC_MICROMIPS_GOT16): Likewise. (BFD_RELOC_MICROMIPS_CALL16): Likewise. (BFD_RELOC_MICROMIPS_GOT_HI16): Likewise. (BFD_RELOC_MICROMIPS_GOT_LO16): Likewise. (BFD_RELOC_MICROMIPS_CALL_HI16): Likewise. (BFD_RELOC_MICROMIPS_CALL_LO16): Likewise. (BFD_RELOC_MICROMIPS_SUB): Likewise. (BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise. (BFD_RELOC_MICROMIPS_GOT_OFST): Likewise. (BFD_RELOC_MICROMIPS_GOT_DISP): Likewise. (BFD_RELOC_MICROMIPS_HIGHEST): Likewise. (BFD_RELOC_MICROMIPS_HIGHER): Likewise. (BFD_RELOC_MICROMIPS_SCN_DISP): Likewise. (BFD_RELOC_MICROMIPS_JALR): Likewise. (BFD_RELOC_MICROMIPS_TLS_GD): Likewise. (BFD_RELOC_MICROMIPS_TLS_LDM): Likewise. (BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise. (BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise. (BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise. (BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise. (BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. binutils/ 2011-02-25 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * readelf.c (get_machine_flags): Handle microMIPS ASE. (get_mips_symbol_other): Likewise. gas/ 2011-02-25 Maciej W. Rozycki <macro@codesourcery.com> Chao-ying Fu <fu@mips.com> Richard Sandiford <rdsandiford@googlemail.com> * config/tc-mips.h (mips_segment_info): Add one bit for microMIPS. (TC_LABEL_IS_LOCAL): New macro. (mips_label_is_local): New prototype. * config/tc-mips.c (S0, S7): New macros. (emit_branch_likely_macro): New variable. (mips_set_options): Add micromips. (mips_opts): Initialise micromips to -1. (file_ase_micromips): New variable. (CPU_HAS_MICROMIPS): New macro. (hilo_interlocks): Set for microMIPS too. (gpr_interlocks): Likewise. (cop_interlocks): Likewise. (cop_mem_interlocks): Likewise. (HAVE_CODE_COMPRESSION): New macro. (micromips_op_hash): New variable. (micromips_nop16_insn, micromips_nop32_insn): New variables. (NOP_INSN): Handle microMIPS ASE. (mips32_to_micromips_reg_b_map): New macro. (mips32_to_micromips_reg_c_map): Likewise. (mips32_to_micromips_reg_d_map): Likewise. (mips32_to_micromips_reg_e_map): Likewise. (mips32_to_micromips_reg_f_map): Likewise. (mips32_to_micromips_reg_g_map): Likewise. (mips32_to_micromips_reg_l_map): Likewise. (mips32_to_micromips_reg_n_map): Likewise. (mips32_to_micromips_reg_h_map): New variable. (mips32_to_micromips_reg_m_map): Likewise. (mips32_to_micromips_reg_q_map): Likewise. (micromips_to_32_reg_h_map): New variable. (micromips_to_32_reg_i_map): Likewise. (micromips_to_32_reg_m_map): Likewise. (micromips_to_32_reg_q_map): Likewise. (micromips_to_32_reg_b_map): New macro. (micromips_to_32_reg_c_map): Likewise. (micromips_to_32_reg_d_map): Likewise. (micromips_to_32_reg_e_map): Likewise. (micromips_to_32_reg_f_map): Likewise. (micromips_to_32_reg_g_map): Likewise. (micromips_to_32_reg_l_map): Likewise. (micromips_to_32_reg_n_map): Likewise. (micromips_imm_b_map, micromips_imm_c_map): New macros. (RELAX_DELAY_SLOT_16BIT): New macro. (RELAX_DELAY_SLOT_SIZE_FIRST): Likewise. (RELAX_DELAY_SLOT_SIZE_SECOND): Likewise. (RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros. (RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise. (RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise. (RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise. (RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise. (RELAX_MICROMIPS_MARK_TOOFAR16): Likewise. (RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise. (RELAX_MICROMIPS_TOOFAR32): Likewise. (RELAX_MICROMIPS_MARK_TOOFAR32): Likewise. (RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise. (INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE. (mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p, fsize and insns. (mips_mark_labels): New function. (mips16_small, mips16_ext): Remove variables, replacing with... (forced_insn_size): ... this. (append_insn, mips16_ip): Update accordingly. (micromips_insn_length): New function. (insn_length): Return the length of microMIPS instructions. (mips_record_mips16_mode): Rename to... (mips_record_compressed_mode): ... this. Handle microMIPS ASE. (install_insn): Handle microMIPS ASE. (reglist_lookup): New function. (is_size_valid, is_delay_slot_valid): Likewise. (md_begin): Handle microMIPS ASE. (md_assemble): Likewise. Update for append_insn interface change. (micromips_reloc_p): New function. (got16_reloc_p): Handle microMIPS ASE. (hi16_reloc_p): Likewise. (lo16_reloc_p): Likewise. (jmp_reloc_p): New function. (jalr_reloc_p): Likewise. (matching_lo_reloc): Handle microMIPS ASE. (insn_uses_reg, reg_needs_delay): Likewise. (mips_move_labels): Likewise. (mips16_mark_labels): Rename to... (mips_compressed_mark_labels): ... this. Handle microMIPS ASE. (gpr_mod_mask): New function. (gpr_read_mask, gpr_write_mask): Handle microMIPS ASE. (fpr_read_mask, fpr_write_mask): Likewise. (insns_between, nops_for_vr4130, nops_for_insn): Likewise. (fix_loongson2f_nop, fix_loongson2f_jump): Likewise. (MICROMIPS_LABEL_CHAR): New macro. (micromips_target_label, micromips_target_name): New variables. (micromips_label_name, micromips_label_expr): New functions. (micromips_label_inc, micromips_add_label): Likewise. (mips_label_is_local): Likewise. (micromips_map_reloc): Likewise. (can_swap_branch_p): Handle microMIPS ASE. (append_insn): Add expansionp argument. Handle microMIPS ASE. (start_noreorder, end_noreorder): Handle microMIPS ASE. (macro_start, macro_warning, macro_end): Likewise. (brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables. (mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise. (BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros. (MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise. (macro_build): Handle microMIPS ASE. Update for append_insn interface change. (mips16_macro_build): Update for append_insn interface change. (macro_build_jalr): Handle microMIPS ASE. (macro_build_lui): Likewise. Simplify. (load_register): Handle microMIPS ASE. (load_address): Likewise. (move_register): Likewise. (macro_build_branch_likely): New function. (macro_build_branch_ccl): Likewise. (macro_build_branch_rs): Likewise. (macro_build_branch_rsrt): Likewise. (macro): Handle microMIPS ASE. (validate_micromips_insn): New function. (expr_const_in_range): Likewise. (mips_ip): Handle microMIPS ASE. (options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS. (md_longopts): Add mmicromips and mno-micromips. (md_parse_option): Handle OPTION_MICROMIPS and OPTION_NO_MICROMIPS. (mips_after_parse_args): Handle microMIPS ASE. (md_pcrel_from): Handle microMIPS relocations. (mips_force_relocation): Likewise. (md_apply_fix): Likewise. (mips_align): Handle microMIPS ASE. (s_mipsset): Likewise. (s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers. (s_dtprel_internal): Likewise. (s_gpword, s_gpdword): Likewise. (s_insn): Handle microMIPS ASE. (s_mips_stab): Likewise. (relaxed_micromips_32bit_branch_length): New function. (relaxed_micromips_16bit_branch_length): New function. (md_estimate_size_before_relax): Handle microMIPS ASE. (mips_fix_adjustable): Likewise. (tc_gen_reloc): Handle microMIPS relocations. (mips_relax_frag): Handle microMIPS ASE. (md_convert_frag): Likewise. (mips_frob_file_after_relocs): Likewise. (mips_elf_final_processing): Likewise. (mips_nop_opcode): Likewise. (mips_handle_align): Likewise. (md_show_usage): Handle microMIPS options. * symbols.c (TC_LABEL_IS_LOCAL): New macro. (S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check. * doc/as.texinfo (Target MIPS options): Add -mmicromips and -mno-micromips. (-mmicromips, -mno-micromips): New options. * doc/c-mips.texi (-mmicromips, -mno-micromips): New options. (MIPS ISA): Document .set micromips and .set nomicromips. (MIPS insn): Update for microMIPS support. gas/testsuite/ 2011-02-25 Maciej W. Rozycki <macro@codesourcery.com> Chao-ying Fu <fu@mips.com> Richard Sandiford <rdsandiford@googlemail.com> * gas/mips/micromips.d: New test. * gas/mips/micromips-branch-delay.d: Likewise. * gas/mips/micromips-branch-relax.d: Likewise. * gas/mips/micromips-branch-relax-pic.d: Likewise. * gas/mips/micromips-size-1.d: Likewise. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips.l: New stderr output. * gas/mips/micromips-branch-delay.l: Likewise. * gas/mips/micromips-branch-relax.l: Likewise. * gas/mips/micromips-branch-relax-pic.l: Likewise. * gas/mips/micromips-size-0.l: New list test. * gas/mips/micromips-size-1.l: New stderr output. * gas/mips/micromips.s: New test source. * gas/mips/micromips-branch-delay.s: Likewise. * gas/mips/micromips-branch-relax.s: Likewise. * gas/mips/micromips-size-0.s: Likewise. * gas/mips/micromips-size-1.s: Likewise. * gas/mips/mips.exp: Run the new tests. * gas/mips/dli.s: Use .p2align. * gas/mips/elf_ase_micromips.d: New test. * gas/mips/elf_ase_micromips-2.d: Likewise. * gas/mips/micromips@abs.d: Likewise. * gas/mips/micromips@add.d: Likewise. * gas/mips/micromips@alnv_ps-swap.d: Likewise. * gas/mips/micromips@and.d: Likewise. * gas/mips/micromips@beq.d: Likewise. * gas/mips/micromips@bge.d: Likewise. * gas/mips/micromips@bgeu.d: Likewise. * gas/mips/micromips@blt.d: Likewise. * gas/mips/micromips@bltu.d: Likewise. * gas/mips/micromips@branch-likely.d: Likewise. * gas/mips/micromips@branch-misc-1.d: Likewise. * gas/mips/micromips@branch-misc-2-64.d: Likewise. * gas/mips/micromips@branch-misc-2.d: Likewise. * gas/mips/micromips@branch-misc-2pic-64.d: Likewise. * gas/mips/micromips@branch-misc-2pic.d: Likewise. * gas/mips/micromips@branch-misc-4-64.d: Likewise. * gas/mips/micromips@branch-misc-4.d: Likewise. * gas/mips/micromips@branch-self.d: Likewise. * gas/mips/micromips@cache.d: Likewise. * gas/mips/micromips@daddi.d: Likewise. * gas/mips/micromips@dli.d: Likewise. * gas/mips/micromips@elf-jal.d: Likewise. * gas/mips/micromips@elf-rel2.d: Likewise. * gas/mips/micromips@elfel-rel2.d: Likewise. * gas/mips/micromips@elf-rel4.d: Likewise. * gas/mips/micromips@jal-svr4pic.d: Likewise. * gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise. * gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise. * gas/mips/micromips@li.d: Likewise. * gas/mips/micromips@loc-swap-dis.d: Likewise. * gas/mips/micromips@loc-swap.d: Likewise. * gas/mips/micromips@mips1-fp.d: Likewise. * gas/mips/micromips@mips32-cp2.d: Likewise. * gas/mips/micromips@mips32-imm.d: Likewise. * gas/mips/micromips@mips32-sf32.d: Likewise. * gas/mips/micromips@mips32.d: Likewise. * gas/mips/micromips@mips32r2-cp2.d: Likewise. * gas/mips/micromips@mips32r2-fp32.d: Likewise. * gas/mips/micromips@mips32r2-sync.d: Likewise. * gas/mips/micromips@mips32r2.d: Likewise. * gas/mips/micromips@mips4-branch-likely.d: Likewise. * gas/mips/micromips@mips4-fp.d: Likewise. * gas/mips/micromips@mips4.d: Likewise. * gas/mips/micromips@mips5.d: Likewise. * gas/mips/micromips@mips64-cp2.d: Likewise. * gas/mips/micromips@mips64.d: Likewise. * gas/mips/micromips@mips64r2.d: Likewise. * gas/mips/micromips@pref.d: Likewise. * gas/mips/micromips@relax-at.d: Likewise. * gas/mips/micromips@relax.d: Likewise. * gas/mips/micromips@rol-hw.d: Likewise. * gas/mips/micromips@uld2-eb.d: Likewise. * gas/mips/micromips@uld2-el.d: Likewise. * gas/mips/micromips@ulh2-eb.d: Likewise. * gas/mips/micromips@ulh2-el.d: Likewise. * gas/mips/micromips@ulw2-eb-ilocks.d: Likewise. * gas/mips/micromips@ulw2-el-ilocks.d: Likewise. * gas/mips/cache.d: Likewise. * gas/mips/daddi.d: Likewise. * gas/mips/mips32-imm.d: Likewise. * gas/mips/pref.d: Likewise. * gas/mips/elf-rel27.d: Handle microMIPS ASE. * gas/mips/l_d.d: Likewise. * gas/mips/l_d-n32.d: Likewise. * gas/mips/l_d-n64.d: Likewise. * gas/mips/ld.d: Likewise. * gas/mips/ld-n32.d: Likewise. * gas/mips/ld-n64.d: Likewise. * gas/mips/s_d.d: Likewise. * gas/mips/s_d-n32.d: Likewise. * gas/mips/s_d-n64.d: Likewise. * gas/mips/sd.d: Likewise. * gas/mips/sd-n32.d: Likewise. * gas/mips/sd-n64.d: Likewise. * gas/mips/mips32.d: Update immediates. * gas/mips/micromips@mips32-cp2.s: New test source. * gas/mips/micromips@mips32-imm.s: Likewise. * gas/mips/micromips@mips32r2-cp2.s: Likewise. * gas/mips/micromips@mips64-cp2.s: Likewise. * gas/mips/cache.s: Likewise. * gas/mips/daddi.s: Likewise. * gas/mips/mips32-imm.s: Likewise. * gas/mips/elf-rel4.s: Handle microMIPS ASE. * gas/mips/lb-pic.s: Likewise. * gas/mips/ld.s: Likewise. * gas/mips/mips32.s: Likewise. * gas/mips/mips.exp: Add the micromips arch. Exclude mips16e from micromips. Run mips32-imm. * gas/mips/jal-mask-11.d: New test. * gas/mips/jal-mask-12.d: Likewise. * gas/mips/micromips@jal-mask-11.d: Likewise. * gas/mips/jal-mask-1.s: Source for the new tests. * gas/mips/jal-mask-21.d: New test. * gas/mips/jal-mask-22.d: Likewise. * gas/mips/micromips@jal-mask-12.d: Likewise. * gas/mips/jal-mask-2.s: Source for the new tests. * gas/mips/mips.exp: Run the new tests. * gas/mips/mips16-e.d: Add --special-syms to `objdump'. * gas/mips/tmips16-e.d: Likewise. * gas/mips/mipsel16-e.d: Likewise. * gas/mips/tmipsel16-e.d: Likewise. * gas/mips/and.s: Adjust padding. * gas/mips/beq.s: Likewise. * gas/mips/bge.s: Likewise. * gas/mips/bgeu.s: Likewise. * gas/mips/blt.s: Likewise. * gas/mips/bltu.s: Likewise. * gas/mips/branch-misc-2.s: Likewise. * gas/mips/jal.s: Likewise. * gas/mips/li.s: Likewise. * gas/mips/mips4.s: Likewise. * gas/mips/mips4-fp.s: Likewise. * gas/mips/relax.s: Likewise. * gas/mips/and.d: Update accordingly. * gas/mips/elf-jal.d: Likewise. * gas/mips/jal.d: Likewise. * gas/mips/li.d: Likewise. * gas/mips/relax-at.d: Likewise. * gas/mips/relax.d: Likewise. include/elf/ 2011-02-25 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * mips.h (R_MICROMIPS_min): New relocations. (R_MICROMIPS_26_S1): Likewise. (R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise. (R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise. (R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise. (R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise. (R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise. (R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise. (R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise. (R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise. (R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise. (R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise. (R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise. (R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise. (R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise. (R_MICROMIPS_TLS_GOTTPREL): Likewise. (R_MICROMIPS_TLS_TPREL_HI16): Likewise. (R_MICROMIPS_TLS_TPREL_LO16): Likewise. (R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise. (R_MICROMIPS_max): Likewise. (EF_MIPS_ARCH_ASE_MICROMIPS): New macro. (STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise. (ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise. (STO_MICROMIPS): Likewise. (ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise. (ELF_ST_IS_COMPRESSED): Likewise. (STO_MIPS_PLT, STO_MIPS_PIC): Rework. (ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise. (STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise. include/opcode/ 2011-02-25 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros. (OP_MASK_STYPE, OP_SH_STYPE): Likewise. (OP_MASK_CODE10, OP_SH_CODE10): Likewise. (OP_MASK_TRAP, OP_SH_TRAP): Likewise. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise. (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise. (OP_MASK_RS3, OP_SH_RS3): Likewise. (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise. (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise. (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise. (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise. (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise. (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise. (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise. (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise. (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise. (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise. (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise. (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise. (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise. (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise. (INSN_WRITE_GPR_S): New macro. (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise. (INSN2_READ_FPR_D): Likewise. (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise. (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise. (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise. (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise. (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise. (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise. (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise. (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise. (CPU_MICROMIPS): New macro. (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values. (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise. (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise. (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise. (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise. (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise. (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise. (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise. (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise. (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise. (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise. (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise. (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise. (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros. (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise. (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise. (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise. (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise. (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise. (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise. (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise. (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise. (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise. (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise. (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise. (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise. (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise. (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise. (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise. (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise. (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise. (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise. (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise. (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise. (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise. (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise. (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise. (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise. (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise. (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise. (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise. (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise. (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise. (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise. (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise. (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise. (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise. (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise. (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise. (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise. (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise. (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise. (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise. (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise. (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise. (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise. (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise. (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise. (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise. (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise. (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise. (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise. (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise. (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise. (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise. (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise. (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise. (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise. (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise. (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise. (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise. (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise. (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise. (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise. (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise. (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise. (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise. (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise. (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise. (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise. (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise. (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise. (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise. (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise. (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise. (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise. (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise. (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise. (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise. (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise. (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise. (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise. (micromips_opcodes): New declaration. (bfd_micromips_num_opcodes): Likewise. ld/testsuite/ 2011-02-25 Catherine Moore <clm@codesourcery.com> Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * lib/ld-lib.exp (run_dump_test): Support distinct assembler flags for the same source named multiple times. * ld-mips-elf/jalx-1.s: New test source. * ld-mips-elf/jalx-1.d: New test output. * ld-mips-elf/jalx-1.ld: New test linker script. * ld-mips-elf/jalx-2-main.s: New test source. * ld-mips-elf/jalx-2-ex.s: Likewise. * ld-mips-elf/jalx-2-printf.s: Likewise. * ld-mips-elf/jalx-2.dd: New test output. * ld-mips-elf/jalx-2.ld: New test linker script. * ld-mips-elf/mips16-and-micromips.d: New test. * ld-mips-elf/mips-elf.exp: Run the new tests opcodes/ 2011-02-25 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * micromips-opc.c: New file. * mips-dis.c (micromips_to_32_reg_b_map): New array. (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise. (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise. (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise. (micromips_to_32_reg_q_map): Likewise. (micromips_imm_b_map, micromips_imm_c_map): Likewise. (micromips_ase): New variable. (is_micromips): New function. (set_default_mips_dis_options): Handle microMIPS ASE. (print_insn_micromips): New function. (is_compressed_mode_p): Likewise. (_print_insn_mips): Handle microMIPS instructions. * Makefile.am (CFILES): Add micromips-opc.c. * configure.in (bfd_mips_arch): Add micromips-opc.lo. * Makefile.in: Regenerate. * configure: Regenerate. * mips-dis.c (micromips_to_32_reg_h_map): New variable. (micromips_to_32_reg_i_map): Likewise. (micromips_to_32_reg_m_map): Likewise. (micromips_to_32_reg_n_map): New macro.
2011-07-22Add initial Intel K1OM support.H.J. Lu1-1/+2
bfd/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am (ALL_MACHINES): Add cpu-k1om.lo. (ALL_MACHINES_CFILES): Add cpu-k1om.c. * Makefile.in: Regenerated. * archures.c (bfd_architecture): Add bfd_arch_k1om. (bfd_k1om_arch): New. (bfd_archures_list): Add &bfd_k1om_arch. * bfd-in2.h: Regenerated. * config.bfd (targ64_selvecs): Add bfd_elf64_k1om_vec if bfd_elf64_x86_64_vec is supported. Add bfd_elf64_k1om_freebsd_vec if bfd_elf64_x86_64_freebsd_vec is supported. (targ_selvecs): Likewise. * configure.in: Support bfd_elf64_k1om_vec and bfd_elf64_k1om_freebsd_vec. * configure: Regenerated. * cpu-k1om.c: New. * elf64-x86-64.c (elf64_k1om_elf_object_p): New. (bfd_elf64_k1om_vec): Likewise. (bfd_elf64_k1om_freebsd_vec): Likewise. * targets.c (bfd_elf64_k1om_vec): New. (bfd_elf64_k1om_freebsd_vec): Likewise. (_bfd_target_vector): Add bfd_elf64_k1om_vec and bfd_elf64_k1om_freebsd_vec. binutils/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (init_dwarf_regnames): Handle EM_K1OM. * elfedit.c (elf_machine): Support EM_K1OM. (elf_class): Likewise. * readelf.c (guess_is_rela): Handle EM_K1OM. (dump_relocations): Likewise. (get_machine_name): Likewise. (get_section_type_name): Likewise. (get_elf_section_flags): Likewise. (process_section_headers): Likewise. (get_symbol_index_type): Likewise. (is_32bit_abs_reloc): Likewise. (is_32bit_pcrel_reloc): Likewise. (is_64bit_abs_reloc): Likewise. (is_64bit_pcrel_reloc): Likewise. (is_none_reloc): Likewise. * doc/binutils.texi: Mention K1OM for elfedit. binutils/testsuite/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * binutils-all/elfedit.exp: Run elfedit-4. * binutils-all/elfedit-4.d: New. gas/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add k1om. (i386_align_code): Handle PROCESSOR_K1OM. (check_cpu_arch_compatible): Check EM_K1OM. (i386_arch): Handle Intel K1OM. (i386_mach): Return bfd_mach_k1om for Intel K1OM. (i386_target_format): Return ELF_TARGET_K1OM_FORMAT for Intel K1OM. * config/tc-i386.h (ELF_TARGET_K1OM_FORMAT): New. (processor_type): Add PROCESSOR_K1OM. * doc/c-i386.texi: Document k1om. gas/testsuite/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/k1om.d: New. * gas/i386/k1om-inval.l: Likewise. * gas/i386/k1om-inval.s: Likewise. * gas/i386/i386.exp: Run k1om-inval and k1om. include/elf/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * common.h (EM_K1OM): New. ld/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am (ALL_64_EMULATIONS): Add eelf_k1om.o and eelf_k1om_fbsd.o (eelf_k1om.c): New. (eelf_k1om_fbsd.c): Likewise. * Makefile.in: Regenerated. * configure.tgt (targ64_extra_emuls): Add elf_k1om if elf_x86_64 is supported. Add elf_k1om_fbsd if elf_x86_64_fbsd is supported. (targ_extra_emuls): Likewise. * emulparams/elf_k1om.sh: New. * emulparams/elf_k1om_fbsd.sh: Likewise. ld/testsuite/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * ld-x86-64/abs-k1om.d: New. * ld-x86-64/protected2-k1om.d: Likewise. * ld-x86-64/protected3-k1om.d: Likewise. * ld-x86-64/x86-64.exp: Run abs-k1om, protected2-k1om and protected3-k1om. opcodes/ 2011-07-22 H.J. Lu <hongjiu.lu@intel.com> * configure.in: Handle bfd_k1om_arch. * configure: Regenerated. * disassemble.c (disassembler): Handle bfd_k1om_arch. * i386-dis.c (print_insn): Handle bfd_mach_k1om and bfd_mach_k1om_intel_syntax. * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS. (cpu_flags): Add CpuK1OM. * i386-opc.h (CpuK1OM): New. (i386_cpu_flags): Add cpuk1om. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2011-07-18Fix a typo in doc/c-i386.texi.H.J. Lu1-1/+1
2011-07-18 H.J. Lu <hongjiu.lu@intel.com> * doc/c-i386.texi: Fix a typo.
2011-07-03ELFOSABI_GNUThomas Schwinge1-2/+3
bfd/ * elf.c (_bfd_elf_set_osabi): Use ELFOSABI_GNU name instead of ELFOSABI_LINUX alias. * elf32-hppa.c: Likewise. * elf32-i370.c: Likewise. * elf64-hppa.c: Likewise. binutils/ * elfedit.c (osabis): Use ELFOSABI_GNU name instead of ELFOSABI_LINUX alias and ELFOSABI_HURD. Add GNU alias. * readelf.c (get_osabi_name, get_symbol_binding, get_symbol_type): Likewise. * doc/binutils.texi <elfedit>: Update accordingly. elfcpp/ * elfcpp.h (ELFOSABI): Add ELFOSABI_GNU with value of ELFOSABI_LINUX, keep ELFOSABI_LINUX as an alias. Remove ELFOSABI_HURD. gas/ * config/obj-elf.c (obj_elf_type): Use ELFOSABI_GNU name instead of ELFOSABI_LINUX alias. * config/tc-ia64.c: Likewise. include/elf/ * common.h (ELFOSABI_GNU): Define, replaces... (ELFOSABI_LINUX): ... this, kept as an alias. (ELFOSABI_HURD): Remove. ld/testsuite/ * ld-ifunc/ifunc.exp: Update for changed output. * ld-unique/unique.exp: Likewise.
2011-06-20 * doc/Makefile.am: (CPU_DOCS): Add c-xstormy16.texi.Nick Clifton4-0/+107
* doc/Makefile.in: Regenerate. * doc/all.texi: Set XSTORMY16. * doc/c-xstormy16.texi: New file.
2011-06-13 * Makefile.am (ALL_MACHINES): Add cpu-tilegx.lo and cpu-tilepro.lo.Nick Clifton6-0/+713
(ALL_MACHINE_CFILES): Add cpu-tilegx.c and cpu-tilepro.c. (BFD32_BACKENDS): Add elf32-tilegx.lo, elf32-tilepro.lo, and elfxx-tilegx.lo. (BFD32_BACKENDS_CFILES): Add elf32-tilegx.c elf32-tilepro.c, and elfxx-tilegx.c. (BFD64_BACKENDS): Add elf64-tilegx.lo. (BFD64_BACKENDS_CFILES): Add elf64-tilegx.c. * Makefile.in: Regenerate. * arctures.c (bfd_architecture): Define bfd_arch_tilepro, bfd_arch_tilegx, bfd_mach_tilepro, bfd_mach_tilegx. (bfd_arch_info): Add bfd_tilegx_arch, bfd_tilepro_arch. (bfd_archures_list): Add bfd_tilegx_arch, bfd_tilepro_arch. bfd-in2.h: Regenerate. * config.bfd: Handle tilegx-*-* and tilepro-*-*. * configure.in: Handle bfd_elf32_tilegx_vec, bfd_elf32_tilepro_vec, and bfd_elf64_tilegx_vec. * configure: Regenerate. * elf-bfd.h (enum elf_target_id): Define TILEGX_ELF_DATA and TILEPRO_ELF_DATA. * libbfd.h: Regenerate. * reloc.c: Add BFD_RELOC_TILEPRO_{COPY, GLOB_DAT, JMP_SLOT, RELATIVE, BROFF_X1, JOFFLONG_X1, JOFFLONG_X1_PLT, IMM8_X0, IMM8_Y0, IMM8_X1, IMM8_Y1, DEST_IMM8_X1, MT_IMM15_X1, MF_IMM15_X1, IMM16_X0, IMM16_X1, IMM16_X0_LO, IMM16_X1_LO, IMM16_X0_HI, IMM16_X1_HI, IMM16_X0_HA, IMM16_X1_HA, IMM16_X0_PCREL, IMM16_X1_PCREL, IMM16_X0_LO_PCREL, IMM16_X1_LO_PCREL, IMM16_X0_HI_PCREL, IMM16_X1_HI_PCREL, IMM16_X0_HA_PCREL, IMM16_X1_HA_PCREL, IMM16_X0_GOT, IMM16_X1_GOT, IMM16_X0_GOT_LO, IMM16_X1_GOT_LO, IMM16_X0_GOT_HI, IMM16_X1_GOT_HI, IMM16_X0_GOT_HA, IMM16_X1_GOT_HA, MMSTART_X0, MMEND_X0, MMSTART_X1, MMEND_X1, SHAMT_X0, SHAMT_X1, SHAMT_Y0, SHAMT_Y1, IMM16_X0_TLS_GD, IMM16_X1_TLS_GD, IMM16_X0_TLS_GD_LO, IMM16_X1_TLS_GD_LO, IMM16_X0_TLS_GD_HI, IMM16_X1_TLS_GD_HI, IMM16_X0_TLS_GD_HA, IMM16_X1_TLS_GD_HA, IMM16_X0_TLS_IE, IMM16_X1_TLS_IE, IMM16_X0_TLS_IE_LO, IMM16_X1_TLS_IE_LO, IMM16_X0_TLS_IE_HI, IMM16_X1_TLS_IE_HI, IMM16_X0_TLS_IE_HA, IMM16_X1_TLS_IE_HA, TLS_DTPMOD32, TLS_DTPOFF32, TLS_TPOFF32} Add BFD_RELOC_TILEGX_{HW0, HW1, HW2, HW3, HW0_LAST, HW1_LAST, HW2_LAST, COPY, GLOB_DAT, JMP_SLOT, RELATIVE, BROFF_X1, JUMPOFF_X1, JUMPOFF_X1_PLT, IMM8_X0, IMM8_Y0, IMM8_X1, IMM8_Y1, DEST_IMM8_X1, MT_IMM14_X1, MF_IMM14_X1, MMSTART_X0, MMEND_X0, SHAMT_X0, SHAMT_X1, SHAMT_Y0, SHAMT_Y1, IMM16_X0_HW0, IMM16_X1_HW0, IMM16_X0_HW1, IMM16_X1_HW1, IMM16_X0_HW2, IMM16_X1_HW2, IMM16_X0_HW3, IMM16_X1_HW3, IMM16_X0_HW0_LAST, IMM16_X1_HW0_LAST, IMM16_X0_HW1_LAST, IMM16_X1_HW1_LAST, IMM16_X0_HW2_LAST, IMM16_X1_HW2_LAST, IMM16_X0_HW0_PCREL, IMM16_X1_HW0_PCREL, IMM16_X0_HW1_PCREL, IMM16_X1_HW1_PCREL, IMM16_X0_HW2_PCREL, IMM16_X1_HW2_PCREL, IMM16_X0_HW3_PCREL, IMM16_X1_HW3_PCREL, IMM16_X0_HW0_LAST_PCREL, IMM16_X1_HW0_LAST_PCREL, IMM16_X0_HW1_LAST_PCREL, IMM16_X1_HW1_LAST_PCREL, IMM16_X0_HW2_LAST_PCREL, IMM16_X1_HW2_LAST_PCREL, IMM16_X0_HW0_GOT, IMM16_X1_HW0_GOT, IMM16_X0_HW1_GOT, IMM16_X1_HW1_GOT, IMM16_X0_HW2_GOT, IMM16_X1_HW2_GOT, IMM16_X0_HW3_GOT, IMM16_X1_HW3_GOT, IMM16_X0_HW0_LAST_GOT, IMM16_X1_HW0_LAST_GOT, IMM16_X0_HW1_LAST_GOT, IMM16_X1_HW1_LAST_GOT, IMM16_X0_HW2_LAST_GOT, IMM16_X1_HW2_LAST_GOT, IMM16_X0_HW0_TLS_GD, IMM16_X1_HW0_TLS_GD, IMM16_X0_HW1_TLS_GD, IMM16_X1_HW1_TLS_GD, IMM16_X0_HW2_TLS_GD, IMM16_X1_HW2_TLS_GD, IMM16_X0_HW3_TLS_GD, IMM16_X1_HW3_TLS_GD, IMM16_X0_HW0_LAST_TLS_GD, IMM16_X1_HW0_LAST_TLS_GD, IMM16_X0_HW1_LAST_TLS_GD, IMM16_X1_HW1_LAST_TLS_GD, IMM16_X0_HW2_LAST_TLS_GD, IMM16_X1_HW2_LAST_TLS_GD, IMM16_X0_HW0_TLS_IE, IMM16_X1_HW0_TLS_IE, IMM16_X0_HW1_TLS_IE, IMM16_X1_HW1_TLS_IE, IMM16_X0_HW2_TLS_IE, IMM16_X1_HW2_TLS_IE, IMM16_X0_HW3_TLS_IE, IMM16_X1_HW3_TLS_IE, IMM16_X0_HW0_LAST_TLS_IE, IMM16_X1_HW0_LAST_TLS_IE, IMM16_X0_HW1_LAST_TLS_IE, IMM16_X1_HW1_LAST_TLS_IE, IMM16_X0_HW2_LAST_TLS_IE, IMM16_X1_HW2_LAST_TLS_IE, TLS_DTPMOD64, TLS_DTPOFF64, TLS_TPOFF64, TLS_DTPMOD32, TLS_DTPOFF32, TLS_TPOFF32} * targets.c (bfd_elf32_tilegx_vec): Declare. (bfd_elf32_tilepro_vec): Declare. (bfd_elf64_tilegx_vec): Declare. (bfd_target_vector): Add bfd_elf32_tilegx_vec, bfd_elf32_tilepro_vec, and bfd_elf64_tilegx_vec. * cpu-tilegx.c: New file. * cpu-tilepro.c: New file. * elf32-tilepro.h: New file. * elf32-tilepro.c: New file. * elf32-tilegx.c: New file. * elf32-tilegx.h: New file. * elf64-tilegx.c: New file. * elf64-tilegx.h: New file. * elfxx-tilegx.c: New file. * elfxx-tilegx.h: New file. * Makefile.am (TARGET_CPU_CFILES): Add config/tc-tilegx.c and config/tc-tilepro.c. (TARGET_CPU_HFILES): Add config/tc-tilegx.h and config/tc-tilepro.h. * Makefile.in: Regenerate. * configure.tgt (tilepro-*-*): New. (tilegx-*-*): Likewise. * config/tc-tilegx.c: New file. * config/tc-tilegx.h: Likewise. * config/tc-tilepro.h: Likewise. * config/tc-tilepro.c: Likewise. * doc/Makefile.am (CPU_DOCS): Add c-tilegx.texi and c-tilepro.texi. * doc/Makefile.in: Regenerate. * doc/all.texi (TILEGX): Define. (TILEPRO): Define. * doc/as.texinfo: Add Tile-Gx and TILEPro documentation. Include c-tilegx.texi and c-tilepro.texi. * doc/c-tilegx.texi: New. * doc/c-tilepro.texi: New. * gas/tilepro/t_constants.s: New file. * gas/tilepro/t_constants.d: Likewise. * gas/tilepro/t_insns.s: Likewise. * gas/tilepro/tilepro.exp: Likewise. * gas/tilepro/t_insns.d: Likewise. * gas/tilegx/tilegx.exp: Likewise. * gas/tilegx/t_insns.d: Likewise. * gas/tilegx/t_insns.s: Likewise. * dis-asm.h (print_insn_tilegx): Declare. (print_insn_tilepro): Likewise. * tilegx.h: New file. * tilepro.h: New file. * common.h: Add EM_TILEGX. * tilegx.h: New file. * tilepro.h: New file. * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32tilegx.c and eelf32tilepro.c. (ALL_64_EMULATION_SOURCES): Add eelf64tilegx.c. (eelf32tilegx.c): New target. (eelf32tilepro.c): Likewise. (eelf64tilegx.c): Likewise. * Makefile.in: Regenerate. * configure.tgt: Handle tilegx-*-* and tilepro-*-*. * emulparams/elf32tilegx.sh: New file. * emulparams/elf64tilegx.sh: New file. * emulparams/elf32tilepro.sh: New file. * ld-elf/eh5.d: Don't run on tile*. * ld-srec/srec.exp: xfail on tile*. * ld-tilegx/external.s: New file. * ld-tilegx/reloc.d: New file. * ld-tilegx/reloc.s: New file. * ld-tilegx/tilegx.exp: New file. * ld-tilepro/external.s: New file. * ld-tilepro/reloc.d: New file. * ld-tilepro/reloc.s: New file. * ld-tilepro/tilepro.exp: New file. * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c, tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c. * Makefile.in: Regenerate. * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch. * configure: Regenerate. * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro. * po/POTFILES.in: Regenerate. * tilegx-dis.c: New file. * tilegx-opc.c: New file. * tilepro-dis.c: New file. * tilepro-opc.c: New file.
2011-06-10Support AVX Programming Reference (June, 2011).H.J. Lu1-1/+6
gas/ 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * config/tc-i386.c (i386_error): Add invalid_vsib_address and unsupported_vector_index_register. (cpu_arch): Add .avx2, .bmi2, .lzcnt and .invpcid. (check_VecOperands): New. (match_template): Call check_VecOperands. Handle invalid_vsib_address and unsupported_vector_index_register. (build_modrm_byte): Support VecSIB. Check register-only source operand when two source operands are swapped. (i386_index_check): Allow Xmm/Ymm index registers. * doc/c-i386.texi: Document avx2/.avx2, bmi2/.bmi2, lzcnt/.lzcnt and invpcid./invpcid. gas/testsuite/ 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * gas/i386/arch-10-1.l: Updated. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.s: Add LZCNT to comments. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/arch-10-lzcnt.d: New. * gas/i386/avx-gather-intel.d: Likewise. * gas/i386/avx-gather.d: Likewise. * gas/i386/avx-gather.s: Likewise. * gas/i386/avx2-intel.d: Likewise. * gas/i386/avx2.d: Likewise. * gas/i386/avx2.s: Likewise * gas/i386/avx256int-intel.d: Likewise. * gas/i386/avx256int.d: Likewise. * gas/i386/avx256int.s: Likewise. * gas/i386/bmi2-intel.d: Likewise. * gas/i386/bmi2.d: Likewise. * gas/i386/bmi2.s: Likewise. * gas/i386/inval-invpcid.l:Likewise. * gas/i386/inval-invpcid.s: Likewise. * gas/i386/invpcid-intel.d: Likewise. * gas/i386/invpcid.d: Likewise. * gas/i386/invpcid.s: Likewise. * gas/i386/x86-64-arch-2-lzcnt.d: Likewise. * gas/i386/x86-64-avx-gather-intel.d: Likewise. * gas/i386/x86-64-avx-gather.d: Likewise. * gas/i386/x86-64-avx-gather.s: Likewise. * gas/i386/x86-64-avx2-intel.d: Likewise. * gas/i386/x86-64-avx2.d: Likewise. * gas/i386/x86-64-avx2.s: Likewise. * gas/i386/x86-64-avx256int-intel.d: Likewise. * gas/i386/x86-64-avx256int.d: Likewise. * gas/i386/x86-64-avx256int.s: Likewise. * gas/i386/x86-64-bmi2-intel.d: Likewise. * gas/i386/x86-64-bmi2.d: Likewise. * gas/i386/x86-64-bmi2.s: Likewise. * gas/i386/x86-64-inval-invpcid.l: Likewise. * gas/i386/x86-64-inval-invpcid.s: Likewise. * gas/i386/x86-64-invpcid-intel.d: Likewise. * gas/i386/x86-64-invpcid.d: Likewise. * gas/i386/x86-64-invpcid.s: Likewise. opcodes/ 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * i386-dis.c (XMGatherQ): New. * i386-dis.c (EXxmm_mb): New. (EXxmm_mb): Likewise. (EXxmm_mw): Likewise. (EXxmm_md): Likewise. (EXxmm_mq): Likewise. (EXxmmdw): Likewise. (EXxmmqd): Likewise. (VexGatherQ): Likewise. (MVexVSIBDWpX): Likewise. (MVexVSIBQWpX): Likewise. (xmm_mb_mode): Likewise. (xmm_mw_mode): Likewise. (xmm_md_mode): Likewise. (xmm_mq_mode): Likewise. (xmmdw_mode): Likewise. (xmmqd_mode): Likewise. (ymmxmm_mode): Likewise. (vex_vsib_d_w_dq_mode): Likewise. (vex_vsib_q_w_dq_mode): Likewise. (MOD_VEX_0F385A_PREFIX_2): Likewise. (MOD_VEX_0F388C_PREFIX_2): Likewise. (MOD_VEX_0F388E_PREFIX_2): Likewise. (PREFIX_0F3882): Likewise. (PREFIX_VEX_0F3816): Likewise. (PREFIX_VEX_0F3836): Likewise. (PREFIX_VEX_0F3845): Likewise. (PREFIX_VEX_0F3846): Likewise. (PREFIX_VEX_0F3847): Likewise. (PREFIX_VEX_0F3858): Likewise. (PREFIX_VEX_0F3859): Likewise. (PREFIX_VEX_0F385A): Likewise. (PREFIX_VEX_0F3878): Likewise. (PREFIX_VEX_0F3879): Likewise. (PREFIX_VEX_0F388C): Likewise. (PREFIX_VEX_0F388E): Likewise. (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise. (PREFIX_VEX_0F38F5): Likewise. (PREFIX_VEX_0F38F6): Likewise. (PREFIX_VEX_0F3A00): Likewise. (PREFIX_VEX_0F3A01): Likewise. (PREFIX_VEX_0F3A02): Likewise. (PREFIX_VEX_0F3A38): Likewise. (PREFIX_VEX_0F3A39): Likewise. (PREFIX_VEX_0F3A46): Likewise. (PREFIX_VEX_0F3AF0): Likewise. (VEX_LEN_0F3816_P_2): Likewise. (VEX_LEN_0F3819_P_2): Likewise. (VEX_LEN_0F3836_P_2): Likewise. (VEX_LEN_0F385A_P_2_M_0): Likewise. (VEX_LEN_0F38F5_P_0): Likewise. (VEX_LEN_0F38F5_P_1): Likewise. (VEX_LEN_0F38F5_P_3): Likewise. (VEX_LEN_0F38F6_P_3): Likewise. (VEX_LEN_0F38F7_P_1): Likewise. (VEX_LEN_0F38F7_P_2): Likewise. (VEX_LEN_0F38F7_P_3): Likewise. (VEX_LEN_0F3A00_P_2): Likewise. (VEX_LEN_0F3A01_P_2): Likewise. (VEX_LEN_0F3A38_P_2): Likewise. (VEX_LEN_0F3A39_P_2): Likewise. (VEX_LEN_0F3A46_P_2): Likewise. (VEX_LEN_0F3AF0_P_3): Likewise. (VEX_W_0F3816_P_2): Likewise. (VEX_W_0F3818_P_2): Likewise. (VEX_W_0F3819_P_2): Likewise. (VEX_W_0F3836_P_2): Likewise. (VEX_W_0F3846_P_2): Likewise. (VEX_W_0F3858_P_2): Likewise. (VEX_W_0F3859_P_2): Likewise. (VEX_W_0F385A_P_2_M_0): Likewise. (VEX_W_0F3878_P_2): Likewise. (VEX_W_0F3879_P_2): Likewise. (VEX_W_0F3A00_P_2): Likewise. (VEX_W_0F3A01_P_2): Likewise. (VEX_W_0F3A02_P_2): Likewise. (VEX_W_0F3A38_P_2): Likewise. (VEX_W_0F3A39_P_2): Likewise. (VEX_W_0F3A46_P_2): Likewise. (MOD_VEX_0F3818_PREFIX_2): Removed. (MOD_VEX_0F3819_PREFIX_2): Likewise. (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise. (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise. (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise. (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise. (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise. (VEX_LEN_0F3A0E_P_2): Likewise. (VEX_LEN_0F3A0F_P_2): Likewise. (VEX_LEN_0F3A42_P_2): Likewise. (VEX_LEN_0F3A4C_P_2): Likewise. (VEX_W_0F3818_P_2_M_0): Likewise. (VEX_W_0F3819_P_2_M_0): Likewise. (prefix_table): Updated. (three_byte_table): Likewise. (vex_table): Likewise. (vex_len_table): Likewise. (vex_w_table): Likewise. (mod_table): Likewise. (putop): Handle "LW". (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode, xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode, vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode. (OP_EX): Likewise. (OP_E_memory): Handle vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. (OP_XMM): Handle vex_vsib_q_w_dq_mode. (OP_VEX): Likewise. * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS, CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID. (opcode_modifiers): Add VecSIB. * i386-opc.h (CpuAVX2): New. (CpuBMI2): Likewise. (CpuLZCNT): Likewise. (CpuINVPCID): Likewise. (VecSIB128): Likewise. (VecSIB256): Likewise. (VecSIB): Likewise. (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid. (i386_opcode_modifier): Add vecsib. * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2011-05-312011-05-31 Paul Brook <paul@codesourcery.com>Paul Brook1-1/+1
gas/ * config/tc-arm.c (arm_cpus): Add Cortex-R5. (arm_extensions): Allow idiv on ARMv7-R. * doc/c-arm.text: Update idiv extension restrictions. gas/testsuite/ * gas/arm/arm-idiv-bad.d: New test. * gas/arm/arm-idiv-bad.s: New test. * gas/arm/arm-idiv-bad.l: New test. * gas/arm/arm-idiv.d: New test. * gas/arm/arm-idiv.s: New test. include/ * opcode/arm.h (ARM_ARCH_V7R_IDIV): Define.
2011-05-16 * config/tc-cris.c (md_parse_option) <OPTION_PIC>: Error if notHans-Peter Nilsson1-1/+2
emitting ELF object. (md_show_usage): Only mention --pic if the assembler can generate ELF objects. * doc/c-cris.texi (CRIS-Opt): Mention that generating ELF is a prerequisite for --pic being a valid option.
2011-05-102011-05-10 Quentin Neill <quentin.neill@amd.com>Quentin Neill1-1/+2
gas/ * config/tc-i386.c (cpu_arch): Add bdver2 and rename PROCESSOR_BDVER1 to PROCESSOR_BDVER. (i386_align_code): Rename PROCESSOR_BDVER1. (processor_type): Ditto. * doc/c-i386.texi: Add bdver2. opcodes/ * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS. * i386-init.h: Regenerated. gas/testsuite/ * gas/i386/i386.exp: Add new bdver2 test cases. * gas/i386/nops-1-bdver2.d: New. * gas/i386/x86-64-nops-1-bdver2.d: New.
2011-05-092011-05-09 Paul Brook <paul@codesourcery.com>Paul Brook1-0/+32
bfd/ * elf32-tic6x.c (is_tic6x_elf_unwind_section_name, elf32_tic6x_fake_sections): New functions. (elf_backend_fake_sections): Define. gas/ * config/tc-tic6x.c (streq): Define. (tic6x_get_unwind): New. (s_tic6x_cantunwind, s_tic6x_handlerdata, s_tic6x_endp, s_tic6x_personalityindex, s_tic6x_personality): New functions. (md_pseudo_table): Add "endp", "handlerdata", "personalityindex", "personality" and "cantunwind". (tic6x_regname_to_dw2regnum, tic6x_frame_initial_instructions, tic6x_start_unwind_section, tic6x_unwind_frame_regs, tic6x_pop_rts_offset_little, tic6x_pop_rts_offset_big, tic6x_unwind_reg_from_dwarf, tic6x_flush_unwind_word, tic6x_unwind_byte, tic6x_unwind_2byte, tic6x_unwind_uleb, tic6x_cfi_startproc, output_exidx_entry, tic6x_output_unwinding, tic6x_cfi_endproc): New. * config/tc-tic6x.h (TIC6X_NUM_UNWIND_REGS): Define. (tic6x_unwind_info): New. (tic6x_segment_info_type): Add marked_pr_dependency, unwind and text_unwind. (TARGET_USE_CFIPOP, tc_regname_to_dw2regnum, tc_cfi_frame_initial_instructions, DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT, tc_cfi_startproc, tc_cfi_endproc, tc_cfi_section_name): Define. * doc/c-tic6x.texi: Document new unwinding directives. * dw2gencfi.c (tc_cfi_startproc, tc_cfi_endproc): Add default definitions. (cfi_insn_data, fde_entry, CFI_adjust_cfa_offset, CFI_return_column, CFI_rel_offset, CFI_escape, CFI_signal_frame, CFI_val_encoded_addr): Move to dw2gencfi.h. (CFI_EMIT_target): Define. (dot_cfi_sections): Check tc_cfi_section_name. (dot_cfi_startproc): Use tc_cfi_startproc. (dot_cfi_endproc): Use tc_cfi_endproc. * dw2gencfi.h (cfi_insn_data, fde_entry, CFI_adjust_cfa_offset, CFI_return_column, CFI_rel_offset, CFI_escape, CFI_signal_frame, CFI_val_encoded_addr): Move to here from dw2gencfi.c. gas/testsuite: * gas/tic6x/unwind-1.d: New test. * gas/tic6x/unwind-1.s: New test. * gas/tic6x/unwind-2.d: New test. * gas/tic6x/unwind-2.s: New test. * gas/tic6x/unwind-3.d: New test. * gas/tic6x/unwind-3.s: New test. * gas/tic6x/unwind-bad-1.d: New test. * gas/tic6x/unwind-bad-1.s: New test. * gas/tic6x/unwind-bad-1.l: New test. * gas/tic6x/unwind-bad-2.d: New test. * gas/tic6x/unwind-bad-2.s: New test. * gas/tic6x/unwind-bad-2.l: New test. include/ * elf/tic6x.h (ELF_STRING_C6000_unwind, ELF_STRING_C6000_unwind_info, ELF_STRING_C6000_unwind_once, ELF_STRING_C6000_unwind_info_once): Define.
2011-05-032011-05-03 Paul Brook <paul@codesourcery.com>Paul Brook1-0/+4
bfd/ * elf32-tic6x.c (elf32_tic6x_howto_table, elf32_tic6x_howto_table_rel, (elf32_tic6x_gc_sweep_hook, elf32_tic6x_relocate_section, elf32_tic6x_check_relocs): Add R_C6000_EHTYPE. gas/ * config/tc-tic6x.c (s_ehtype): New function. (md_pseudo_table): Add "ehtype". (tic6x_fix_adjustable, md_apply_fix): BFD_RELOC_C6000_EHTYPE. * doc/c-tic6x.texi: Document .ehtype directive. ld/testsuite/ * ld-tic6x/ehtype-reloc-1-rel.d: New test. * ld-tic6x/ehtype-reloc-1.d: New test. * ld-tic6x/ehtype-reloc-1.s: New test.
generated by cgit v1.1 at 2024-10-11 01:25:44 +0000