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path: root/gas/config/tc-i386.c
AgeCommit message (Expand)AuthorFilesLines
2023-10-23x86: don't use 32-bit LEA as NOP surrogate in 64-bit codeJan Beulich1-10/+21
2023-10-23x86: i386_generate_nops() may not derive decisions from global variablesJan Beulich1-2/+2
2023-10-23x86: record flag_code in tc_frag_dataJan Beulich1-13/+5
2023-09-27x86: prefer VEX encodings over EVEX ones when possibleJan Beulich1-0/+31
2023-09-27x86: drop cpu_arch_tune_flagsJan Beulich1-22/+4
2023-09-27x86: correct cpu_arch_isa_flags maintenanceJan Beulich1-47/+35
2023-09-27x86: fold FMA VEX and EVEX templatesJan Beulich1-0/+4
2023-09-27x86: fold VAES/VPCLMULQDQ VEX and EVEX templatesJan Beulich1-4/+12
2023-09-27x86: fold certain VEX and EVEX templatesJan Beulich1-5/+97
2023-09-27x86: tighten .insn SAE and broadcast checkingJan Beulich1-2/+3
2023-09-27x86-64: REX.W overrides DATA_PREFIXJan Beulich1-2/+5
2023-09-27x86-64: fix suffix-less PUSH of symbol addressJan Beulich1-1/+6
2023-09-15x86: fold CpuLM and Cpu64Jan Beulich1-3/+3
2023-09-15x86: don't play with cpu_arch_flags.cpu{,no}64Jan Beulich1-37/+6
2023-09-15x86: make code size vs CPU arch checking consistentJan Beulich1-0/+18
2023-09-15x86: re-order update_code_flag()Jan Beulich1-19/+16
2023-09-14x86: support AVX10.1 vector size restrictionsJan Beulich1-38/+175
2023-09-14x86: support AVX10.1/512Jan Beulich1-0/+1
2023-09-08x86: restrict prefix use with .insn VEX/XOP/EVEXJan Beulich1-0/+23
2023-09-01x86: unindent most of set_cpu_arch()Jan Beulich1-151/+154
2023-09-01x86: rename CpuPCLMULJan Beulich1-3/+3
2023-08-18x86: remove indirection from bx[] and di_si[]Jan Beulich1-2/+2
2023-08-11gas: purge md_elf_section_word()Jan Beulich1-9/+0
2023-08-11x86: pack CPU flags in opcode tableJan Beulich1-73/+116
2023-08-02Revert "2.41 Release sources"Sam James1-0/+89
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-89/+0
2023-07-27Support Intel PBNDKBHu, Lin11-0/+1
2023-07-27Support Intel SM4Haochen Jiang1-0/+1
2023-07-27Support Intel SM3Haochen Jiang1-0/+1
2023-07-27Support Intel SHA512Haochen Jiang1-0/+1
2023-07-27Support Intel AVX-VNNI-INT16konglin11-0/+1
2023-07-04x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQJan Beulich1-0/+27
2023-07-04x86: optimize pre-AVX512 {,V}PCMPGT* with identical sourcesJan Beulich1-0/+40
2023-07-04x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sourcesJan Beulich1-0/+17
2023-06-22Revert "x86: Don't check if AVX512 template requires AVX512VL"H.J. Lu1-2/+3
2023-06-20x86: Don't check if AVX512 template requires AVX512VLH.J. Lu1-3/+2
2023-06-16x86: shrink Masking insn attribute to a single bit (boolean)Jan Beulich1-29/+18
2023-05-26x86-64: improve gas diagnostic when no 32-bit target is configuredJan Beulich1-1/+15
2023-05-26x86: figure braces aren't really part of mnemonicsJan Beulich1-8/+24
2023-05-26x86: de-duplicate operand_special_chars[] wrt extra_symbol_chars[]Jan Beulich1-10/+7
2023-05-23x86: don't recognize quoted symbol names as registers or operatorsJan Beulich1-0/+7
2023-05-23Support Intel FRED LKGSZhang, Jun1-0/+2
2023-05-23Revert "Support Intel FRED LKGS"liuhongt1-2/+0
2023-05-23Support Intel FRED LKGSZhang, Jun1-0/+2
2023-05-19x86: permit all relational operators in insn operandsJan Beulich1-1/+1
2023-05-19x86: further adjust extend-to-32bit-address conditionsJan Beulich1-3/+54
2023-05-19x86: tighten extend-to-32bit-address conditionsJan Beulich1-2/+2
2023-05-12x86: slightly simplify i386_parse_name()Jan Beulich1-7/+2
2023-05-12gas: equates of registersJan Beulich1-2/+2
2023-04-28x86/Intel: reduce ELF/PE conditional scope in x86_cons()Jan Beulich1-6/+4
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